CN118051450A

CN118051450A - General input/output interface circuit, system on chip and electronic equipment

Info

Publication number: CN118051450A
Application number: CN202410224269.1A
Authority: CN
Inventors: 洪聪; 冯彦东
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2024-02-28
Filing date: 2024-02-28
Publication date: 2024-05-17

Abstract

The embodiment of the application provides a general input/output interface circuit, a system on a chip and an electronic device, wherein the general input/output interface circuit comprises: the device comprises a receiving module, a communication module and a signal generating module; the receiving module is used for receiving a request signal from the external equipment; the signal generation module is used for generating an interrupt signal according to the request signal and sending the interrupt signal to the processor; the communication module is used for sending a first control signal to the signal generation module when the general input/output interface circuit is powered on so that the signal generation module does not generate an interrupt signal when the general input/output interface circuit is powered on, and sending a second control signal to the signal generation module when the processor responds to the interrupt signal to execute a register reading operation, and clearing the interrupt signal. The general input/output interface circuit provided by the application does not need to set a low-speed clock, so that the power consumption is lower.

Description

General input/output interface circuit, system on chip and electronic equipment

Technical Field

Embodiments of the present application relate to the field of integrated circuits, and in particular, to a universal input/output interface circuit, a system on a chip, and an electronic device.

Background

A general purpose input output interface (General Purpose Input Output, GPIO) circuit is commonly used in a System On Chip (SOC) for exchanging signals between an internal Chip and an external Chip. When the GPIO circuit receives a signal sent by the external device, an interrupt signal is generated, so that the SOC is switched from executing the current task to executing the task requested by the external device.

At present, synchronization of initial states of the GPIO circuits and elimination of interrupt signals are achieved through clock signals generated by a low-speed clock.

However, the low-speed clock needs to generate a clock signal through the crystal oscillator, and the power consumption of the crystal oscillator is higher, so that the power consumption of the conventional general input/output interface circuit is higher.

Disclosure of Invention

In view of the above, the embodiments of the present application provide a general purpose input/output interface circuit, a system on a chip and an electronic device, where the general purpose input/output interface circuit has low power consumption.

According to a first aspect of an embodiment of the present application, there is provided a universal input output interface circuit, comprising: the device comprises a receiving module, a communication module and a signal generating module; the receiving module is used for receiving a request signal from the external equipment; the signal generation module is used for generating an interrupt signal according to the request signal and sending the interrupt signal to the processor; the communication module is used for sending a first control signal to the signal generation module when the general input/output interface circuit is powered on so that the signal generation module does not generate an interrupt signal when the general input/output interface circuit is powered on, and sending a second control signal to the signal generation module when the processor responds to the interrupt signal to execute a register reading operation, and clearing the interrupt signal.

In one possible implementation, the signal generating module includes at least two latches for switching to a signal synchronization state upon receipt of the first control signal, causing the signal generating module to not generate an interrupt signal upon power-up of the universal input output interface circuit, and switching between a signal latching state and a signal synchronization state upon receipt of the second control signal to clear the interrupt signal, wherein a data input of a latch in the signal synchronization state is signal synchronized with an output.

In one possible implementation, the signal generating module includes: a first latch, a second latch, and a first exclusive-or gate; the output end of the receiving module is respectively connected with the data input end of the first latch and the first input end of the first exclusive-OR gate; the output end of the first latch is connected with the data input end of the second latch, the output end of the second latch is connected with the second input end of the first exclusive-OR gate, and the output end of the first exclusive-OR gate is electrically connected with the processor; the control end of the first latch and the control end of the second latch are respectively connected with the communication module; the first latch and the second latch are switched to a signal synchronization state in response to the first control signal so as to synchronize signals of an input end and an output end, and the first exclusive-OR gate does not output an interrupt signal; the second latch responds to the second control signal, is switched from a signal latching state to a signal synchronizing state, and is switched from the signal synchronizing state to the signal latching state, so that the first exclusive-OR gate stops outputting the interrupt signal to clear the interrupt signal.

In one possible implementation, the communication module includes: the first communication unit, the first reset unit, the first AND gate, the second AND gate and the first inverter; the input end of the first AND gate is respectively connected with the output end of the first communication unit and the output end of the first reset unit, and the output end of the first AND gate is connected with the control end of the first latch; the input end of the first inverter is connected with the output end of the first communication unit, the output end of the first inverter and the output end of the first reset unit are respectively connected with the input end of the second AND gate, and the output end of the second AND gate is connected with the control end of the second latch; the first reset unit is configured to output a low level signal when the universal input/output interface circuit is powered on, so that the first and gate outputs a first control signal to the first latch, and the second and gate outputs a first control signal to the second latch; the first reset unit is configured to output a high-level signal after the universal input/output interface circuit is powered on, so that the second and gate outputs the second control signal to the second latch when the communication module outputs a pulse signal.

In one possible implementation, the signal generating module includes: a third latch, a fourth latch, a fifth latch, and a second exclusive-or gate; the output end of the receiving module is respectively connected with the data input end of the third latch and the first input end of the second exclusive-OR gate; the output end of the third latch is connected with the data input end of the fourth latch, the output end of the fourth latch is connected with the data input end of the fifth latch, the output end of the fifth latch is connected with the second input end of the second exclusive-OR gate, and the output end of the second exclusive-OR gate is electrically connected with the processor; the control ends of the third latch, the fifth latch and the fourth latch are respectively connected with the communication module; the third latch, the fourth latch and the fifth latch are switched to a signal synchronization state in response to the first control signal so as to synchronize signals of an input end and an output end, and the second exclusive-OR gate does not output an interrupt signal; the fourth latch responds to the second control signal, is switched from a signal latching state to a signal synchronizing state, and is switched from the signal synchronizing state to the signal latching state, so that the second exclusive-OR gate stops outputting the interrupt signal to clear the interrupt signal.

In one possible implementation, the communication module includes: the second communication unit, the second reset unit, the third AND gate, the fourth AND gate and the second inverter; the input end of the third AND gate is respectively connected with the output end of the second communication unit and the output end of the second reset unit, and the output end of the third AND gate is respectively connected with the control end of the third latch and the control end of the fifth latch; the input end of the second inverter is connected with the output end of the second communication unit, the output end of the second inverter and the output end of the second reset unit are respectively connected with the input end of the fourth AND gate, and the output end of the fourth AND gate is connected with the control end of the fourth latch; the second reset unit is configured to output a low level signal when the universal input/output interface circuit is powered on, so that the third and gate outputs a first control signal to the third latch and the fifth latch, and the fourth and gate outputs a first control signal to the fourth latch; and the second reset unit is used for outputting a high-level signal after the general input/output interface circuit is electrified, so that the fourth AND gate outputs the second control signal to the fourth latch when the communication module outputs the pulse signal.

In one possible implementation, the first control signal includes a low level signal output by the third and gate and a low level signal output by the fourth and gate; the second control signal includes a first pulse signal output by the third and gate and a second pulse signal output by the fourth and gate, the first pulse signal being opposite in potential to the second pulse signal.

In one possible implementation, the second communication unit includes an integrated circuit bus communication unit in the processor.

In one possible implementation manner, the second reset unit includes: the first reset subunit, the second reset subunit and the third AND gate; the output end of the first reset subunit and the output end of the second reset subunit are respectively connected with the input end of a third AND gate, and the output end of the third AND gate is respectively connected with the input ends of the third AND gate and a fourth AND gate; the first reset subunit is configured to output a low level when the universal input/output interface circuit is powered on, and output a high level after the universal input/output interface circuit is powered on; the second reset subunit is configured to output a high level when not triggered, and output a pulse signal when triggered, so as to reset the universal input/output interface circuit.

According to a second aspect of an embodiment of the present application, there is provided a system on a chip, including: a processor and a general purpose input output interface circuit according to the first aspect of an embodiment of the present application; the processor is electrically connected with a signal generation module included in the general input/output interface circuit; the processor is used for responding to the interrupt signal sent by the general input/output interface circuit and executing the register read operation.

According to a third aspect of embodiments of the present application, there is provided an electronic device comprising a system on a chip according to the second aspect of embodiments of the present application.

According to the general input/output interface circuit provided by the embodiment of the application, when the general input/output interface circuit is powered on, the communication module generates the first control signal and sends the first control signal to the signal generation module, so that the signal generation module does not generate an interrupt signal when the general input/output interface circuit is powered on, thereby realizing that the interrupt signal is not generated when the general input/output interface circuit is powered on, and the processor can send the second control signal to the signal generation module through the communication module when the processor executes a register reading operation, thereby eliminating the interrupt signal, realizing the synchronization of the initial state between the general input/output interface circuit and the external equipment and eliminating the interrupt signal, and realizing that a low-speed clock is not adopted when the initial state is synchronized and the interrupt signal is eliminated, so that a crystal oscillator is not required to be arranged in the general input/output interface circuit, namely the crystal oscillator is not required to continuously oscillate to generate a clock signal, and the power consumption is lower.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.

FIG. 1 is a schematic diagram of a general purpose input/output interface circuit according to an embodiment of the present application;

FIG. 2 is a circuit diagram of a signal generating module according to an embodiment of the present application;

fig. 3 is a circuit diagram of a communication module according to an embodiment of the present application;

FIG. 4 is a circuit diagram of another signal generation module according to an embodiment of the present application;

fig. 5 is a circuit diagram of another communication module according to an embodiment of the present application;

Fig. 6 is a circuit diagram of a reset unit according to an embodiment of the present application;

Fig. 7 is a schematic diagram of a system on a chip according to an embodiment of the present application.

Detailed Description

In order to better understand the technical solutions in the embodiments of the present application, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the present application, shall fall within the scope of protection of the embodiments of the present application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.

As mentioned above, the general purpose input output interface (General Purpose Input Output, GPIO) circuit is commonly used in a System On Chip (SOC), and is mainly used for exchanging between an On-Chip signal and an off-Chip signal. When the GPIO circuit receives a signal sent by the external device, an interrupt signal is generated, so that the SOC is switched from executing the current task to executing the task requested by the external device.

When the general input/output interface circuit is powered on, the general input/output interface circuit is in an initial state, and the state of an output signal is unknown when the external device is powered on the general input/output interface circuit, when the output signal of the external device is different from the initial state of the general input/output interface circuit, an interrupt signal is generated, and at the moment, the external device does not send a request signal to the general input/output interface circuit, so that an error interrupt is generated, the processor stops the current work due to the error interrupt, the execution efficiency of the processor is reduced, and therefore, the generation of the error interrupt signal needs to be avoided.

In the related art, when the universal input/output interface circuit is powered on, a clock signal is generated through a low-speed clock arranged in the circuit, so that the universal input/output interface circuit and external equipment synchronize an initial signal state, and erroneous interruption is avoided.

However, the low-speed clock needs to generate a clock signal through a crystal oscillator, the crystal oscillator needs to continuously oscillate in the circuit to generate the clock signal, and the power consumption of the crystal oscillator is high, so that the power consumption of the conventional general input/output interface circuit is high.

In the embodiment of the application, when the general input/output interface circuit is powered on, the communication module generates the first control signal and sends the first control signal to the signal generation module, so that the signal generation module does not generate an interrupt signal when the general input/output interface circuit is powered on, thereby realizing that the interrupt signal is not generated when the general input/output interface circuit is powered on, and the processor can send the second control signal to the signal generation module through the communication module when executing the register reading operation, thereby eliminating the interrupt signal, realizing the synchronization of the initial state between the general input/output interface circuit and the external equipment and the elimination of the interrupt signal.

Fig. 1 is a schematic diagram of a universal input/output interface circuit 100 according to an embodiment of the present application, including: a receiving module 101, a communication module 102 and a signal generating module 103. The receiving module 101 may receive a request signal from the external device 20. The signal generation module 103 may generate an interrupt signal according to the request signal and transmit the interrupt signal to the processor 60. The communication module 102 may send a first control signal to the signal generation module 103 when the general input output interface circuit 100 is powered up so that the signal generation module 103 does not generate an interrupt signal when the general input output interface circuit 100 is powered up, and send a second control signal to the signal generation module 103 when the processor 60 performs a read register operation in response to the interrupt signal, clearing the interrupt signal.

When the universal input/output interface circuit 100 is powered on, the communication module 102 in the universal input/output interface circuit 100 generates a first control signal, where the first control signal may be a high level signal, a low level signal, a pulse signal, etc., after the communication module 102 generates the first control signal, the first control signal is sent to the signal generating module 103, and after the signal generating module 103 receives the first control signal, the initial state of the universal input/output interface circuit 100 and the initial state of the external device 20 may be synchronized, so that no interrupt signal may be generated when the universal input/output interface circuit 100 is powered on.

When the external device 20 has a read-write request or other task request after the power-up is completed, a request signal is sent, the request signal may be a high level signal or a low level signal, the receiving module 101 may receive the request signal sent by the external device 20 and send the request signal to the signal generating module 103, after the signal generating module 103 receives the request signal sent by the receiving module 101, an interrupt signal is generated according to the request signal and sent to the processor 60, so that the processor 60 may execute the task required to be executed by the external device 20 according to the interrupt signal, specifically, after the processor 60 receives the interrupt signal, the processor reads a corresponding register and executes the corresponding task according to the data read from the register.

When the processor 60 reads the register in response to the interrupt signal, the processor 60 sends a second control signal to the signal generating module 103 through the communication module 102, where the second control signal may be a high level signal, a low level signal, a pulse signal, etc., and when the signal generating module 103 receives the second control signal, the interrupt signal is cleared, for example: the interrupt signal is a high level signal, and the high level signal output from the signal generation module 103 is converted into a low level signal after receiving the second control signal, whereby the interrupt can be eliminated. After the next time the receiving module 101 receives the request signal, the above steps are continued to be performed, so as to complete the generation and elimination of the interrupt signal.

In the embodiment of the present application, when the general input/output interface circuit 100 is powered on, the communication module 102 generates the first control signal and sends the first control signal to the signal generating module 103, so that the signal generating module 103 does not generate the interrupt signal when the general input/output interface circuit 100 is powered on, thereby realizing that the interrupt signal is not generated when the general input/output interface circuit 100 is powered on, and the second control signal can be sent to the signal generating module 103 through the communication module 102 when the processor 60 executes the register reading operation, thereby eliminating the interrupt signal, realizing that the synchronization of the initial state and the elimination of the interrupt signal between the general input/output interface circuit 100 and the external device 20 are realized, and because the low-speed clock is not adopted when the initial state is synchronized and the interrupt signal is eliminated, a crystal oscillator is not required to be arranged in the general input/output interface circuit 100, that is, the crystal oscillator is not required to continuously oscillate to generate the clock signal, and therefore the power consumption is low.

In one possible implementation, the signal generating module 103 includes at least two latches for switching to a signal synchronization state upon receiving a first control signal, such that the signal generating module 103 does not generate an interrupt signal upon powering up the universal input output interface circuit 100, and switching between the signal latching state and the signal synchronization state upon receiving a second control signal to clear the interrupt signal, wherein the data input and the output of the latches in the signal synchronization state are signal synchronized.

The signal generating module 103 includes at least two latches, and the at least two latches can be switched to a signal synchronization state after receiving the first control signal sent by the communication module 102, at this time, signal synchronization is performed between the data input end and the output end of the at least two latches, that is, the output signal of the output end is the input signal of the input end, at this time, the initial state of the signal generating module 103 is synchronized with the initial state of the external device 20, and because the initial state of the signal generating module 103 is synchronized with the initial state of the external device 20, no interrupt signal is generated when the universal input/output interface circuit 100 is powered on.

When the power-up is completed, at least two latches are in a signal latch state and/or a signal synchronization state according to the signal input by the control end, for example: the latch can be in a signal latch state, and when the latch is in the signal latch state, the output signal latched after the last signal synchronization is output. The at least two latches may be in different states according to the signal input at the control terminal, for example: one latch is in a signal latch state, the other latches are in a signal sync state, etc. The cooperation of at least two latches can realize that after the power-on is completed, and after the receiving module 101 receives the request signal, an interrupt signal is output.

When the at least two latches receive the second control signal sent by the communication module 102, the latch state and the signal synchronization state can be switched, and as the at least two latches switch between the signal latching state and the signal synchronization state, the state of the general input/output interface can be synchronized with the state of the external device 20, thereby stopping outputting the on-off signal and clearing the interrupt signal.

In the embodiment of the present application, the signal generating module 103 includes at least two latches, and the at least two latches can be switched to the signal synchronization mode when receiving the first control signal, so that initial states of the general input output interface circuit 100 and the external device 20 can be synchronized, no interrupt signal is generated when the general input output interface circuit 100 is powered on, and the state of the latches is switched after receiving the second control signal, so that elimination of the interrupt signal can be realized. Since the latch does not output the interrupt signal according to the first control signal and the second control signal sent by the communication module 102, a crystal oscillator is not required to be set in the universal input/output interface circuit 100, that is, the crystal oscillator is not required to continuously oscillate to generate the clock signal, so that the power consumption is lower.

In the present application, the latch includes a control terminal, an input terminal D, an output terminal Q, and an output terminalOutput end/>When the output terminal Q outputs a high level, the output terminal/>, which is the inverse of the output terminal QOutput low level, whereas when output terminal Q outputs low level, output terminal/>In the present application, the data input terminals of the latches are all input terminals D and the output terminals are all output terminals Q, unless otherwise specified.

Fig. 2 is a circuit diagram of a signal generating module according to an embodiment of the present application. As shown in fig. 2, the signal generation module 103 includes: a first latch 201, a second latch 202 and a first exclusive or gate 203.

The output of the receiving module 101 is connected to the data input of the first latch 201 and to the first input of the first exclusive-or gate 203, respectively. An output of the first latch 201 is connected to a data input of the second latch 202, an output of the second latch 202 is connected to a second input of the first exclusive-or gate 203, and an output of the first exclusive-or gate 203 is electrically connected to the processor 60. The control terminal of the first latch 201 and the control terminal of the second latch 202 are connected to the communication module 102, respectively.

The first latch 201 and the second latch 202 may switch to a signal synchronization state in response to a first control signal to perform signal synchronization of the input terminal and the output terminal such that the first exclusive or gate 203 does not output the interrupt signal, and the second latch 202 may switch from the signal latching state to the signal synchronization state in response to a second control signal and from the signal synchronization state to the signal latching state such that the first exclusive or gate 203 stops outputting the interrupt signal to clear the interrupt signal.

The signal generating module 103 includes a first exclusive-or gate 203, where the principle of the first exclusive-or gate 203 is that a high level signal is output when two input end input level signals are inconsistent, a low level signal is generated when two input end input level signals are consistent, a first input end of the first exclusive-or gate 203 is connected to an output end of the receiving module 101, and a second input end of the first exclusive-or gate 203 is connected to an output end of the second latch 202.

The signal generating module 103 includes a first latch 201 and a second latch 202, when the universal input output interface circuit 100 is powered on, the control terminals of the first latch 201 and the second latch 202 receive the first control signal sent by the communication module 102, at this time, the first latch 201 and the second latch 202 switch to the signal synchronization state in response to the first control signal, and since the data input terminal of the first latch 201 is connected to the receiving module 101, the signal output by the output terminal of the first latch 201 is the initial output signal of the external device 20, for example: the output is a low level signal, and the data input end of the second latch 202 is connected to the output end of the first latch 201, so that the output end of the second latch 202 in the signal synchronization state outputs the initial output signal of the external device 20, and after the universal input/output interface circuit 100 is powered on, the input signals of the first input end and the second input end of the first exclusive-OR gate 203 are consistent due to the synchronization of the initial state, and the low level signal is output, so that no interrupt signal is generated during power on.

When the power-up is completed, the first latch 201 is in a signal synchronization state, the second latch 202 is in a signal latch state, and if the external device 20 sends a request signal, the first latch 201 outputs the request signal because the first latch 201 is in the signal synchronization state, but because the second latch 202 is in the signal latch state, the second latch 202 still outputs an initial output signal of the external device 20, at this time, a first input terminal of the first exclusive-or gate 203 inputs the request signal, a second input terminal inputs the initial output signal, and the input signals of the first input terminal and the second input terminal are inconsistent, a high level signal is output, and the high level signal is output to the processor 60 as an interrupt signal, thereby realizing the generation of the interrupt.

When the processor 60 performs a register reading operation in response to the interrupt signal, the communication module 102 transmits a second control signal to the signal generation module 103. The first latch 201 changes from the signal synchronization state to the signal latch state in response to the second control signal and from the signal latch state to the signal synchronization state, so that the output signal of the first latch 201 is not changed but remains the request signal. The second latch 202 changes from the signal latch state to the signal synchronization state in response to the second control signal, and at this time, the data input terminal and the output terminal of the second latch 202 perform signal synchronization, that is, the output signal of the output terminal changes to the output signal of the first latch 201, that is, the request signal, and at this time, the input signals of the first input terminal and the second input terminal of the first exclusive-OR gate 203 are consistent to each other and are both request signals, so that the output of the high level signal is stopped, the output of the low level signal is converted, and the elimination of the interrupt signal is realized.

After the second latch 202 is switched from the signal latch state to the signal synchronization state, the signal synchronization state is switched to the signal latch state, and at this time, if the signal output by the external device 20 changes again, since the second latch 202 outputs the latched signal, different signals are input to the two ends of the first exclusive-or gate 203, and a high level signal is output, so as to generate an interrupt signal.

In an embodiment of the present application, the signal generating module 103 includes: the first latch 201, the second latch 202 and the first exclusive-or gate 203, the first latch 201 and the second latch 202 switch to a signal synchronization state in response to the first control signal, so that the input terminal and the output terminal perform signal synchronization, and the two input terminals of the first exclusive-or gate 203 input the same signal, thereby enabling no interrupt signal to be generated when the universal input output interface circuit 100 is powered on, and the second latch 202 switches between the signal synchronization state and the signal latching state in response to the second control signal, thereby enabling the interrupt signal to be cleared when the processor 60 reads the register, and enabling the interrupt signal to be eliminated. So that the signal generation module 103 can be made to eliminate the interrupt signal.

Fig. 3 is a circuit diagram of a communication module according to an embodiment of the present application, and as shown in fig. 3, the communication module 102 includes: a first communication unit 701, a first reset unit 702, a first and gate 703, a second and gate 704, and a first inverter 705;

The input end of the first and gate 703 is connected to the output end of the first communication unit 701 and the output end of the first reset unit 702, respectively, the output end of the first and gate 703 is connected to the control end of the first latch, the input end of the first inverter 705 is connected to the output end of the first communication unit 701, the output end of the first inverter 705 and the output end of the first reset unit 702 are connected to the input end of the second and gate 704, respectively, the output end of the second and gate 704 is connected to the control end of the second latch, the first reset unit 702 is configured to output a low level signal when the universal input/output interface circuit is powered on, to cause the first and gate 703 to output a first control signal to the first latch, and to cause the second and gate 704 to output a first control signal to the second latch, and the first reset unit 702 is configured to output a high level signal after the universal input/output interface circuit is powered on, to cause the second and gate 704 to output a second control signal to the second latch when the communication module outputs a pulse signal.

The principle of the AND gate is that when the high level signal is input to both input ends, the AND gate outputs the high level signal, and when the low level signal is input to any one of the input ends, the AND gate outputs the low level signal. The first reset unit 702 outputs a low level signal when the general input output interface circuit 100 is powered on, one input terminal of the first and gate 703 and the second and gate 704 inputs the low level signal, so that the first and gate 703 outputs the low level signal as a first control signal to the control terminal of the first latch 201, and the second and gate 704 outputs the low level signal as a first control signal to the control terminal of the second latch 202, thereby switching the first latch 201 and the second latch 202 to the signal synchronization state.

It should be understood that in the embodiment of the present application, the first latch 201 and the second latch 202 are latches that are through with low level signals and latch with high level signals.

After the general input/output interface circuit 100 is powered on, the first reset unit 702 outputs a high level signal, at this time, since the processor 60 does not complete the register reading operation, the first communication unit 701 outputs a low level signal, one of the two input terminals of the first and gate 703 is input with a low level signal, the other input is input with a high level signal, and the first and gate 703 outputs a low level signal, so that the first latch 201 is in a signal synchronization state. Since the second and gate 704 is provided with the inverter 705, the second latch 202 is in the signal latch state because the first communication unit 701 outputs the high level signal, and at this time, both input terminals of the second and gate 704 input the high level signal, and the second and gate 704 outputs the high level signal.

When the processor 60 finishes the register reading operation, a pulse signal is output through the first communication unit 701, and since the first reset unit 702 outputs a high level signal, the first and gate 703 outputs a high level signal when the high level signal is included in the pulse signal, and since the second and gate 704 outputs a high level signal when the low level signal is included in the pulse signal due to the inverter 705, it is possible to realize that the second control signal is output to control the second latch 202 to switch between the signal latch state and the signal synchronization state.

It should be understood that, the first latch 201 also switches between the signal latch state and the signal synchronization state according to the second control signal, where the first latch 201 is initially in the signal synchronization state, and after receiving the second control signal, the first latch 201 switches from the signal synchronization state to the signal latch state and from the signal latch state to the signal synchronization state, where the first latch 201 may transmit the request signal received by the receiving module 101 to the second latch 202 in the initial state, and the second latch 202 outputs the request signal to the output end of the xor gate after switching to the signal synchronization state, thereby implementing clearing of the interrupt signal.

In an embodiment of the present application, the communication module 102 includes: the first communication unit 701, the first reset unit 702, the first and gate 703, the second and gate 704 and the inverter 705 can output the first control signal through the first and gate 703 and the second and gate 704 when the universal input output interface circuit 100 is powered on through the first reset unit 702 and the inverter 705, so that the input end of the exclusive or gate can input the same signal when each latch is in a signal synchronization state when the universal input output interface circuit 100 is powered on, and no interrupt signal is generated. When the processor 60 reads the register, the first communication unit 701 and the inverter 705 can output the second control signal to the second latch 202, so that the second latch 202 switches states, and sends the request signal to the input end of the exclusive-or gate, thereby realizing the clearing of the interrupt signal. Since the latch does not output the interrupt signal according to the first control signal and the second control signal output by the communication module 102, the general input/output interface circuit 100 does not need to be provided with a crystal oscillator, that is, the crystal oscillator does not need to continuously oscillate to generate the clock signal, so that the power consumption is lower.

Fig. 4 is a circuit diagram of another signal generating module according to an embodiment of the present application. As shown in fig. 4, the signal generation module 103 includes: a third latch 301, a fourth latch 302, a fifth latch 303 and a second exclusive or gate 304.

The output of the receiving module 101 is connected to the data input of the third latch 301 and to the first input of the second exclusive-or gate 304, respectively. The output of the third latch 301 is connected to the data input of the fourth latch 302, the output of the fourth latch 302 is connected to the data input of the fifth latch 303, the output of the fifth latch 303 is connected to the second input of the second exclusive or gate 304, and the output of the second exclusive or gate 304 is electrically connected to the processor 60. The control terminals of the third latch 301, the fifth latch 303 and the fourth latch 302 are respectively connected to the communication module 102.

The third latch 301, the fourth latch 302, and the fifth latch 303 may switch to a signal synchronization state in response to the first control signal to perform signal synchronization of the input terminal and the output terminal so that the second exclusive or gate 304 does not output an interrupt signal. The fourth latch 302 may switch from the signal latch state to the signal synchronous state in response to the second control signal, and switch from the signal synchronous state to the signal latch state, so that the second exclusive-or gate 304 stops outputting the interrupt signal to clear the interrupt signal.

The signal generating module 103 includes a third latch 301, a fourth latch 302, and a fifth latch 303, when the general input output interface circuit 100 is powered on, the control terminals of the third latch 301, the fourth latch 302, and the fifth latch 303 receive the first control signal transmitted from the communication module 102, at which time the third latch 301, the fourth latch 302, and the fifth latch 303 switch to the signal synchronization state in response to the first control signal, and since the data input terminal of the third latch 301 is connected to the receiving module 101, the output signal of the output terminal of the third latch 301 is the initial output signal of the external device 20, for example: the output is a low level signal, and the data input end of the fourth latch 302 is connected to the output end of the third latch 301, so that the output end of the fourth latch 302 in the signal synchronization state outputs the initial output signal of the external device 20, and the fifth latch 303 is similar, and the output end outputs the initial output signal of the external device 20, after the universal input/output interface circuit 100 is powered on, because the input signals of the first input end and the second input end of the second exclusive-OR gate 304 are consistent due to the synchronization of the initial state, the low level signal is output, and no interrupt signal is generated after the power on is realized.

When the power-up is completed, the third latch 301 and the fifth latch 303 are in a signal synchronization state, the fourth latch 302 is in a signal latching state, at this time, if the external device 20 sends a request signal, since the third latch 301 is in a signal synchronization state, the output terminal of the third latch 301 outputs the request signal, but since the fourth latch 302 is in a signal latching state, the fourth latch 302 still outputs the initial output signal of the external device 20, and since the fifth latch 303 is in a signal synchronization state, the output terminal of the fifth latch 303 outputs the initial output signal of the external device 20 output by the fourth latch 302, at this time, the first input terminal of the second exclusive or gate 304 inputs the request signal, the second input terminal inputs the initial output signal, the first input terminal of the exclusive or gate and the second input terminal input signal are inconsistent, and outputs a high level signal, and the high level signal is output as an interrupt signal to the processor 60, thereby realizing the interrupt generation.

When the processor 60 performs a register reading operation in response to the interrupt signal, the communication module 102 transmits a second control signal to the signal generation module 103. The third latch 301 and the fifth latch 303 change from the signal synchronization state to the signal latch state in response to the second control signal and change from the signal latch state to the signal synchronization state, and thus the third latch 301 output signal is not changed and is still the request signal. The fourth latch 302 changes from the signal latch state to the signal synchronization state in response to the second control signal, at this time, the data input terminal and the output terminal of the fourth latch 302 perform signal synchronization, that is, the output signal of the output terminal changes to the request signal output by the third latch 301, and when the fifth latch 303 is in the signal synchronization state, the signal output by the output terminal of the fifth latch 303 is the signal output by the output terminal of the fourth latch 302, that is, the request signal, at this time, the input signals of the first input terminal and the second input terminal of the second exclusive-or gate 304 are both consistent to the request signal, so that the output of the high level signal is stopped, the output of the low level signal is converted, and the elimination of the interrupt signal is realized.

After the fourth latch 302 is switched from the signal latch state to the signal synchronous state, the signal synchronous state is switched to the signal latch state, at this time, if the signal output by the external device 20 changes again, the fourth latch 302 outputs the latched signal, so that no matter the fifth latch 303 is in the signal synchronous state or the signal latch state, the request signal output by the receiving module 101 last time is output, so that different signals are input at two ends of the exclusive or gate to generate a high level signal, and thus an interrupt signal is generated.

In an embodiment of the present application, the signal generating module 103 includes: the third latch 301, the fourth latch 302, the fifth latch 303 and the second exclusive-or gate 304, the third latch 301, the fourth latch 302 and the fifth latch 303 switch to the signal synchronization state in response to the first control signal, so that the input terminal and the output terminal perform signal synchronization, and the two input terminals of the second exclusive-or gate 304 input the same signal, thereby enabling no interrupt signal to be generated when the universal input output interface circuit 100 is powered on, and the fourth latch 302 switches between the signal synchronization state and the signal latching state in response to the second control signal, thereby enabling the interrupt signal to be cleared when the processor 60 reads the registers, and enabling the interrupt signal to be eliminated. So that the signal generation module 103 can eliminate the interrupt signal.

Fig. 5 is a circuit diagram of another communication module according to an embodiment of the present application. As shown in fig. 5, the communication module 102 includes: a second communication unit 401, a second reset unit 402, a third and gate 403, a fourth and gate 404, and a second inverter 405.

The input end of the third and gate 403 is connected to the output end of the second communication unit 401 and the output end of the second reset unit 402, respectively, and the output end of the third and gate 403 is connected to the control end of the third latch 301 and the control end of the fifth latch 303, respectively; an input end of the second inverter 405 is connected to an output end of the second communication unit 401, an output end of the second inverter 405 and an output end of the second reset unit 402 are respectively connected to an input end of the fourth and gate 404, and an output end of the fourth and gate 404 is connected to a control end of the fourth latch 302;

The second reset unit 402 may output a low level signal when the general input output interface circuit 100 connected to the reception module 101 is powered up, to cause the third and gate 403 to output the first control signal to the third latch 301 and the fifth latch 303, and to cause the fourth and gate 404 to output the first control signal to the fourth latch 302. The second reset unit 402 may output a high level signal after the power-on of the universal input output interface circuit 100, so that the fourth and gate 404 outputs a second control signal to the fourth latch 302 when the communication module 102 outputs a pulse signal.

The principle of the AND gate is that when the high level signal is input to both input ends, the AND gate outputs the high level signal, and when the low level signal is input to any one of the input ends, the AND gate outputs the low level signal. The second reset unit 402 outputs a low level signal when the general input output interface circuit 100 is powered on, one input terminal of the third and gate 403 and the fourth and gate 404 inputs the low level signal, and thus the third and gate 403 outputs the low level signal as a first control signal to the control terminals of the third latch 301 and the fifth latch 303, and the fourth and gate 404 outputs the low level signal as a first control signal to the control terminal of the fourth latch 302, whereby the third latch 301, the fourth latch 302, and the fifth latch 303 can be switched to the signal synchronization state.

It should be understood that in the embodiment of the present application, the third latch 301, the fourth latch 302 and the fifth latch 303 are latches in which the low level signal is through, and the high level signal is latched.

After the general input/output interface circuit 100 is powered on, the second reset unit 402 outputs a high level signal, at this time, since the processor 60 does not complete the register reading operation, the second communication unit 401 outputs a low level signal, one of the two input terminals of the third and gate 403 is input with a low level signal, the other input is input with a high level signal, the third and gate 403 outputs a low level signal, and the third latch 301 and the fifth latch 303 are in a signal synchronization state. Since the fourth and gate 404 is provided with the second inverter 405, the second communication unit 401 outputs a high level signal, and at this time, both input terminals of the fourth and gate 404 input a high level signal, and the fourth and gate 404 outputs a high level signal, the fourth latch 302 is in a signal latch state.

When the processor 60 finishes the register reading operation, a pulse signal is output through the second communication unit 401, and since the second reset unit 402 outputs a high level signal, the third and gate 403 outputs a high level signal when the high level signal is included in the pulse signal, and since the second inverter 405 functions, the fourth and gate 404 outputs a high level signal when the low level signal is included in the pulse signal, whereby it is possible to realize that the fourth latch 302 is controlled to switch between the signal latch state and the signal synchronization state by outputting the second control signal.

It should be understood that, the third latch 301 and the fifth latch 303 will also switch between the signal latch state and the signal synchronization state according to the second control signal, where the third latch 301 and the fifth latch 303 are initially in the signal synchronization state, after receiving the second control signal, the third latch 301 may transmit the request signal received by the receiving module 101 to the fourth latch 302 in the initial state, after the fourth latch 302 is switched to the signal synchronization state, output the request signal to the fifth latch 303, and after the fifth latch 303 is switched to the signal synchronization state, output the request signal to the output end of the exclusive or gate, thereby implementing clearing of the interrupt signal.

In an embodiment of the present application, the communication module 102 includes: the second communication unit 401, the second reset unit 402, the third and gate 403, the fourth and gate 404 and the second inverter 405 can output the first control signal through the third and gate 403 and the fourth and gate 404 when the universal input output interface circuit 100 is powered on through the second reset unit 402 and the second inverter 405, so that the input ends of the exclusive-OR gates can input the same signal in a signal synchronization state when the universal input output interface circuit 100 is powered on, and no interrupt signal is generated. When the processor 60 reads the register, the second communication unit 401 and the second inverter 405 can output the second control signal to the fourth latch 302, so that the fourth latch 302 switches states, and sends the request signal to the input end of the exclusive-or gate, thereby realizing the clearing of the interrupt signal. Since the latch does not output the interrupt signal according to the first control signal and the second control signal output by the communication module 102, the general input/output interface circuit 100 does not need to be provided with a crystal oscillator, that is, the crystal oscillator does not need to continuously oscillate to generate the clock signal, so that the power consumption is lower.

In one possible implementation, in the circuit shown in fig. 5, the first control signal includes a low level signal output by the third and gate 403 and a low level signal output by the fourth and gate 404. The second control signal includes a first pulse signal output by the third and gate 403 and a second pulse signal output by the fourth and gate 404, the first pulse signal being opposite in potential to the second pulse signal.

The second reset unit 402 outputs a low level signal when the general input output interface circuit 100 is powered on, one input terminal of the third and gate 403 and the fourth and gate 404 inputs the low level signal, and thus the third and gate 403 outputs the low level signal as a first control signal to the control terminals of the third latch 301 and the fifth latch 303, and the fourth and gate 404 outputs the low level signal as a first control signal to the control terminal of the fourth latch 302, whereby the third latch 301, the fourth latch 302, and the fifth latch 303 can be switched to the signal synchronization state.

When the power-up is completed, the second reset unit 402 outputs a high level signal, at this time, one input terminal of the third and fourth and gates 403 and 404 inputs a high level signal, the communication module 102 initially outputs a low level signal, the other input terminal of the third and gate 403 initially inputs a low level signal, the other input terminal of the fourth and gate 404 initially inputs a high level signal, the third and gate 403 initially outputs a low level signal, the fourth and gate 404 initially outputs a high level signal, and thus the third and fifth latches 301 and 303 are initially in a signal synchronization state, and the fourth latch 302 is initially in a signal latch state.

When the processor 60 performs a register reading operation, the communication module 102 outputs a pulse signal, and the other input terminal of the third and gate 403 inputs a pulse signal with a rising edge and a falling edge, and at this time, the output terminal of the third and gate 403 is a first pulse signal that changes from a low level signal to a high level signal and from the high level signal to the low level signal, so that the third latch 301 and the fifth latch 303 can be switched from the signal synchronization state to the signal latching state and vice versa. Since the pulse signal with the rising edge after the falling edge is input to the other input terminal of the fourth and gate 404 through the second inverter 405, at this time, the output terminal of the fourth and gate 404 outputs the second pulse signal with the signal changed from the high level signal to the low level signal and from the low level signal to the high level signal, so that the fourth latch 302 can be switched from the signal latch state to the signal synchronization state and from the signal synchronization state to the signal latch state, thereby sending the request signal output by the external device 20 to the exclusive or gate, inputting the same signal to the input terminal of the exclusive or gate, stopping outputting the interrupt signal, and achieving the purpose of clearing the interrupt.

In the embodiment of the present application, the first control signal is a low level signal output by the third and fourth and gates 403 and 404, so that each latch is in a signal synchronization state, so that no interrupt signal can be generated when the universal input/output interface circuit 100 is powered on, the second control signal includes pulse signals output by the third and fourth and gates 403 and 404, so that each latch can be switched between a signal latching state and a signal synchronization state, so that interrupt signal can be cleared when the processor 60 performs register reading operation, and since the latch does not output an interrupt signal according to the first control signal and the second control signal, and the first control signal and the second control signal are not clock signals, a crystal oscillator is not required to be set in the universal input/output interface circuit 100, that is, no crystal oscillator is required to continuously oscillate to generate a clock signal, so that power consumption is low.

In one possible implementation, the communication module 102 includes an integrated circuit bus communication unit in the processor 60.

The communication module 102 is a communication module 102 external to the general input/output interface circuit 100, in an example, the general input/output interface circuit 100 may be connected to an integrated circuit bus communication unit in the processor 60 through a line, so that when the processor 60 performs a register reading operation, a second control signal sent by the communication module 102 in the processor 60 may be obtained, and an interrupt signal generated by the general input/output interface circuit 100 is cleared

In the embodiment of the present application, the communication module 102 is an integrated circuit bus communication unit in the processor 60, and the general purpose input/output interface circuit 100 is not provided with the communication module 102, so that the general purpose input/output interface circuit 100 has lower power consumption.

Fig. 6 is a circuit diagram of a reset unit according to an embodiment of the present application. It should be appreciated that the reset unit may be the first reset unit 702 or the second reset unit 402, as shown in fig. 6, including: a first reset subunit 501, a second reset subunit 502, and a third and gate 503.

The output end of the first reset subunit 501 and the output end of the second reset subunit 502 are respectively connected with the input end of the third and gate 503, and the output end of the third and gate 503 is respectively connected with the input ends of the third and gate 403 and the fourth and gate 404.

The first reset subunit 501 may output a low level when the gpio interface circuit 100 is powered up, and output a high level after the gpio interface circuit 100 is powered up. The second reset subunit 502 may output a high level when not triggered and a pulse signal when triggered to reset the gpio interface circuit 100.

The first reset subunit 501 is a power-on reset subunit, and when the power-on reset subunit 501 outputs a low level, the first reset subunit 501 outputs a high level after the power-on.

The second reset subunit 502 is a physical reset subunit, when the second reset subunit 502 is not triggered, the second reset subunit 502 outputs a high level, and when the second reset subunit 502 is triggered, the second reset subunit 502 outputs a pulse signal with a falling edge and a rising edge. It should be appreciated that the second reset subunit 502 is triggered when a reset of the gpio interface circuit 100 is required.

In an embodiment of the present application, the reset unit includes: the first reset subunit 501, the second reset subunit 502, and the third and gate 503, when the universal input output interface circuit 100 is powered on, the third and gate 503 receives the low level output by the first reset subunit 501 and the high level output by the second reset subunit 502, thereby realizing that the low level is output when the universal input output interface circuit is powered on. After the general input output interface circuit 100 is powered on, the third and gate 503 receives the high level output by the first reset subunit 501 and the high level output by the second reset subunit 502, thereby realizing the output of the high level after the power on. The output of the reset signal is achieved so that the third and gate 403 and the fourth and gate 404 can receive the reset signal and generate the first control signal and the second control signal at least according to the reset signal, so that the signal generating module 103 does not output the interrupt signal.

Fig. 7 is a schematic diagram of a system on a chip according to an embodiment of the present application. As shown in fig. 7, the system on chip 600 includes: the processor 60 and the general purpose input output interface circuit 100 in any of the embodiments described above;

The processor 60 is electrically connected to a signal generation module 103 included in the general input/output interface circuit 100;

The processor 60 is configured to perform a register read operation in response to an interrupt signal sent by the universal input output interface circuit 100.

It should be noted that, since the content of the information interaction and the execution process between the processor 60 and the general input/output interface circuit 100 in the system on chip is based on the same concept as that of the foregoing embodiment, the specific content may be referred to the description of the foregoing embodiment, and the description is omitted here.

The embodiment of the application also provides electronic equipment, which comprises the system on a chip in the embodiment.

It should be noted that, according to implementation requirements, each component/step described in the embodiments of the present application may be split into more components/steps, or two or more components/steps or part of operations of the components/steps may be combined into new components/steps, so as to achieve the objects of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the elements and method steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

The above embodiments are only for illustrating the embodiments of the present application, but not for limiting the embodiments of the present application, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of the embodiments of the present application should be defined by the claims.

Claims

1. A universal input output interface circuit, comprising: the device comprises a receiving module, a communication module and a signal generating module;

The receiving module is used for receiving a request signal from the external equipment;

The signal generation module is used for generating an interrupt signal according to the request signal and sending the interrupt signal to the processor;

The communication module is used for sending a first control signal to the signal generation module when the general input/output interface circuit is powered on, so that the signal generation module does not generate an interrupt signal when the general input/output interface circuit is powered on, and sending a second control signal to the signal generation module when the processor responds to the interrupt signal to execute a register reading operation, and clearing the interrupt signal.

2. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,

The signal generating module comprises at least two latches, the at least two latches are used for switching to a signal synchronization state when the first control signal is received, so that the signal generating module does not generate an interrupt signal when the general input/output interface circuit is powered on, and switching between the signal latching state and the signal synchronization state when the second control signal is received, so as to clear the interrupt signal, wherein a data input end and an output end of the latches in the signal synchronization state are in signal synchronization.

3. The circuit of claim 2, wherein the signal generation module comprises: a first latch, a second latch, and a first exclusive-or gate;

the output end of the receiving module is respectively connected with the data input end of the first latch and the first input end of the first exclusive-OR gate;

The output end of the first latch is connected with the data input end of the second latch, the output end of the second latch is connected with the second input end of the first exclusive-OR gate, and the output end of the first exclusive-OR gate is electrically connected with the processor;

the control end of the first latch and the control end of the second latch are respectively connected with the communication module;

the first latch and the second latch are switched to a signal synchronization state in response to the first control signal so as to synchronize signals of an input end and an output end, and the first exclusive-OR gate does not output an interrupt signal;

the second latch responds to the second control signal, is switched from a signal latching state to a signal synchronizing state, and is switched from the signal synchronizing state to the signal latching state, so that the first exclusive-OR gate stops outputting the interrupt signal to clear the interrupt signal.

4. The circuit of claim 3, wherein the circuit comprises a plurality of transistors,

The communication module includes: the first communication unit, the first reset unit, the first AND gate, the second AND gate and the first inverter;

The input end of the first AND gate is respectively connected with the output end of the first communication unit and the output end of the first reset unit, and the output end of the first AND gate is connected with the control end of the first latch;

the input end of the first inverter is connected with the output end of the first communication unit, the output end of the first inverter and the output end of the first reset unit are respectively connected with the input end of the second AND gate, and the output end of the second AND gate is connected with the control end of the second latch;

the first reset unit is configured to output a low level signal when the universal input/output interface circuit is powered on, so that the first and gate outputs a first control signal to the first latch, and the second and gate outputs a first control signal to the second latch;

The first reset unit is configured to output a high-level signal after the universal input/output interface circuit is powered on, so that the second and gate outputs the second control signal to the second latch when the communication module outputs a pulse signal.

5. The circuit of claim 2, wherein the signal generation module comprises: a third latch, a fourth latch, a fifth latch, and a second exclusive-or gate;

The output end of the receiving module is respectively connected with the data input end of the third latch and the first input end of the second exclusive-OR gate;

The output end of the third latch is connected with the data input end of the fourth latch, the output end of the fourth latch is connected with the data input end of the fifth latch, the output end of the fifth latch is connected with the second input end of the second exclusive-OR gate, and the output end of the second exclusive-OR gate is electrically connected with the processor;

the control ends of the third latch, the fifth latch and the fourth latch are respectively connected with the communication module;

The third latch, the fourth latch and the fifth latch are switched to a signal synchronization state in response to the first control signal so as to synchronize signals of an input end and an output end, and the second exclusive-OR gate does not output an interrupt signal;

The fourth latch responds to the second control signal, is switched from a signal latching state to a signal synchronizing state, and is switched from the signal synchronizing state to the signal latching state, so that the second exclusive-OR gate stops outputting the interrupt signal to clear the interrupt signal.

6. The circuit of claim 5, wherein the communication module comprises: the second communication unit, the second reset unit, the third AND gate, the fourth AND gate and the second inverter;

The input end of the third AND gate is respectively connected with the output end of the second communication unit and the output end of the second reset unit, and the output end of the third AND gate is respectively connected with the control end of the third latch and the control end of the fifth latch;

The input end of the second inverter is connected with the output end of the second communication unit, the output end of the second inverter and the output end of the second reset unit are respectively connected with the input end of the fourth AND gate, and the output end of the fourth AND gate is connected with the control end of the fourth latch;

The second reset unit is configured to output a low level signal when the universal input/output interface circuit is powered on, so that the third and gate outputs a first control signal to the third latch and the fifth latch, and the fourth and gate outputs a first control signal to the fourth latch;

and the second reset unit is used for outputting a high-level signal after the general input/output interface circuit is electrified, so that the fourth AND gate outputs the second control signal to the fourth latch when the communication module outputs the pulse signal.

7. The circuit of claim 6, wherein the circuit further comprises a logic circuit,

The first control signal includes a low level signal output by the third and gate and a low level signal output by the fourth and gate;

The second control signal includes a first pulse signal output by the third and gate and a second pulse signal output by the fourth and gate, the first pulse signal being opposite in potential to the second pulse signal.

8. The circuit of claim 6, wherein the second communication unit comprises an integrated circuit bus second communication unit in the processor.

9. The circuit of any of claims 6-8, wherein the second reset unit comprises: the first reset subunit, the second reset subunit and the third AND gate;

The output end of the first reset subunit and the output end of the second reset subunit are respectively connected with the input end of a third AND gate, and the output end of the third AND gate is respectively connected with the input ends of the third AND gate and a fourth AND gate;

the first reset subunit is configured to output a low level when the universal input/output interface circuit is powered on, and output a high level after the universal input/output interface circuit is powered on;

The second reset subunit is configured to output a high level when not triggered, and output a pulse signal when triggered, so as to reset the universal input/output interface circuit.

10. A system on a chip, comprising: a processor and a universal input output interface circuit as claimed in any one of claims 1 to 9;

the processor is electrically connected with a signal generation module included in the general input/output interface circuit;

The processor is used for responding to the interrupt signal sent by the general input/output interface circuit and executing the register read operation.

11. An electronic device comprising the system-on-chip of claim 10.