KR20020071183A - Semiconductor circuit for controlling clock skew and method of clock tree synthesis - Google Patents

Abstract

PURPOSE: A semiconductor circuit for controlling a clock skew is provided to adjust a clock skew between transmission lines by using a reference clock generator and a plurality of transmission lines. CONSTITUTION: A reference clock generation portion(I1) is used for generating a reference clock. A plural of clock transmission lines(BR1,BR2,BR3) are connected with the reference clock generation portion(I1). The clock transmission lines(BR1,BR2,BR3) have clock generation portions for generating new clocks in response to reference clocks. The clock generation portions can be substituted with clock generation portions(IC1,IC2). The clock generation portions(IC1,IC2) are used for adjust a clock skew among clock transmission lines(BR1,BR2,BR3) between the clock transmission lines(BR1,BR2,BR3) in a layout step.

Description

Semiconductor circuit for controlling clock skew and method of clock tree synthesis}

The present invention relates to a semiconductor circuit and a clock tree synthesis method for matching skew between clock transmission lines in a layout phase of a semiconductor circuit design.

When a plurality of transmission lines are connected to one reference clock, the clock skew for driving a device connected to each transmission line may vary due to a difference in resistance between the transmission lines. Therefore, it is necessary to adjust the clock skew between transmission lines in consideration of the clock skew error in the design of the circuit.

1 is a circuit diagram illustrating a clock network including a conventional multiple clock driver.

The conventional clock network shown in FIG. 1 has clock generation means FF1 and FF2 connected to the reference clock generating means I1 and the reference clock generating means I1, respectively, and generate a new clock in response to the reference clock. A plurality of clock transmission lines BR1, BR2, BR3 and combinational logics C0M1, COM11, COM2, COM21, and COM3 are provided.

The first transmission line BR1 is connected to the reference clock generating means I1 and includes first clock generating means FF1 for generating the first clock CLOCK1 in response to the reference clock. The first clock CLOCK1 is applied to the flip flops FF11 and FF12 connected to the end of the first transmission line BR1 through the combinational logic COM11. Here, the combinational logic COM1 and COM11 refers to logic including an inverter, an end gate, and a noah gate that have its own delay time but are not recognized as an end of the clock when the clock passes.

The second transmission line BR2 is connected to the reference clock generating means I1 and includes second clock generating means FF2 for generating a second clock CLOCK2 in response to the reference clock. The second clock CLOCK2 is applied to the flip flops FF21 and FF22 connected to the end of the second transmission line BR2 through the combinational logic COM21.

The third transmission line BR3 passes through the combinational logic COM3 with the reference clock as the third clock CLOCK3 and to the flip flops FF31 and FF32 connected to the end of the third transmission line BR3. Is approved.

Although the first clock CLOCK1, the second clock CLOCK2, and the third clock CLOCK3 are independent clocks having different periods, the skew between these clocks must be matched with each other due to the design of the circuit. In clock tree synthesis (CTS) for skew adjustment between clocks, clock tree synthesis (CTS) is terminated when clock tree synthesis (CTS) is performed from a source clock to reach a clock pin of a clock generator. In other words, the clock pin is the end of the clock tree synthesis (CTS). When a clock tree synthesis (CTS) for adjusting the skew between clocks is performed by using the reference clock generated by the reference clock generator I1 as a source clock, the first clock generator FF1 and the second clock. The clock pin of the generating means FF2 is the end of the clock tree synthesis (CTS). Therefore, the clock skew between the transmission lines of the first clock CLOCK1, the second clock CLOCK2, and the third clock CLOCK3 may not be matched.

Conventionally, clock tree synthesis (CTS) has been performed three times using the first clock CLOCK1, the second clock CLOCK2, and the third clock CLOCK3 as reference clocks. Even in this case, the clock skew in each of the transmission lines BR1, BR2, and BR3 may be set, but the clock skew between each of the transmission lines BR1, BR2, and BR3 may not be set. At this time, in the conventional clock tree synthesis (CTS) method, a delay buffer is manually inserted into each transmission line BR1, BR2, and BR3 to adjust the clock skew between each transmission line. If it is not easy to modify the netlist on the layout, the clock skew between the transmission lines BR1, BR2, BR3 is adjusted while inserting a delay buffer on the netlist. However, even when a delay buffer is inserted in anticipation of a delay value on a netlist, it is generally different from the predicted value in actual simulation. In addition, manually inserting a delay buffer or modifying a netlist in order to match the clock skew between transmission lines BR1, BR2, and BR3 has a problem of time and effort.

An object of the present invention is to provide a semiconductor circuit for matching the clock skew between transmission lines.

Another object of the present invention is to provide a clock tree synthesis method for matching clock skew between transmission lines.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a circuit diagram illustrating a clock network including a conventional multiple clock driver.

2 is a circuit diagram of a semiconductor circuit according to an embodiment of the present invention.

3A is a diagram for explaining the clock generating means of FIG.

3B is a diagram for explaining the substitution clock means of FIG.

4 is a diagram illustrating a clock network by simplifying the substitution clock generating unit of FIG. 2.

According to the present invention for achieving the above technical problem, there is provided a semiconductor circuit comprising a reference clock generating means for generating a reference clock and a plurality of clock transmission lines.

The plurality of clock transmission lines are respectively provided with clock generation means connected to the reference clock generation means and generating a new clock in response to the reference clock. The clock generating means may be replaced by a replacement clock generating means capable of matching a clock skew between the plurality of clock transmission lines in a lay out step.

According to the present invention for achieving the another technical problem, a reference clock generating means for generating a reference clock, and a clock generating means for generating a new clock in response to the reference clock and connected to the reference clock generating means, respectively; A clock tree synthesizing method for matching clock skew between a plurality of clock transmission lines, the method comprising: (a) performing a simulation for adjustment of clock skew from the reference clock generating means; and (b) the clock generating means at lay out. Replacing (c) with a constant replacement clock generating means, (c) performing a simulation for adjusting the clock skew from the reference clock generating means and adjusting the skew, and (d) replacing the replacing clock generating means with the clock generating means. The clock tree synthesizing method comprising the steps of: It is.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a circuit diagram of a semiconductor circuit according to an embodiment of the present invention.

2, a semiconductor circuit according to an embodiment of the present invention is connected to a reference clock generating means I1 and a reference clock generating means I1 for generating a reference clock, respectively, and generates a new clock in response to the reference clock. A plurality of clock transmission lines BR1, BR2, BR3 having a clock generating means is provided. The clock generating means may be replaced by the replacement clock generating means IC1 and IC2 capable of matching the clock skew between the plurality of clock transmission lines BR1, BR2, and BR3 in the layout step.

3A is a diagram for explaining the clock generating means of FIG.

3B is a diagram for explaining the substitution clock means of FIG.

Hereinafter, an operation of a semiconductor circuit and a clock tree synthesis method according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

The principle of clock tree synthesis for matching skew between clock transmission lines BR1, BR2, and BR3 respectively connected to the reference clock generating means I1 is that the clock tree synthesis is stopped because it is recognized as the end of the reference clock in the layout step. The clock generating means is replaced with a clock generating means having a combinational logic characteristic that is not recognized as the end of the reference clock. The clock generation means having such a combinational logic characteristic is the replacement clock generation means IC1 and IC2, and the clock tree synthesis is not completed by the replacement clock generation means IC1 and IC2, and the replacement clock generation means IC1 and IC2 are used. It is carried out through and thus the skew between each transmission line BR1, BR2, BR3 can be adjusted at once.

First, clock tree synthesis is performed to match the clock skew of each of the transmission lines BR1, BR2, and BR3 using the reference clock generating means I1 as a source clock. At this time, the clock generation means is replaced with the replacement clock generation means IC1 and IC2.

Substitution clock generating means is described with reference to Figs. 3A and 3B.

The general clock generating means 301 receives a reference clock and generates a clock by itself. The clock generating means 301 has characteristics of an element that stores and transmits information by a clock edge. Therefore, clock tree synthesis for skew adjustment is performed only from the reference clock generating means I1 to the clock generating means 301. The clock tree synthesis is performed again by the new clock CLOCK1 generated from the clock generator 301. Therefore, the skew of the clock is different between the transmission lines BR1, BR2, and BR3 after the clock generation means 301 where new clock tree synthesis is performed. In order to solve this problem, the replacement clock generating means IC1 and IC2 are replaced.

The replacement clock generating means 303 has the same physical structure and timing characteristics as the clock generating means 301, and the characteristic of the clock input terminal CK, which is recognized as the end of the clock when the clock skew is adjusted, is not recognized as the end of the clock. Changed to the data input terminal characteristics.

Specifically, first, the timing arc present in the clock generating means CK is kept the same. That is, in the clock generating means 301, there is no timing arc between the input terminal D and the output terminal Q and there is a timing arc between the clock terminal CK and the output terminal Q. The clock generating means 303 is also maintained as it is.

Second, the capacitance of the input terminal of the clock generating means 301 is also maintained as it is.

Third, the characteristic of the clock terminal CK of the clock generating means 301 is changed to the characteristic of the general data input terminal in the substitution clock generating means 303. Therefore, the clock terminal of the substitution clock generating means 303 is not recognized as the end of the clock tree synthesis with respect to the reference clock, and the reference clock is continuously transmitted through the substitution clock generating means 303.

The substitution clock generating means 303 having such a characteristic eventually has the same characteristics as the combinational logic. Therefore, when the clock generation means 301 is replaced by the replacement clock generation means 303, clock tree synthesis for adjusting the clock skew between the transmission lines BR1, BR2, and BR3 may be performed at once.

4 is a diagram illustrating a clock network by simplifying the substitution clock generating unit of FIG. 2.

Since the replacement clock generating means having the above-described characteristics has characteristics of the combinational logic, it can be combined with the combinational logics COM1 and COM2 included in each of the transmission lines BR1, BR2, and BR3. .

That is, when the combinational logic COM1 and the replacement clock generation means IC1 of the first transmission line BR1 are combined in terms of clock tree synthesis, they may be represented as new combinational logic COMIC1. Combination of the combinational logic COM2 of the second transmission line BR2 and the replacement clock generating means IC2 in terms of clock tree synthesis may be represented as a new combinational logic COMIC2.

When the clock tree synthesis for adjusting the clock skew is performed from the reference clock generating means I1 to the first transmission line BR1, the reference clock does not recognize the clock terminal of the replacement clock generating means as the end of the clock. It passes through the logic logics COMIC1 and COM11 and is applied to the flip flops FFII and FF12 at the end of the first transmission line BR1. Similarly, the reference clock is also applied to the flip flops FF21, FF22, FF31, and FF32 at the end of the transmission line in the second transmission line BR2 and the third transmission line BR3. Therefore, it is possible to adjust the skew of the clock at a time from the reference clock generating means I1 to the end of each transmission line BR1, BR2, BR3, and to adjust the skew between each transmission line BR1, BR2, BR3. .

If the replacement clock generating means is replaced with the original clock generating means after adjusting the skew of the clock, the plurality of transmission lines BR1, BR2, which are connected to one reference clock generating means I1 and include the clock generating means, The clock skew between BR3) can be adjusted at once.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor circuit and the method according to the present invention can adjust the clock skew between each clock transmission line including the clock generating means without the trouble of adjusting the clock skew by inserting the delay buffer by modifying the netlist or by manual operation. have.

Claims (6)

Reference clock generating means for generating a reference clock; And A plurality of clock transmission lines each connected to said reference clock generating means and having clock generating means for generating a new clock in response to said reference clock, The clock generation means, And a replacement clock generating means capable of matching a clock skew between the plurality of clock transmission lines in a lay out step. The method of claim 1, wherein the clock generating means, It is a flip-flop, The semiconductor circuit characterized by the above-mentioned. The method of claim 1, wherein the replacement clock generating means, A semiconductor having a physical structure and a timing characteristic identical to that of the clock generating means and changing a characteristic of a clock input terminal recognized as an end of a clock when adjusting the clock skew to a characteristic of a data input terminal not recognized as an end of a clock; Circuit. A reference clock generating means for generating a reference clock, and a clock skew between a plurality of clock transmission lines each having a clock generating means connected to said reference clock generating means and generating a new clock in response to said reference clock; In the clock tree synthesis method, (a) performing a simulation for adjusting the clock skew from the reference clock generating means; (b) replacing the clock generation means with a constant replacement clock generation means during lay out; (c) performing simulation for adjusting the clock skew from the reference clock generating means and adjusting the skew; (d) replacing said replacing clock generating means with said clock generating means. The method of claim 4, wherein the clock generating means, A clock tree synthesizing method, characterized in that the flip-flop. The method of claim 4, wherein the replacement clock generating means, A clock having a physical structure and a timing characteristic identical to that of the clock generating means and changing a characteristic of a clock input terminal recognized as an end of the clock when adjusting the clock skew to a characteristic of a data input terminal not recognized as an end of the clock; Tree Synthesis Method.