JP2000048727A - Plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent unnecessary electric discharge by suppressing the movement of electric charge. SOLUTION: In this plasma display panel(PDP) 1, a first and second electrodes X, Y are disposed in parallel so as to constitute a main electrode pair 12 for generating a surface discharge on each line of a matrix display, and a plurality of barrier ribs 29 in a form of strips on a plan view are provided through the whole screen in a form of stripes so as to partition each line into a sell. In this case, PDP 1 is positioned so that each barrier rib 29 extends in the direction slanting against the first and second electrodes X, Y.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) for performing matrix display by surface discharge along a screen.

[0002] With the practical use of color screens, PDPs have come to be widely used in applications such as television images and computer monitors. The structure and manufacturing technology are being developed to further expand the applications of such PDPs.

[0003]

2. Description of the Related Art As a color display device, an AC type PDP of a three-electrode surface discharge type has been commercialized. The surface discharge type referred to here is a type in which a lighting state is maintained using wall charges.
First and second alternating anode or cathode in C drive
Are arranged in parallel with one inner surface of the substrate pair. According to this type, the phosphor layer for color display is provided on the second substrate facing the first substrate on which the main electrode pairs are arranged, so that deterioration of the phosphor layer due to ion bombardment during discharge is prevented. It is possible to reduce the length and extend the life.

In the surface discharge type PDP, since the main electrodes extend in the same direction, third electrodes for selecting individual cells and barrier ribs (barrier ribs) for dividing a discharge space for each column are provided.
is necessary.

FIG. 6 is a plan view showing an arrangement relationship between electrodes and partition walls in a conventional PDP. In the conventional PDP 90, a band-shaped address electrode Ap as a third electrode and a band-shaped partition 29p in a plan view are arranged so as to be orthogonal to the main electrodes Xp and Yp extending in the left-right direction in the drawing. Main electrode X
p and Yp are arranged in pairs for each row, and the dimension g of the electrode gap (referred to as a slit) in each row is selected to a value at which surface discharge occurs. The screen is partitioned for each column by the partition wall 29p, and each row is partitioned for each cell Cp. One address electrode Ap is arranged in each column.

Since the arrangement pattern of the partition walls 29p is a so-called striped pattern, the discharge space in each column is continuous across all rows. Therefore, in order to prevent discharge coupling in the column direction, the value b of the electrode gap (referred to as an inverted slit) between adjacent rows is selected to be sufficiently larger than the value of the slit g. That is, in the column direction, the cells Cp are defined by the spatial distance.

For display, the main electrode Yp is used as a scan electrode for selecting a row, and a discharge for addressing is generated between the main electrode Yp and the address electrode Ap. Cell C to be lit by performing line-sequential addressing
After a predetermined amount of wall charge is formed on p, a lighting sustaining voltage having an alternating polarity is simultaneously applied to the main electrode pairs in all rows to periodically generate a surface discharge.

[0008]

In the conventional PDP, as the arrangement interval of the main electrodes Xp and Yp becomes narrower due to the high definition of the screen, space charge moves to another cell Cp adjacent in the column direction, particularly at the time of addressing. However, there is a problem that an addressing error is likely to occur. That is, the margin of the driving voltage for performing the correct display is reduced.

[0009] If the discharge space is divided into cells by making the partition walls grid-like, the movement of space charges can be suppressed reliably. However, in that case, it is necessary to perform the assembly in a discharge gas atmosphere, and it becomes difficult to align the partition and the main electrode, so that the cost is greatly increased.

SUMMARY OF THE INVENTION An object of the present invention is to prevent unnecessary discharge by suppressing movement of electric charges.

[0011]

A PDP according to the first aspect of the present invention.
The first and second electrodes are arranged so as to form a main electrode pair for generating a surface discharge for each row of the matrix display, and a plurality of partition walls having a band shape in plan view form each row over the entire area of the screen for each cell. Of a surface discharge structure provided in a stripe pattern
DP, wherein each of the partition walls is the first and second partition walls.
Extend along a direction inclined with respect to the electrode.

In the PDP according to the second aspect of the present invention, the third electrodes for selecting columns are arranged in the screen in parallel with the partition walls. In the PDP according to the third aspect of the present invention, the third electrodes for column selection are arranged in the row direction so as to be orthogonal to the first and second electrodes.

[0013]

FIG. 1 is an exploded perspective view showing the internal structure of a PDP 1 according to the present invention. PDP 1 is an AC type color PDP having a three-electrode surface discharge structure, and includes a pair of substrate structures 1.
0,20. In each cell (display element) constituting the screen ES, the pair of main electrodes X and Y intersect with the address electrode A. The main electrodes X and Y are arranged on an inner surface of a glass substrate 11 which is a base material of the substrate structure 10 on the front side, and each includes a transparent conductive film 41 and a metal film 42. A dielectric layer 17 having a thickness of about 30 to 50 μm is provided so as to cover the main electrodes X and Y, and MgO is applied as a protective film 18 on the surface of the dielectric layer 17.

The address electrodes A are connected to the substrate structure 20 on the rear side.
Are arranged on the inner surface of a glass substrate 21 as a base material. Partitions 29 each having a linear band shape in plan view are arranged in parallel with the address electrodes A in the arrangement gap of the address electrodes A, and the partition walls 29 divide the discharge gas space 30 in the row direction (horizontal direction of the screen) for each cell. .

R, G, and B three-color phosphor layers 28R, 28G, and 28B for color display are provided so as to cover the inner surface on the back side including the upper side of the address electrode A and the side surface of the partition wall 29.
Is provided. One pixel of display is composed of three cells arranged in the row direction and having different emission colors. Since the arrangement pattern of the partition walls 29 is a stripe pattern, a portion of the discharge gas space 30 between the adjacent partition walls 29 is continuous across all rows.

In the PDP 1, an address electrode A and a main electrode Y are used for addressing for setting lighting / non-lighting of each cell. That is, N (N is the number of rows) main electrodes Y
The screen scan is performed by sequentially applying scan pulses one by one to each row, and a counter discharge (address discharge) generated between the main electrode Y and the address electrode A selected according to the display content causes a row scan. , A predetermined charged state is formed. After the addressing, when a sustain pulse having a predetermined peak value is alternately applied to the main electrode X and the main electrode Y, a surface discharge along the substrate surface occurs in the cell in which an appropriate amount of wall charge exists at the end of the addressing. The phosphor layers 28R, 28G,
28B is locally excited to emit light.

FIG. 2 is a diagram showing an example of a field configuration and a drive voltage waveform. In television display by the PDP 1, in order to perform gradation reproduction by binary lighting control, each field f of a time series as an input image (a subscript of a code represents a display order) is, for example, eight subfields sf1. , Sf2, sf3, sf4, sf5, sf6, s
Divide into f7 and sf8. In other words, field f
Is replaced by a set of eight subfields sf1 to sf8. However, when reproducing a non-interlaced image such as a computer output, each frame F is divided into eight. The relative ratio of luminance in these subfields sf1 to sf8 is 1: 2: 4: 8: 16: 32: 64:
Each subfield s is weighted to be 128
The number of light emission of f1 to sf8 is set. Since 256 levels of luminance can be set for each of RGB colors by a combination of lighting / non-lighting in units of subfields, the number of colors that can be displayed is 256 ³ .

A sub-field period Tsf assigned to each of the sub-fields sf1 to sf8 secures a reset period TR for erasing electric charges on the entire screen, for example, an address period TA for performing addressing in a writing format, and luminance according to a gradation level. Therefore, a sustain period TS for maintaining the lighting state is provided. In each subfield period Tsf, the lengths of the reset period TR and the address period TA are constant irrespective of the luminance weight, but the sustain period TS
Is longer as the luminance weight is larger. That is, eight subfield periods Ts corresponding to one field f
The lengths of f are different from each other.

In the reset period TR, a positive reset pulse Pr having a sufficiently high peak value Vr is applied to all the main electrodes X at the same time, and discharge is forcibly generated in all the cells. Due to the charging of the wall charges, the wall voltage and the applied voltage cancel each other, the cell voltage drops, and the discharge stops once.
Thereafter, when the reset pulse Pr falls, a so-called self-erasing discharge occurs due to an excessive wall voltage, and the wall charges disappear. When applying the reset pulse Pr,
In order to prevent useless discharge between the main electrode X and the address electrode A, the address electrode A is biased to a positive potential.

In the address period TA, a scan pulse Py is applied to each main electrode Y in order from the top line, and an address pulse Pa is applied to an address electrode A corresponding to a cell to be turned on in parallel with the scan pulse Py. In the cells to which the scan pulse Py and the address pulse Pa have been applied, an address discharge occurs to form a predetermined amount of wall charges.

In the sustain period TS, first, the main electrode Y
Then, a positive sustain pulse Ps having a peak value Vs is applied, and thereafter, a sustain pulse Ps is alternately applied to the main electrode X and the main electrode Y. A discharge occurs in the cell written in the address period TA for each application, and an apparently continuous lighting state is maintained.

FIG. 3 is a plan view showing the positional relationship between the electrodes and the partitions according to the first embodiment. In the PDP 1, the main electrodes X and Y are connected to the electrode pair 1 for surface discharge for each row as in the conventional example.
2 and partition walls 29 that divide the discharge gas space extend in a direction inclined with respect to the main electrodes X and Y. Therefore, the plan view shape of the cell C is a parallelogram. In the present embodiment, the address electrodes A are arranged in parallel with the partition walls 29.

The movement of the charged particles generated by the address discharge is as follows.
It is mainly governed by the potential difference between the main electrodes X and Y adjacent to each other across the reverse slit between rows. Then, the ratio (a) between the opposing length a of the adjacent main electrodes X and Y and the dimension b of the reverse slit.
The larger the value of / b), the larger the amount of movement of the charged particles in the direction orthogonal to the main electrodes X and Y.

When the partition 29 is perpendicular to the main electrodes X and Y, the opposing length a is the arrangement interval of the partition 29. By inclining the partition wall 29 with respect to the main electrodes X and Y, the above-mentioned ratio (a / b) becomes smaller than in the case where the partition walls 29 are orthogonal to each other, so that the amount of charge transfer is reduced and unnecessary discharge is prevented. .

FIG. 4 is a diagram showing a wiring structure of an address electrode. When the address electrode A is inclined with respect to the main electrodes X and Y as described above, the tip of the address electrode A protrudes from the screen ES at least at one end in the row direction of the screen ES. By providing the insulating film 60 on the protruding portion and performing multi-layer wiring, the dimension of the glass substrate 21 in the row direction can be reduced. The illustrated example is a two-layer wiring in which a predetermined number of address electrodes A are alternately distributed one by one to a lower layer side and an upper layer side. As shown in FIG.
The lower wiring portion Aa and the upper wiring portion Ab are connected to a drive circuit (not shown) by flexible cables 71 and 72, respectively.

FIG. 5 is a plan view showing the positional relationship between the electrodes and the partitions according to the second embodiment. In this figure, components corresponding to the PDP 1 of the first embodiment are denoted by the same reference numerals as in FIGS.

Also in the PDP 2 of FIG. 5, the main electrodes X and Y
Are arranged so as to form an electrode pair 12 for surface discharge for each row, and a partition wall 29 that divides a discharge gas space extends in a direction inclined with respect to the main electrodes X and Y. Therefore, the plan view shape of the cell C is a parallelogram.

In this embodiment, the address electrodes Ab are arranged so as to be orthogonal to the main electrodes X and Y as in the conventional example. Thereby, all the address electrodes A in the screen are
The lengths of b are equal, and the panel load factor is equal. Further, the connection between the address electrode Ab and the drive circuit becomes easier than in the first embodiment.

If the inclination angle θ of the partition wall 29 with respect to the main electrodes X and Y is selected so as to satisfy the following equation, the conventional driving sequence can be applied as it is. tan θ = q / pp: cell pitch in the direction along the address electrode Ab q: cell pitch in the direction along the main electrodes X, Y In the above embodiments, not only write addressing but also erase addressing may be used. Phosphor layer 28R, 2
The present invention can be applied to a surface discharge type PDP other than the examples, such as a transmission type structure in which 8G and 28B are arranged on the front side, and a structure in which the address electrode A is arranged on the same substrate as the main electrodes X and Y.

[0030]

According to the first to third aspects of the present invention,
It is possible to apply a stripe-shaped partition arrangement suitable for manufacturing, suppress the movement of electric charges, and prevent unnecessary discharge.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view showing an internal structure of a PDP according to the present invention.

FIG. 2 is a diagram illustrating an example of a field configuration and a drive voltage waveform.

FIG. 3 is a plan view illustrating an arrangement relationship between electrodes and partition walls according to the first embodiment.

FIG. 4 is a diagram showing a wiring structure of an address electrode.

FIG. 5 is a plan view illustrating an arrangement relationship between electrodes and partition walls according to a second embodiment.

FIG. 6 is a plan view showing an arrangement relationship between electrodes and partition walls in a conventional PDP.

[Explanation of symbols]

 1, 2 PDP (plasma display panel) 12 electrode pair (main electrode pair) X main electrode Y main electrode ES screen 29 partition A, Ab address electrode (third electrode)

Claims (3)

[Claims] A first electrode and a second electrode are arranged so as to form a main electrode pair for generating a surface discharge for each row of a matrix display, and a plurality of partition walls having a band shape in plan view are provided in each row over the entire area of the screen. A plasma display panel having a surface discharge structure provided in a stripe pattern for partitioning each cell, wherein each of the partition walls extends along a direction inclined with respect to the first and second electrodes. Characteristic plasma display panel. 2. The plasma display panel according to claim 1, wherein third electrodes for selecting columns are arranged in the screen in parallel with the partition walls. 3. The plasma display panel according to claim 1, wherein third electrodes for selecting a column are arranged in a row direction so as to be orthogonal to said first and second electrodes.