JP2000040059A - Signal processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain efficient bus utilization and hardware device configuration by changing the setting of hardware device in a signal processing system having plural buses. SOLUTION: This signal processing system is provided with a central processing unit(CPU) 1 and hardware devices 5, 5x and 5y connected to plural buses so as to process signals successively inputted through the buses. This hardware device is provided with a bus interface 51 connectable to plural buses so as to execute the input/output of signals with respect to the plural buses and a signal processing part 52 for processing the inputted signals. The CPU 1 sets/changes the bus to be used while controlling the bus interface 51 and sets/changes the contents of signal processing to be executed at the hardware device while controlling the signal processing part 52 so that the system optimum for signal processing can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a stream signal processing apparatus which has a time constraint and requires isochronous processing in multimedia signal processing such as video and audio. The present invention relates to a signal processing system having a bus structure for efficiently separating a system bus for transmitting a command of a central processing unit and a signal processing bus for transmitting a signal to be processed, which is mainly used for a signal processing device which is generally performed. .

[0002]

2. Description of the Related Art Since the performance of a central processing unit has been improved, in the field of signal processing of multimedia such as video and audio, it is necessary to use the central processing unit for stream signal processing. Are increasing. A central processing unit in a signal processing system having a conventional central processing unit usually has one system bus, and a hardware device for processing signals is connected to the system bus. These hardware devices input a signal from outside the signal processing system, partially process the signal, and receive and pass the signal by a central processing unit via a shared bus to perform signal processing. In general, the processed signal is output to the outside by a hardware device that processes the signal.

[0003] A system for processing such a signal as described above includes:
Since the system bus for processing instructions and the bus for stream signal processing are shared, the bus is used to transmit instructions for the central processing unit to operate, such as video and audio. When performing stream signal processing,
The possibility of performing isochronous signal processing by colliding with asynchronous bus access has increased, and the efficiency of signal processing has been reduced.

In order to solve the above-mentioned drawbacks, there is a Harvard architecture in which an instruction bus for simply transmitting instructions and a data bus for transmitting signals to be processed are used as a central processing unit, but even if the instruction bus can be separated, Since the data bus was not separated, the bus could not be used effectively.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a signal processing system including a central processing unit having a plurality of buses. The purpose of the present invention is to improve the width of the allowable amount of data transmission on the bus in order to eliminate the bottleneck in which the amount of data to be processed exceeds the amount of data that can be transmitted on the bus by performing the isochronous processing required for the bus.

Another object of the present invention is to change the function of a hardware device for processing a signal for performing a stream process in the signal processing system as needed to obtain an optimal system configuration and reduce the number of hardware devices. To configure the signal processing system.

Still another object is to reduce the functions of the central processing unit in the above signal system.

[0008]

A signal processing system according to the present invention comprises a plurality of buses including a system bus, a central processing unit connected to the system bus, and a plurality of buses connected to the plurality of buses. And a plurality of hardware devices for processing signals sequentially input through at least one bus.

The hardware device is connectable to the plurality of buses, and includes a bus interface for executing input and output of signals to the plurality of buses, and a signal processing unit for processing the input signals. It is characterized by.

The plurality of buses include a signal processing bus for cascading hardware devices for sequentially processing signals, and the bus interface transmits the processed signal to the next signal processing bus via the signal processing bus. Is transmitted to a hardware device for processing.

The bus interface includes an input bus selector for selecting a bus for inputting a signal to a hardware device, an output bus selector for selecting a bus for outputting a signal processed by the hardware device, and a bus for selecting a bus. A bus control unit that receives the bus control information from the outside and sets and changes a bus selected by the input bus selector and the output bus selector.

The content of the signal processing performed by the hardware device is set and changed by signal processing information input from outside the hardware device, and the bus interface receives the signal processing information and performs the signal processing. Is provided to the signal processing unit.

The central processing unit has a storage unit for storing a bus control information transmission program for transmitting the bus control information to the bus control unit.

[0014] The central processing unit includes a storage unit for storing a signal processing information transmission program for transmitting the signal processing information to the signal processing content setting unit.

The central processing unit is characterized in that the central processing unit has a storage unit for storing a signal processing program for performing signal processing.

[0016] The hardware device includes a memory unit for storing signals to be processed by the signal processing unit.

[0017] The hardware device includes a data transmission device for transmitting a signal without passing through a central processing unit.

The hardware device is a programmable device.

The central processing unit has a storage unit for storing an element setting program for changing the setting of the programmable element, and the programmable element is capable of changing the element setting by the program. It is characterized by.

At least the processing sequence data including the signal processing information is added to the signal itself to be processed, and the hardware device includes a signal processing state storage unit that stores a state of signal processing in the signal processing unit; It is characterized by comprising a processing sequence data analyzing section for analyzing sequence data, and a signal processing state setting section for setting a signal processing state in the signal processing state storage section.

The processing sequence data analysis section analyzes the processing sequence data added to the signal itself to be processed, and notifies the bus control section and the signal processing content setting section of the analyzed processing sequence data. I do.

The signal processing unit is characterized by including a processing sequence data setting unit for adding the processing sequence data for notifying the next stage of signal processing to the signal itself to be processed.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows an example of an embodiment of a signal processing system according to the present invention. In the present embodiment, the signal processing system includes a plurality of buses 2,
3, 4, a central processing unit 1 connected to the system bus 2, and a plurality of hardware units 5, 5 for processing signals.
x, 5y. The system bus 2 is a bus for transmitting commands from the central processing unit 1, and the signal processing buses 3, 4 are buses for transmitting data for processing signals. FIG. 2 shows a block diagram of the hardware device 5 and the central processing unit 1. The hardware device 5 that processes signals has a bus interface 51 that can be connected to a plurality of buses and a signal processing unit 52 that processes signals, and the system bus 2 and the signal processing bus 3 via the bus interface 51. , 4. Further, as shown in FIG. 1, a plurality of hardware devices 5x and 5y are cascaded via a signal processing bus.

The bus interface 51 is connectable to a plurality of buses 2, 3, and 4, and executes signal input and output to the plurality of buses. Bus interface 51
Are the input bus selector 513 and the output bus selector 51
4, a bus control unit 511, and a signal processing content setting unit 5
It has 12. The bus control unit 511 has a bus setting register 5111. Input bus selector 513
Selects a bus for inputting a signal to a hardware device. The output bus selector 514 selects a bus that outputs a signal processed by the hardware device. The buses selected by the input bus selector 513 and the output bus selector 514 are set and changed by externally input bus control information. The bus control unit 511 sets and changes the bus selected by the input bus selector 513 and the output bus selector 514 according to the bus control information. The bus setting register 5111 is a register that stores bus control information for setting and changing the input bus selector 513 and the output bus selector 514.

The content of the signal processing performed by the hardware device 5 is set and changed by signal processing information input from outside the hardware device. The signal processing content setting unit 512 receives the signal processing information and notifies the signal processing unit 52 of the content of the signal processing. The signal processing unit 52 processes a signal input to the hardware device. The central processing unit 1 includes a storage unit 12 that stores a bus setting information transmission program, a storage unit 13 that stores a signal processing information transmission program, and a storage unit 14 that stores a signal processing program.
And a storage unit 15 for storing an element setting program. The storage unit 14 for storing the signal processing program
Are used in the second embodiment, and the storage unit 15 for storing the element setting program is used in the fifth embodiment.

The present embodiment is configured as described above, and its operation will be described below. In the hardware device 5, the signal processing content is set by the signal processing content setting unit 512, the input bus selector 513 and the output bus selector 514 are set by the bus control unit 511, and then the signal processing unit 52 is ready to start processing. At this stage, processing of a signal input from outside via the input bus selector 513 is started. The processed signal is output to the outside via the output bus selector 514. The above is the outline of the operation. The operation of each component will be described below.

First, the operation of setting and changing the content of the signal processing of the signal processing section 52 will be described. The signal processing information for setting and changing the content of the signal processing performed by the hardware device is, for example, a setting of a register from the central processing unit 1 or a setting by a parameter. Specifically, the central processing unit 1 transmits signal processing information to the signal processing content setting unit 512 via the system bus 2 by using a bus setting information transmission program provided in the storage unit 12.
After receiving and analyzing the signal processing information, the signal processing content setting unit 512 notifies the signal processing unit 52 of register setting or signal processing content. In the signal processing unit 52,
The parameters and the signal processing conditions are set in the notified processing contents according to the processing contents. The contents of the signal processing include a decoder and an encoder, Huffman decoding, and quantization. The parameters are
This is a coefficient indicating the setting of the coefficient of the Huffman code and the degree of quantization. In this way, the processing content of the signal processing unit 52 can be changed from the central processing unit 1. The setting and change of the signal processing contents of the signal processing unit 52 are performed not only from the central processing unit 1 but also from the central processing unit 1.
It is also possible from other hardware devices 5x and 5y,
Other methods may be used as long as the signal processing content setting unit 512 can transmit the signal processing information.

Next, the operation of the bus control unit 511 of the bus interface 51 will be described. The bus selected by the input bus selector 513 and the output bus selector 514 is determined by the bus control unit transmission program provided in the storage unit 12 of the central processing unit 1 by the bus setting register 5 of the bus control unit.
This is performed by setting 111. The bus setting register 5111 selects a bus to be used by the input bus selector 513 and the output bus selector 514 according to the setting. In this way, the central processing unit 1 can set and change the signal processing performed by the hardware device.

In the present embodiment, the bus control information transmission program includes a bus setting register 5111.
Is set, the bus control is performed. However, a program for setting parameters to the bus control unit 511 or a program for transmitting bus control information to the bus control unit 511 by another method may be used. Further, the bus setting information transmission program not only sets the bus to be selected, but also transmits information for controlling the entire signal processing.
1 to control the bus control unit 511. The bus control information is not sent from the central processing unit 1,
It may be transmitted to the bus control unit 511 from another hardware device or the like. Further, the program for transmitting the bus setting information from the central processing unit to the bus control unit can also control the input and output of signals to be processed to and from the bus from outside.

Next, the operation of signal input / output will be described. The bus interface 51 monitors the state of the signal processing of the signal processing unit 52, and inputs a signal when the signal processing unit 52 can start processing. The signal to be processed is
The data is input to the hardware device 5 via the bus selected by the input bus selector 513. The input signal is transmitted to the signal processing unit 52, and after performing signal processing, output again via the bus selected by the output bus selector 514, and then transmitted to a hardware device that processes the signal. You. As described above, the signal flow for transmitting the signal to the hardware device for processing the signal is controlled by the bus interface and the signal processing is repeated, so that the signal processing system can be controlled without being controlled by the central processing unit. The input signal is processed and output.

As described above, by setting the register or parameter in the signal processing unit 52 to change the content of the signal processing, the system can be configured efficiently. For example, when a signal processing system that performs signal processing A and signal processing B is considered, if the signal processing A and signal processing B are not simultaneously performed, the signal processing content of the signal processing unit 52 is referred to as signal processing A and signal processing. By changing the processing so as to process both of the processing B, the signal processing A and the signal processing B can be performed by one hardware device. Therefore, the scale of the hardware device can be reduced.

As a specific example, JPEG (Joint P
photographic Coding Expert
s Group) decoder. FIG.
1 shows a block configuration example of a general hardware device of a PEG decoder. The input signal is first analyzed by the analysis unit, and necessary parameters are set in each table. Next, Huffman decoding, inverse quantization, inverse D
CT (Discrete Cosine Transf)
(orm). The above is JPE
It is an outline of a G decoder. FIG. 4 illustrates an example of a JPEG decoder. In FIG. 4, the JPEG decoder comprises a central processing unit 1 and hardware units 5a, 5b, 5c, 5
d. Reference numeral 5a denotes an analysis unit that analyzes parameters used in decoding added to the signal at the time of decoding. 5b is a decoder for performing Huffman decoding.
In FIG. 4, for simplification, the table for setting the parameters shown in FIG. 3 is not shown. In the following description, the hardware device uses only the analysis unit 5a and the Huffman decoder 5b. Analysis unit 5
The bus control information is transmitted to the bus control section 511 by the bus setting information transmission program provided in the storage section 12 of the central processing unit 1.
The bus control unit 511 sets the input bus selector 513 and the output bus selector 514 based on the received bus control information. The analysis unit 5a and the Huffman decoder 5b
The signal processing information is transmitted by the signal processing information transmission program provided in the storage unit 13 of the central processing unit 1. The analysis unit 5a sets the signal processing unit 52 to perform the analysis process based on the transmitted signal processing information. The Huffman decoder 5b sets to process the Huffman decoding in the signal processing unit 52 according to the transmitted signal processing information. At this time, for the predetermined parameters, necessary parameters are transmitted from the central processing unit 1 to the signal processing content setting unit 512, and the signal processing unit 5
2 is notified. Analysis unit 5a and Huffman decoder 5b
Is completed, the signal processing unit 5 of the hardware device
When the signal processing becomes possible in the state 2, a signal to be processed is input from outside the hardware device. First, when the analysis of the signal is performed by the analysis unit 5a, the Huffman coefficient added to the signal is extracted, transmitted from the analysis unit 5a to the Huffman decoder 5b, and used as a parameter of the Huffman decoder 5b. Is set. Signal processing is performed based on the transmitted parameter information. The processed signal is transmitted to a hardware device such as the hardware device 5c or the hardware device 5d as necessary. As described above, the parameters are set for each hardware device from the central processing unit 1 and other hardware devices.

Embodiment 2 FIG. In the first embodiment, the signal processing is performed in the hardware device 5. However, in the present embodiment, the storage unit 14 that stores the signal processing program for performing the signal processing in the central processing unit 1 is used. This embodiment is installed (FIG. 2), and a part of signal processing is performed by a signal processing program stored in the storage unit 14. In the case of the present embodiment, the central processing unit 1 controls the entire signal processing, which steps of the signal processing are executed by the central processing unit 1 and which steps are executed by the hardware device 5. Further, the central processing unit 1
Storage unit 14 for storing a program for performing the above signal processing
When there is room in the system bus 2, a part of the signal processing can be performed by the central processing unit 1 via the system bus 2. Processing becomes possible.

Embodiment 3 In the present embodiment, as shown in FIG. 5, the hardware device 5 has a memory unit 53 for storing a signal for storing a signal to be processed by the signal processing unit 52. The signal before the signal processing and the signal after the signal processing can be stored in the memory unit 53 that stores the signal. Therefore, the memory unit 5 for storing signals
Utilizing 3 allows the following system configuration. When the sequential processing is possible, the signal before the signal processing and the signal after the signal processing are temporarily stored in the memory unit 53 for storing the signal, and time-division processing is performed, so that one hardware device can be used. , It is also possible to carry out signal processing. In addition, by using a system bus, at least one signal processing bus and a hardware device that processes a plurality of signals are connected to the system bus, and as a result, the hardware devices can be connected in a ring shape. . At this time, if the signals are temporarily stored in the memory unit 53 for storing the signals and the signal processing is performed in a time-division manner, a series of signal processing can be performed without increasing the number of signal processing buses.

Embodiment 4 FIG. In the present embodiment, a data transmission device 7 is added as shown in FIG. 6 in addition to the system configuration of the first embodiment (FIG. 1). The data transmission device 7 controls transmission of signals between hardware devices without the intervention of the central processing unit 1. Therefore, in the hardware devices 5, 5x, and 5y, the input bus selector 513 and the output bus selector 514 are set by the data transmission device 7.
Further, in the case of the present embodiment, the hardware devices 5, 5
Even if x and 5y do not have the bus interface 51, the data transmission device 7 can select the buses of all the hardware devices and control the signal transmission. Therefore, the load on the central processing unit 1 can be reduced, and the configuration of the hardware device can be simplified.

Embodiment 5 In the above embodiment, the signal processing is performed by the hardware device.
In this embodiment, the signal processing is performed using a programmable element instead of a hardware device. In the first embodiment, the settings performed by the bus control unit 511 and the signal processing content setting unit 512 of the bus interface 51 are performed by programmable elements. An example of a programmable device is an FPGA
(Field Programmable Gate A
(ray). When the programmable element is used as the entire hardware device 5 or when used as a portion corresponding to the bus interface 51 of the hardware device 5, a portion corresponding to the signal processing unit 52 of the hardware device 5 is used. When used as
Alternatively, the bus interface 51 and the signal processing unit 52
When used as a part with, there are other cases.

The programmable element can perform parameter setting and configuration setting of the programmable element by an element setting program provided in the storage unit 15 (FIG. 2) of the central processing unit 1. Therefore, the programmable element can be controlled by the central processing unit 1. Further, in the course of performing the signal processing, the central processing unit 1 dynamically changes the content of the signal processing by changing the setting of the programmable element by the element setting program according to the state of the signal processing. Thus, an optimal system can be configured. Furthermore, if the central processing unit 1 has the ability to perform time-division processing, time-division processing is also possible.

In this embodiment, as in the first embodiment, when a signal processing system that performs signal processing A and signal processing B is considered, if signal processing A and signal processing B are not performed simultaneously, By resetting the programmable elements, the signal processing A and the signal processing B can be performed by one hardware device. Therefore, the scale of the hardware device can be reduced as in the first embodiment.

Embodiment 6 FIG. In the present embodiment, a signal obtained by adding processing sequence data such as signal processing information and bus control information to a signal to be processed is input as a signal to a hardware device to perform signal processing. This embodiment has a system configuration similar to that of the first embodiment. Each component of the hardware device 5 will be described with reference to FIG. Bus interface 51
Has a processing sequence data analysis unit 515 and a signal processing state storage unit 516 in addition to a bus control unit 511, a signal processing content setting unit 512, an input bus selector 513, and an output bus selector 514. The signal processing unit 52 includes a signal processing state setting unit 521 and a processing sequence data adding unit 522.
And

The processing sequence data includes signal processing information and bus control information. A signal obtained by adding processing sequence data to a signal to be processed (hereinafter referred to as “signal data”) is input to the hardware device 5. The processing sequence data analyzer 515 extracts and analyzes the processing sequence data from the signal data. The signal processing state storage unit 516 stores the state of signal processing in the signal processing unit. The signal processing state setting unit 521 sets the signal processing state in the signal processing state storage unit 516. The processing sequence data adding unit 522 adds the processing sequence data notifying the signal processing of the next stage to the signal itself to be processed. Other components are the same as those in the first embodiment.

Next, the operation of each component of this embodiment will be described. The signal input to the hardware device 5 is first analyzed by the processing sequence data analysis unit 515.
The processing sequence data analysis unit 515 notifies the bus control information to the bus control unit 511 of the processing sequence data added to the input signal data, and notifies the signal processing content setting unit 512 of the signal processing information. In the bus control unit 511, the input bus selector 513 and the output bus selector 51 based on the notified information on the bus control.
Set 4 The signal processing content setting unit 512 notifies the signal processing unit 52 of the content of the signal processing based on the notified signal processing information. With the above, the hardware device 5
Is completed.

The bus interface 51 monitors the signal processing state storage unit 516, and when the signal processing unit 52 is ready to start processing, the processing sequence data analysis unit 5
From 15, the signal to be processed is transmitted to the signal processing unit 52.
The signal processing unit 52 processes the signal based on the notified signal processing content, and adds processing sequence data of the next stage to the processed signal as necessary. further,
The signal processing state setting unit 521 sets the state of the signal processing in the signal processing state storage unit 516. The processed signal is transmitted from the output bus selector 514 to the other hardware devices 5x and 5y together with the added processing sequence data.

Embodiment 7 FIG. In this embodiment, an MPEG decoder will be described as a specific application example. First, a general structure of a format of audio, image data, and communication protocol data (hereinafter, referred to as “signal processing data”) will be described with reference to FIG. FIG.
FIG. 9 is a diagram illustrating an example of adding processing sequence data to signal processing data. (A) shows the entire signal processing data,
(B) is an enlarged view of a unit for processing a signal, (C)
Is a diagram showing details of processing sequence data, and (D) is a diagram showing the contents of each process. In the signal processing data, one signal processing unit (frame) is continuous as shown in FIG. 7A, and as shown in FIG. It consists of signal data. The processing sequence data represents an attribute of the signal data in each layer. In each of the data decoding processes, the processing sequence data can be regarded as a command indicating a parameter and a mode for a process that the decoder must perform.

By regarding the signal processing unit (frame) as the content of the signal processing performed by the signal processing unit 52, it is possible to configure a decoding processing device according to the present invention. At this time, considering the efficiency at the time of mounting, the content of signal processing (frame)
If the number is small, several layers can be collectively made to correspond to one signal processing unit 52. Further, when the processing of the layer is large and can be divided into several processing units, it is necessary to divide the signal processing unit (frame) into some stream processing devices and process them.

An example of the above configuration will be described with an example of an MPEG decoder. FIG. 9 is a diagram showing an example of MPEG sequence data. MPEG data is a picture,
It is composed of four layers: GOB (Group Of Block), macro block, and block. Each layer has
There is a header, and the header portion corresponds to the processing sequence data. Therefore, in the case of FIG. 9, the signal processing unit (frame) means, for example, processing of the picture layer or processing of the GOB layer. FIG. 10 shows an example in which a plurality of hardware devices are connected to a bus and signal processing is sequentially performed among the hardware devices. FIG.
Assigns two signal processing units of a picture layer and a GOB layer to one hardware device (hdr). One hardware device (mb) for processing the macroblock layer
Assigned to. The block layer processing divides one signal processing unit into three hardware units (huff_b).
lk, iqant, idct). Furthermore, a frame memory (fr) for storing the decoded image
m). Each hardware device performs the following processing. hdr is the image size, quantization table (qmat), quantization level (q), Huf
Decoding of the fman table (huftbl) is performed, and each table and parameters are set based on this data. mb is the quantization level, cbp data (cb
p) is decoded. recon arranges the data after the inverse DCT in the frame memory based on cbp. hu
ff_blk performs Huffman decoding of DCT blocks. iqant performs inverse scan, inverse quantization based on a quantization level, and a quantization table. idc
t performs inverse DCT. Next, the operation of each hardware device will be described with reference to FIG. A signal input from outside to the hdr is decoded in the picture layer and the GOB layer in the hdr. hdr transmits the size of the image along with the signal to be processed to the next hardware device (mb).
Hdr sets the quantization table (qmat) and the quantization level (q) to equal. further,
hdr is a Huffman table (hufftbl)
Is set to huff_blk. hdr adds necessary processing sequence data to the processed signal, and transmits it to mb. mb performs mb layer decoding and recon
Cbp parameters are set. Necessary processing sequence data is added to the processed signal and transmitted to recon. The transmitted signal is huff_b from recon.
It is transmitted to each of the hardware devices lk, quant, and idct, and the block layer is decoded. The decoded signal is transmitted from idct to recon and output to frm. Thus, the hardware device of FIG.
Signals are transmitted and processed between hardware devices without passing through the central processing unit 1. Therefore, by adding the processing sequence data to the signal to be processed, the signal processing is performed while the bus control and the setting and changing of the signal processing content are performed without passing through the central processing unit 1.

[0046]

According to the signal processing system of the present invention, hardware devices are connected to each other by at least one of a plurality of buses, so that an efficient bus can be used.

Further, according to the present invention, the plurality of buses and the hardware device 5 are connected to the bus interface 5.
1 to enable signal transmission between hardware devices.

According to the present invention, a plurality of hardware devices can be connected in cascade by a signal processing bus without passing through a system bus, and a processed signal can be transmitted.

According to the present invention, the input bus selector 51
3 and an output bus selector 514, the plurality of buses and the hardware device 5 are connected, and a bus control unit 511 controls the input bus selector 513 and the output bus selector 51.
4 can set and change the bus selected.

According to the present invention, signal processing information from the outside can be received and notified to the signal processing section 52.

According to the present invention, the buses selected by the input bus selector 513 and the output bus selector 514 can be set and changed from the program stored in the central processing unit 1.

According to the present invention, the content of the signal processing performed by the signal processing unit 52 can be set and changed from the program in the central processing unit 1.

According to the present invention, the central processing unit 1 can perform signal processing without the signal processing unit 52.

According to the present invention, a signal input to the hardware device 5 or a signal after signal processing can be stored.

According to the present invention, data can be transmitted without going through the central processing unit 1. Therefore, the addition of the central processing unit 1 can be reduced.

According to the present invention, the connection between the hardware device 5 and the bus and the content of the signal processing can be changed by the programmable element without changing the hardware configuration.

According to the present invention, the contents of the hardware device 5 can be changed by the central processing unit 1 by changing the settings of the programmable elements and by the contents of the signal processing. , And the hardware device 5 can be reduced.

According to the present invention, signal processing can be performed using the processing sequence data added to the signal itself.

According to the present invention, the content to be notified to the bus control unit and the signal processing content setting unit can be added to the processing sequence data.

According to the present invention, the content of the signal processing in the next stage is determined by the signal processing unit 52 that processes the signal.
It can be added to the signal to be processed next and notified.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a hardware device and a central processing unit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a block configuration of a general hardware device of a JPEG decoder.

FIG. 4 is a diagram illustrating an example of a JPEG decoder according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a hardware device according to a third embodiment of the present invention.

FIG. 6 is a system configuration diagram according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram of a hardware device according to a sixth embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of processing sequence data addition to signal processing data according to a seventh embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of MPEG sequence data according to the seventh embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of an MPEG decoder according to a seventh embodiment of the present invention.

[Explanation of symbols]

1 central processing unit, 2 system bus, 3-4 signal processing bus, 5, 5x, 5y, 5a, 5b, 5c, 5d
Hardware device for processing signals, 7 data transmission device, 12 storage unit for storing bus control information transmission program, 13 storage unit for storing signal processing information transmission program, 14 storage unit for storing signal processing program, 15
Storage section for storing element setting program, 51 bus interface, 52 signal processing section, 53 element setting section, 511 bus control section, 5111 bus setting register, 512 signal processing content setting section, 513 input bus selector, 514 output bus selector 515 processing sequence data analysis unit 516 signal processing state storage unit 52
1 signal processing state setting section, 522 processing sequence data adding section, 53 memory section for storing signals.

Claims (15)

[Claims] A plurality of buses including a system bus; a central processing unit connected to the system bus; and a signal connected to the plurality of buses and sequentially input via at least one of the plurality of buses. A signal processing system comprising a plurality of hardware devices for processing. 2. The hardware device is connectable to the plurality of buses, and includes a bus interface for executing input and output of signals to the plurality of buses, and a signal processing unit for processing the input signals. The signal processing system according to claim 1, further comprising: 3. The signal processing system according to claim 1, wherein the plurality of buses include a signal processing bus that cascade-connects hardware devices that sequentially process signals, and the bus interface transmits the processed signal to the next bus via the signal processing bus. 3. The signal processing system according to claim 2, wherein the signal is transmitted to a hardware device that processes the signal. 4. The bus interface includes: an input bus selector for selecting a bus for inputting a signal to a hardware device; an output bus selector for selecting a bus for outputting a signal processed by the hardware device; Receiving bus control information from outside
4. The signal processing system according to claim 3, further comprising a bus controller configured to set and change a bus selected by the input bus selector and the output bus selector. 5. The content of the signal processing performed by the hardware device is set and changed by signal processing information input from outside the hardware device, and the bus interface receives the signal processing information and performs signal processing. The signal processing system according to claim 3, further comprising a signal processing content setting unit that notifies the signal processing unit of the content of the signal processing. 6. The signal processing system according to claim 4, wherein the central processing unit includes a storage unit for storing a bus control information transmission program for transmitting the bus control information to the bus control unit. 7. The signal according to claim 5, wherein the central processing unit includes a storage unit for storing a signal processing information transmission program for transmitting the signal processing information to the signal processing content setting unit. Processing system. 8. The signal processing system according to claim 5, wherein the central processing unit includes a storage unit for storing a signal processing program for performing signal processing. 9. The signal processing system according to claim 5, wherein the hardware device includes a memory unit for storing a signal to be processed by the signal processing unit. 10. The signal processing system according to claim 5, wherein the hardware device includes a data transmission device that transmits a signal without passing through a central processing unit. 11. The signal processing system according to claim 5, wherein said hardware device is a programmable element. 12. The central processing unit includes a storage unit for storing an element setting program for changing the setting of the programmable element, wherein the programmable element is capable of changing the element setting by a program. The signal processing system according to claim 11, wherein: 13. At least a processing sequence data including the signal processing information is added to a signal itself to be processed, the hardware device includes: a signal processing state storage unit that stores a state of signal processing in the signal processing unit; 13. The processing sequence data analyzing section for analyzing the processing sequence data, and a signal processing state setting section for setting a signal processing state in the signal processing state storage section. Signal processing system. 14. The processing sequence data analyzing section,
14. The signal processing system according to claim 13, wherein the processing sequence data added to the signal to be processed itself is analyzed, and the analyzed processing sequence data is notified to a bus control unit and a signal processing content setting unit. 15. The signal according to claim 14, wherein the signal processing unit includes a processing sequence data setting unit that adds the processing sequence data for notifying the next stage of signal processing to the signal itself for processing. Processing system.