JP3279860B2 - Signal decoding processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for decoding an encoded image signal, and more particularly, to an image decoding apparatus used in a case where encoding schemes coexist.

[0002]

2. Description of the Related Art Image encoding is used as a technique for improving data transmission efficiency, and international standards are defined for each of still images and moving images. For example, in the case of moving images, MPEG (Moving Pictures Ex
part Group ISO / IEC 1117
2 and 13818) and H.E. 261 (ITU-T)
Has been standardized. In still images, JPEG (Jo
int Photographic Experts
Group ISO / IEC 10918).

[0003] Image data encoded by these various encoding methods are loaded on communication lines by respective servers.

[0004] A decoding device used in a decoding terminal needs to determine an encoding method from data on the communication line and decode image data. In order to determine the encoding method in the decoding device, it has been proposed that the server side transmits the data together with the identifier indicating the encoding method of the image data as a header of the image data in addition to the encoded image data. I have.

FIG. 5 shows an example of a conventional image decoding apparatus disclosed in Japanese Patent Application Laid-Open No. Hei 5-11047.

The data received from the communication line 301 is separated by the interface circuit 302 into encoded data and a header added to the encoded data. The separated encoded image data is transmitted to the processor 304 that performs image decoding. On the other hand, the header information is analyzed by the header processing unit 303. The CPU 306 reads out a program necessary for decryption from the information in the header processing unit 303 from the program storage device 307 and transfers it to the program memory 305. The processor 304 performs decoding based on the program memory 305, and decodes the video by transmitting the decoded video and audio data to the video output control device and the audio output control device.

FIG. 6 shows another example of the conventional image decoding apparatus disclosed in Japanese Patent Application Laid-Open No. 63-263860.

In this prior art example, a decoding program necessary for decoding a video is received together with the encoded data, so that the number of encoding schemes of the data to be decoded which is indispensable in the first conventional example described above. It is possible to eliminate the need for a storage device for storing software.

As shown in FIG. 6, data received from a communication line 404 is sent to a parallel processor 405 via a modem 403 and a transmission control unit 406. The parallel processor 405 separates the decoding program and the encoded data based on the header information received from the transmission control unit 406, and receives the decoding program as an operation command of the parallel processor to decode the encoded data.

[0010]

However, this conventional embodiment requires resources such as storage devices for storing software for the number of data encoding systems to be decoded. This poses a problem that the cost for implementing the decoding device increases as the number of encoding schemes increases. In addition, there is a problem that each decoding device has to deal with a change in the encoding method and a new encoding method.

In the second conventional example, since the decoding program and the encoded data are separated by the processor itself, the processing load of the processor that should perform the decoding increases, and decoding becomes difficult. To Further, in the second conventional example, the decoding process cannot be performed while the decoding program and the encoded data are being separated, so that the data of two different encoding systems are continuously decoded. However, there is a disadvantage that the switching of the decoding method cannot be performed smoothly when performing the decoding.

SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and it is an object of the present invention to provide an image decoding apparatus which supports a plurality of encoding systems with a single decoding terminal without restriction on the decoding terminal side. It is intended for.

[0013]

The above object is achieved by providing at least one image decoding processing circuit and at least one audio decoding processing circuit;
It consists of an interface circuit, a main processor, a main memory, a video output control device, and an audio output control device,
The image decoding processing circuit includes a program storage memory, an image decoding processor, and image data storage memory, and the audio decoding processing circuit can be achieved by a video decoding device including a program storage memory, an audio decoding processor, and an audio data storage memory.

[0014]

In the video decoding apparatus of the present invention, the main processor separates the decoded data received through the communication line from the encoded data, transmits the image decoding program to the memory for storing the image decoding program, and decodes the audio decoding program into the audio decoding. Transmitted to the program storage memory, the image decoding processor performs image decoding processing based on the content of the image decoding program, and the audio decoding processor performs audio decoding processing based on the content of the audio decoding program, so that a single decoding terminal can be used. Video signals corresponding to a plurality of encoding schemes can be decoded without restrictions on the decoding terminal side.

[0015]

FIG. 1 shows a first embodiment of the present invention.

In this embodiment, a main processor 3 for controlling data transfer, a ROM 1 for storing a program of the main processor, a memory 2 for storing a data stream, a video output control circuit 4, a video output device 5, and an audio output control circuit 6 , An audio output device 7, an image decoding processing circuit 9, and an audio decoding processing circuit 10. The image decoding processing circuit 9 includes a decoding program storage memory C, an image decoding processor B, and an image data storage memory A. The audio decoding processing circuit 10 includes a decoding program storage memory F, an audio decoding processor E, and an audio data storage memory D.

In this embodiment, as shown in FIG. 7, it is applicable to a case where encoded data encoded by a plurality of encoding schemes and a decoding program for decoding the encoded data are mixed and transmitted from a line. Is done.

For example, as shown in the configuration example of FIG. 7, the data stream includes an image decoding program header A, an image decoding program data B, an audio decoding program header C, an audio decoding program data D, an encoded image data header E, and an encoded image. It comprises data F, encoded audio data header G, and encoded audio data H.

The data stream received from the communication line I by the interface circuit 8 is transmitted to the main processor 3
(Hereinafter abbreviated as CPU) and stored in the main memory 2 through the data bus G. The interface circuit 8 has a FIFO memory (not shown), which temporarily stores a data stream sent from the line, and which the CPU reads out. Next, the CPU reads the main memory and analyzes the stored data. The CPU analyzes the data based on each data header in the data stream. If the data header indicates an image decoding program, the CPU decodes the image decoding program in the image decoding processing circuit 9 according to the content of each data header. The data is transmitted to the program memory C. Similarly, the speech decoding program is applied to the speech decoding processing circuit 10.
Are transferred through the data bus G to the decryption program memory F existing in the memory. Further, the CPU continues reading and analyzing the main memory, transfers the encoded image data to the image decoding processor B existing in the image decoding processing circuit 9, and transfers the encoded audio data to the audio decoding processor E existing in the audio decoding processing circuit 10. I do.

In the image decoding processing circuit 9, the image decoding processor B decodes the encoded image data transferred from the data bus G according to the decoding program stored in the decoding program memory C. Memory A is used as a memory for temporarily storing image data during decoding.

On the other hand, in the audio decoding processing circuit 10, the audio decoding processor E decodes the encoded audio data transferred from the data bus G in accordance with the decoding program stored in the decoding program memory F. A memory D is used as a memory for temporarily storing audio data during decoding.

The image data decoded by the image decoding processing circuit 9 is transferred to the video output control circuit 4 by the CPU, and the display device 5 displays the video. The audio data decoded by the audio decoding processing circuit 10 is transferred to the audio output control circuit 6 by the CPU, and the audio is output by the audio output device 7.
An address bus H is provided for the CPU to read and transfer each data to these interface circuit 8, main memory 2, image decoding processing circuit 9, audio decoding processing circuit 10, video output control circuit 4, and audio output control circuit 6. CP
U can perform data transfer to each circuit only by control by address designation.

FIG. 8 shows an address map when an address is specified by an address bus when the CPU performs data transfer. As shown in FIG. 8, FIFO in interface, main memory, decoding program storage memory in image processing circuit, image decoding processor, decoding program storage memory in audio processing circuit, audio decoding processor and video output control circuit, audio output control By performing one-dimensional mapping of the circuits, the CPU can transfer desired data to each circuit only with the address.

In the first embodiment of the present invention described above, a decoding program is received together with encoded data from a communication line, so that a single decoding terminal stores in advance a decoding program necessary for decoding. Processor capable of decoding encoded data corresponding to a plurality of encoding schemes, and furthermore, a processor that decodes a decoding program and separation of encoded data is a processor that should perform image decoding or a processor that should perform audio decoding Since it exists separately, image decoding can be performed without interrupting the processing of the processor that should perform image decoding, and audio decoding can be performed without interrupting the processing of the processor that should perform audio decoding.

In the first embodiment shown in FIG. 1, an embodiment in which an image processing circuit and an audio processing circuit are provided to enable simultaneous image decoding and audio decoding has been described. The present invention is not limited to a decoding device intended to simultaneously perform audio decoding, and is applicable to a case where an image decoding device or an audio decoding device is used alone.

In the second embodiment of the present invention shown in FIG. 2, the load on the data bus can be reduced.

In the first embodiment of the present invention, the encoded image data and the encoded audio data are
Is supplied from the data bus by the above processing. In this case, considering the data amount of image data and audio data, it is expected that an excessive load will be applied to the transfer capability of the data bus.

Since the absolute amount of image data and audio data is larger than that of the decoding program, the load on the data bus in data transfer can be reduced by transferring the image data and audio data and the decoding program data separately. Can be.

In the second embodiment shown in FIG. 2, the interface circuit 8 and the switch 11 are different from those in the first embodiment.

The data received by the interface circuit 8 from the communication line I is divided into a decoding program and encoded data, and the decoding program is transferred to the data bus G as in the first embodiment of the present invention. On the other hand, the encoded data is transmitted to the switch 11. The switch 11 transmits the encoded image data to the processor B in the image decoding processing circuit through the encoded image data bus L, and transmits the encoded audio data to the processor E in the audio decoding processing circuit through the encoded audio data bus M. I do.

In the image decoding processing circuit 9, the image decoding processor B decodes the encoded image data transferred from the data bus G in accordance with the decoding process stored in the decoding program memory C. On the other hand, in the audio decoding processing circuit 10, the audio decoding processor E decodes the encoded audio data transferred from the data bus G according to the decoding processing stored in the decoding program memory F. The image data decoded by the image decoding processing circuit 9 is transferred to the video output control circuit 4 by the CPU, and the display device 5 displays the video. The audio data decoded by the audio decoding processing circuit 10 is sent to the audio output control circuit 6 by the CPU.
And the sound is output by the sound output device 7.

In the third embodiment of the present invention shown in FIG. 3, the load on the data bus can be further reduced.

Data received by the interface circuit 8 from the communication line I is divided into a decoding program and encoded data as in the second embodiment of the present invention, and the decoding program is transferred to the data bus G. On the other hand, the encoded data is transmitted to the switch 11. The switch 11 transmits the encoded image data to the processor B in the image decoding processing circuit through the encoded image data bus L, and transmits the encoded audio data to the processor E in the audio decoding processing circuit through the encoded audio data bus M. I do.

In the image decoding processing circuit 9, the image decoding processor B decodes the encoded image data transferred from the data bus G in accordance with the decoding process stored in the decoding program memory C. On the other hand, in the audio decoding processing circuit 10, the audio decoding processor E decodes the encoded audio data transferred from the data bus G according to the decoding processing stored in the decoding program memory F. The image data decoded by the image decoding processing circuit 9 is directly transmitted to the video output control circuit 4 via the decoded image data bus P, and the display device 5 displays the video. The audio data decoded by the audio decoding processing circuit 10 is transmitted to the decoded audio data bus Q directly to the audio output control circuit 6, and the audio is output by the audio output device 7.

According to the second and third embodiments described above, a single decoding terminal can decode coded data corresponding to a plurality of coding systems without increasing the load on the data bus. Yes, the processor that decodes the decoding program and the separation of the encoded data is separate from the processor that performs image decoding and the processor that performs audio decoding. Image decoding can be performed without hindrance, and voice decoding can be performed without hindering processing of a processor that should perform voice decoding.

In the first, second and third embodiments described above, the information transmitted together with the encoded data is a decoding program, and in the image decoding processing circuit, the decoding processor is controlled by the CPU. By operating based on the stored decoding program, image decoding is realized. The present invention can be applied to a case where a decoding processor is not used as a decoding circuit.

FIG. 4 shows a fourth embodiment of the present invention. 4th
In the embodiment, the image decoding circuit is composed of a programmable logic and a memory. In the fourth embodiment, instead of a decoding program, circuit information of a programmable logic for performing a decoding process is transmitted, and the programmable logic is a rewritable FPGA (Field Program).
(rackable logical Array).

Data received by the interface circuit 8 from the communication line I is transmitted to the main processor 3 (hereinafter referred to as CP).
U) and stored in the main memory 2 through the data bus G. Next, the CPU reads the main memory and analyzes the stored data. The CPU performs analysis based on each data header in the data stream, transmits circuit information of the image decoding circuit to programmable logic existing in the image decoding processing circuit 9, and rewrites the logic.

Similarly, the circuit information of the audio decoding circuit is transmitted to the programmable logic existing in the audio decoding processing circuit 10 to rewrite the logic. The CPU continues reading and analyzing the main memory, transfers the encoded image data to the image decoding processor B existing in the image decoding processing circuit 9, and transfers the encoded audio data to the audio decoding processor E existing in the audio decoding processing circuit 10. . In the image decoding processing circuit 9, the rewritten logic decodes the encoded image data transferred from the data bus G. On the other hand, the rewritten logic in the audio decoding processing circuit 10 also decodes the encoded audio data transferred from the data bus G. The image data decoded by the image decoding processing circuit 9 is sent to the video output control circuit 4 by the CPU.
And the display device 5 displays the video. The audio data decoded by the audio decoding processing circuit 10 is transferred to the audio output control circuit 6 by the CPU, and the audio is output by the audio output device 7.

By transmitting circuit information of programmable logic in place of the decoding program data and programming logic for performing a decoding process in the decoding apparatus, the logic is constituted by the sent circuit information and specialized in hardware capable of decoding. Thus, it becomes possible to realize a process that cannot be executed by a general-purpose processor in a program as a decoding process.

As shown in the fourth embodiment, the present invention enables a single decoding terminal to decode encoded data corresponding to a plurality of encoding schemes even when a decoding processor is not used as a decoding circuit. Further, the processor that decodes the decoding program and the encoded data is separated from the processor that performs image decoding and the processor that performs audio decoding. Image decoding can be performed without disturbing the processing, and the sound decoding can be performed without disturbing the processing of the processor that should perform the sound decoding.

[0042]

As described above, the image decoding apparatus according to the present invention can decode image data encoded by a plurality of encoding schemes with a simple configuration while using a single image decoding apparatus. is there.

[Brief description of the drawings]

FIG. 1 is a diagram showing an image decoding device according to the present invention.

FIG. 2 is a diagram showing an image decoding device according to the present invention.

FIG. 3 is a diagram showing an image decoding device according to the present invention.

FIG. 4 is a diagram showing an image decoding device according to the present invention.

FIG. 5 is a diagram showing a conventional image decoding device.

FIG. 6 is a diagram showing a conventional image decoding device.

FIG. 7 is a diagram showing a stream configuration of image data according to the present invention.

FIG. 8 is a diagram showing an address map according to the present invention.

[Description of References] 1 ROM, 2 memory, 3 main processor (CP
U), 4 ... video output control circuit, 5 ... video display device, 6 ...
Audio output control device, 7: Audio output device, 8: Interface circuit, 9: Image decoding processing device, 10: Audio decoding processing device, 11: Switcher, A: Image storage memory, B ...
Image decoding processor, C: image decoding program storage memory, D: audio data storage memory, E: audio decoding processor, F: audio decoding program storage memory, G:
Data bus, H: Address bus, D: Audio data storage memory, J, K: Programmable logic, L: Encoded image data bus, M: Encoded audio data bus, P: Decoded image data bus, Q: Decoded audio data Bus, 301 communication line, 302 interface, 303 header processing unit, 304 main processing unit MPU, 305a, 305b memory, 306 CPU, 308 video output control circuit, 3
09: video display device, 310: bus, 311: audio output control device, 312: audio output device.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masaru Hase 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-63-263860 (JP, A) JP-A-5 -150943 (JP, A) JP-A-5-110447 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/30 H04N 1/41 H04N 7/24

Claims (12)

(57) [Claims] 1. An image decoding circuit for decoding encoded image data, an audio decoding circuit for decoding encoded audio data, and a processing circuit for controlling decoding processing of the image decoding circuit and the audio decoding circuit. An interface circuit for receiving encoded image data, an image decoding program for decoding the image data, encoded audio data, an audio decoding program for decoding the audio data, The decoding circuit and the audio decoding circuit are configured to perform a decoding process based on a program stored in a memory, and the processing circuit includes: encoded image data; an image decoding program for decoding the image data; Audio data, an audio decoding program for decoding the audio data is determined, and the encoded image data is sent to the image decoding circuit. An audio decoding program for transmitting the image data to the memory of the image decoding circuit, transferring the encoded audio data to the audio decoding circuit, and decoding the audio data. A signal decoding processing device configured to perform control so as to transfer data to a memory of the audio decoding circuit. 2. An encoded image data received by the interface circuit, an image decoding program for decoding the image data, an encoded audio data, and an audio decoding program for decoding the audio data, respectively. Header information is added, and the processing circuit decodes the encoded image data, an image decoding program for decoding the image data, encoded audio data, and the audio data based on the header information. The signal decoding processing device according to claim 1, wherein the signal decoding processing device is configured to determine an audio decoding program for performing the decoding. 3. The interface circuit, the image decoding circuit, the audio decoding circuit, and the memory are mapped on a memory map of the processing circuit, and the processing circuit is configured to transfer data or the like by specifying an address. 3. The signal decoding processing device according to claim 1, wherein: 4. An interface circuit for receiving a data sequence in which information relating to a decoding method and encoded data are continuously transmitted, a rewritable memory, and a decoding process for performing a decoding process according to a request from the memory A circuit that controls the transfer of information from the interface circuit to the composite processing circuit; and a switch that transfers the encoded data received by the interface circuit to the decoding processing circuit. The processing circuit is configured to transfer data related to the decoding method from the interface circuit to the memory, and the encoded data is transmitted through the switch,
A signal decoding processing device configured to transfer the data relating to the decoding method to the decoding processing circuit via a bus different from the bus to which the data is transferred. 5. The signal decoding apparatus according to claim 4, wherein the transfer of the information on the decoding method and the encoded data is performed by header information included in the data sequence. 6. The interface circuit, the memory,
6. The signal decoding apparatus according to claim 4, wherein the decoding processing circuit is mapped on a memory map of the processing circuit. 7. The data sequence, different encoding scheme signal decoding encoded data and claims 4 to 6, wherein the including the information of the coding scheme decoding method corresponding to the Processing equipment. 8. The information regarding the decoding method is configured to be transferred to the memory via a data bus of a signal decoding processing device, and the data decoded by the decoding processing circuit is connected to the data bus. 8. The signal decoding processing device according to claim 4, wherein the signal decoding processing device is configured to output the signals via different buses. 9. An image decoding circuit for decoding encoded image data, an audio decoding circuit for decoding encoded audio data, and a processing circuit for controlling decoding processing of the image decoding circuit and the audio decoding circuit. An interface circuit for receiving encoded image data, an image decoding program for decoding the image data, encoded audio data, an audio decoding program for decoding the audio data, A switching circuit for determining the image data and the encoded audio data, transferring the encoded image data to the image decoding circuit, and transmitting the encoded audio data to the audio decoding circuit; The image decoding circuit and the audio decoding circuit are configured to perform a decoding process based on a program stored in a memory, and the processing circuit converts the image data into A video decoding program for decoding the audio data, and a voice decoding program for decoding the audio data. The bus, to which the image decoding program and the audio decoding program are transferred, and the image data and the audio. A signal decoding processing device, which is configured to be different from a bus to which data is transferred. 10. The encoded image data received by the interface circuit, an image decoding program for decoding the image data, an encoded audio data, and an audio decoding program for decoding the audio data, respectively. Header information is added, and the processing circuit decodes the encoded image data, an image decoding program for decoding the image data, encoded audio data, and the audio data based on the header information. The signal decoding processing device according to claim 9, wherein the signal decoding processing device is configured to determine an audio decoding program for performing the decoding. 11. The interface circuit, the image decoding circuit, the audio decoding circuit, and the memory are mapped on a memory map of the processing circuit, and the processing circuit is configured to transfer data or the like by specifying an address. 11. The signal decoding processing device according to claim 9, wherein: 12. The image decoding program and the audio decoding program are configured to be transferred via a data bus of the signal decoding device, and the decoding result of the image decoding circuit and the decoding result of the audio decoding circuit are 12. The signal decoding processing device according to claim 9, wherein the signal is output via a bus different from the data bus.