KR20030030403A - macro block level control circuit of video decoding - Google Patents

Abstract

PURPOSE: A circuit for controlling a macro block level of a video decoder is provided to increase utility of a CPU, simply design a program or a whole integrated circuit, and reduce power consumption. CONSTITUTION: A CI(Co-processor Interface)(602) interfaces with a CPU for co-processing video decoding. A CR(Control Register)(604) interfaces with the CI for setting up a control value for controlling a decoding controller, or reading the state of the decoding controller and each decoding block. A DI(Debugging Interface)(606) interfaces with the CR for generating interrupt in operating each decoding block or after terminating operation. An SM(State Machine)(608) interfaces with the DI for managing a macro block state of the decoding controller and commanding operation of the next decoding block after terminating the operation of the currently operating decoding block. A DBI(Decoding Block Interface)(610) interfaces with the DI for commanding a start of the operation or receiving a terminating signal, and outputting the interrupt to the CPU. A plurality of DB(Decoding Block)s(612a,612b,...,612n) interface with the DBI for constructing the video decoder.

Description

Macro block level control circuit of video decoder

The present invention relates to a macroblock level control circuit of an image decoder. More specifically, the present invention relates to a technology for reducing the complexity of controlling in software and increasing the availability of a CPU by separately setting a control circuit for controlling the decoder blocks constituting the image decoder.

International standards related to video compression and decompression include H.261, H.263, or ISO (Moving Picture Experts Group) -1,2,4, which were established by ITU-T. Video compression differs slightly depending on the standard, but in general, the size of the original image is divided into specific sizes (typically 8 pixels by 8 pixels in size), and discrete cosine transform (DCT), quantization, It is performed through a process such as variable length encoding, and a motion estimation for extracting motion information is also performed.

Video decoders vary slightly from standard to standard, but are mostly inverse discrete cosine transformers (IDCT), inverse quantizers (IQ), variable length decoders (VLD), and motion. Compensator (Motion Compensator: MC) and the like is progressed sequentially.

In the implementation of each decoder device such as IDCT, IQ, VLD, MC, etc. in hardware for high speed decoding in video decoding, the program that drives the hardware is controlled by the program that drives the hardware. There was a problem in that the load was increased or complicated in programming, and the operation order was fixed even when controlled by hardware. In addition, since the device block for audio and image processing in a multimedia integrated circuit shares a single bus, the overall structure is complicated, which causes many design difficulties.

On the other hand, the unit of the image code is an image block of 8 pixels x 8 pixels, and in the case of a video, motion estimation is performed on the image block according to a macroblock unit or standard of 16 pixels * 16 pixels.

Coding is performed by Discrete Cosine Transfrom, Quantization, Variable Length Coding, etc. on a block basis.Motion Estimation is performed on a block basis or a macro block basis according to a standard. Such compressed information is converted into a series of bitstreams for transmission and transmitted.

The bit string also includes compressed information indicating the compressed state of the original image. The content of the information includes the MB type (INTRA or INTER), the coded block pattern of each block, the motion vector, and the quantization. The same value as the macroblock header information. The decoding process is performed through the inverse process of encoding.

FIG. 1 is a block diagram of a general video decoder, and shows a process of reconstructing an original image in units of blocks from a received bit string.

Referring to FIG. 1, the hardware includes a VLD 102, an IQ 104, an IDCT 106, a multiplier 108, an MC 110, and a video memory 112. It is provided.

At this time, the operation of the decoding device block (VLD, IQ, IDCT, MC, etc. constituting the decoder) is determined according to the compressed information (state) of the original image, and in the related art, operation control of each decoding block according to the information is performed. Is controlled by the drive program on a block-by-block basis, which not only increases the load on the CPU executing the drive program but also increases the complexity of the program.

2 is a simplified block diagram of a general multimedia integrated circuit.

2, a CPU 202, a VLD 204, an IDCT 206, an MC 208, a direct memory access (DMA) 210, a peripheral device 212, and a peripheral bus controller (Peri.Bus Controller); 214), and other device blocks constituting the multimedia integrated circuit.

As shown in FIG. 2, many device blocks constituting the integrated circuit for the multimedia use the same bus, and there are many considerations in design such as structural design and resource allocation.

3A and 3B are schematic diagrams illustrating a flowchart of a decoding control method for a macroblock and an operation process according to time zones according to a conventional embodiment.

Referring to FIG. 3A, decoding of a block is started to set a VLD operation, instructing operation start (S301), and then determining whether to terminate the VLD operation (S302). If it is determined in step S302 that the VLD operation is terminated, an IQ / IDCT operation is set, an operation start is indicated (S303), and whether the IQ / IDCT operation is terminated is determined (S304).

If it is determined in step S304 that the IQ / IDCT operation is completed, the MC operation is set, the operation start is instructed (S305), and the determination of whether or not the MC operation is terminated (S304) ends the decoding of the block.

At this time, as shown in FIG. 3B, six operation settings and waits are repeated to decode one macroblock.

4A and 4B are schematic diagrams illustrating a flowchart of a decoding control method for a macroblock and an operation process according to time zones, according to another exemplary embodiment.

Referring to FIG. 4A, decoding of a block is started to set a VLD operation, instructing operation start (S401), and other operations other than video decoding of a driving program are performed, and then the operation state of the VLD is checked and finished. )

Subsequently, the IQ / IDCT operation is set, the operation start is instructed (S403), and other operations other than image decoding of the driving program are performed, and then the operation state of the IQ / IDCT is checked and finished (S404).

After that, the MC operation is set, the operation start is instructed (S405), and other operations other than video decoding of the driving program are performed, and then the decoding of the block is terminated by checking the MC operation state (S406).

At this time, in order to decode one macroblock as shown in FIG. 4B, six operation settings, another operation execution, and waiting are repeated.

As described above, the problems of the prior art according to the control method of each conventional device block will be described.

When decoding the first block as shown in FIGS. 3A and 3B, the driving program sets the operation of the decoding device block to be operated currently and instructs the operation start according to the compression information. After the operation of the decoder block waits for the completion of the operation, the control method of setting and starting the operation of the next decoder block.

However, in this method, there is a problem in that the CPU is unable to perform other tasks in the waiting "waiting state", which degrades the CPU availability. Nowadays, this type of control is rarely used. To decode one macro block, this process must be repeated six times. Since there is a waiting state between operations of each decoder block, CPU availability is considerably reduced.

4A and 4B show that in order to increase the usability of the CPU in the method shown in FIG. 3A, the program checks again whether the operation of the current decoder block is completed after performing other tasks.

In this case, when another task (one or more) is performed and the operation of the current decoder block is checked, the next decoder block is started if it is completed, but there is also a waiting state. However, this control method has a problem in that the operation time of the decoding block device and the time required for other tasks to be performed in between must be accurately calculated and the program is complicated.

In other ways, the operation completion of each decoding block can be notified to the interrupt, which also causes a problem that the CPU load is increased due to frequent interrupts.

In order to solve this problem, in some cases, the next decoding block is designed to be operated immediately after one decoding block is completed in hardware. However, since the control flow is fixed, it is inflexible and most buses are shared by multiple device blocks. In addition to the assignment of the bus, the bus becomes widely distributed in the integrated circuit, which may cause problems in terms of power consumption.

In addition, in case of designing a multimedia integrated circuit for a specific purpose (measurement of all device blocks is fixed according to a specific standard), a new device can be added to a specific device block after completion of production, or a specific device can be used for error or status check. There is a problem in that it is not easy to cope when it is necessary to process the software in the CPU by generating an interrupt at the start or end of the operation.

In order to solve the above problems, the present invention provides a separate control circuit for controlling the decoder blocks constituting the image decoder, thereby reducing the complexity for controlling in software and increasing the availability of the CPU. The control unit (DCU; Decode Control Unit) has a coprocessor interface to enable the design of the image decoder as independent as possible to achieve the ease of design.

According to the present invention as a technical concept for achieving the object of the present invention, in the image decoding controller (DCU) connected to the auxiliary processor of the multimedia integrated circuit having a central processing unit (CPU), the central processing unit ( A coprocessor interface (CI) interfaced with the CPU to serve as a coprocessor for video decoding; A control register (CR) for interfacing with the coprocessor interface (CI) to set a control value for controlling a decoding controller or to read a state of a decoding controller and each decoding block; A debugging interface (DI) for interfacing with the control register (CR) to generate an interrupt during the operation of each decoding block or to generate an interrupt after the operation ends; A state machine (SM) interfaced with the debugging interface (DI) to manage the macroblock state of the decoding controller, and instructing the operation of the next decoding block after the operation of the decoding block currently in operation; A decoding block interface (DBI) interfaced with the debugging interface (DI) to communicate with each decoding block to indicate the start of an operation or to receive an end signal, and to output an interrupt to a central processing unit (CPU); A macroblock level control circuit of an image decoder, which includes a plurality of decoding blocks DB for interfacing with the decoding block interface DBI to configure an image decoder, is provided.

1 is a block diagram of a conventional video decoder.

2 is a block diagram of a conventional multimedia integrated circuit.

3A and 3B illustrate a flowchart of a decoding control method for a macroblock and an operation process according to time zones according to a conventional embodiment.

4A and 4B are flowcharts illustrating a decoding control method for a macroblock and an operation process according to time zones, according to another exemplary embodiment.

5 is a block diagram of a multimedia integrated circuit in accordance with the present invention.

6 is a block diagram of a video decoding controller according to the present invention.

FIG. 7 is a detailed view of the coprocessor interface shown in FIG. 6.

8 is a detailed flowchart of the state machine shown in FIG.

9 is a detailed view of the debugging interface shown in FIG. 6.

10A and 10B schematically illustrate an embodiment applied to an MPEG-4 video decoder and a decoding process of a macroblock according to the present invention.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment of the present invention will be described in detail.

5 is a block diagram of a multimedia integrated circuit according to the present invention.

Referring to FIG. 5, a CPU 502, a DCU 504, a VLD 506, an IDCT 508, an MC 510, a direct memory access 512, a peripheral 514, a peripheral bus controller 516), and other device blocks constituting the multimedia integrated circuit.

At this time, the central processing unit (CPU) 502 and the image decoder device blocks are interfaced to the subprocessor.

6 is a block diagram of a decoding controller according to the present invention, and is designed to be connected to an auxiliary processor of a multimedia integrated circuit having a CPU.

6, a coprocessor interface (CI) 602, control registers (CR) 604, a debugging interface (DI) 606, and a state machine (SM) are shown. 608, a decoding block interface (DBI) 610, and a decoding block (DB) 612a, 612b, and 612n.

The CI 602 corresponds to a coprocessor interface of a CPU, and a detailed design may vary depending on which CPU is used. Through the CI, the CPU (or a driving program) may write or read a value in the CR 604.

The CR 604 is used to set a value for controlling the decoding controller or to read the state of the decoding controller and each decoding block. The program reads and writes these registers. The CR may be classified into a register for storing information such as compressed information (macro block type, encoded block pattern, and motion vector), and a register for setting and monitoring the operation of the decoding controller.

The DI 606 may generate an interrupt during the operation of each decoding block or generate an interrupt after the operation ends. Basically, interrupt occurs only when decoding of one macro block is completed or error occurs during decoding. Then, when you want to replace the function with software rather than hardware, interrupt at the operation of the corresponding decoding block. It can be generated.

The SM 608 is a block that manages the state of the decoding controller and serves to instruct the operation of the next decoding block after the operation of the decoding block that is currently operating. Depending on the setting of the CR 604, the operation of a specific decoding block may be omitted.

The DBI 610 is a block communicating with each decoding block to indicate the start of an operation or to receive an end signal. Outputs an interrupt to the connected CPU.

The DBs 612a, 612b, and 612n represent hardware blocks constituting a decoder such as VLD, IQ / IDCT, and MC.

7 shows an interface of a coprocessor according to the present invention.

Referring to FIG. 7, the CPI [N: 0], CPD [N: 0], CPWAIT, and HAND_SH signals of the CI 702 are connected to the CPU 704, and the NCS [M: 0], The NWR, NRD, ADD [K: 0], DD [N: 0], and CMD [S: 0] signals are coupled to the decoding block register 706.

At this time, the sub-processor interface may have a detailed structure depending on how the specification of the CPU that commands the sentry processor is configured, but generally has the signal structure as described above.

CPI [N: 0], which is connected to the CPU 704, inputs a coprocessor instruction, and N indicates that the CPU uses N-bit instructions. CPD [N: 0] is the coprocessor input / output data. Compression information and information necessary for control are input and written to the register, or the controller status is output as requested by the CPU. CPWAIT waits for the processing of the coprocessor with the coprocessor wait input. HAND_SH are signals for communication between the CPU and the subprocessing period.

The NCS [M: 0] connected to the decoding block register 706 represents a chip select signal of the decoding block and indicates that there are M decoding blocks. NWR represents the write strobe signal of the register. NRD represents the read strobe signal of the register. ADD [K: 0] represents the K-bit address bus in the decoder. DD [N: 0] represents the data bus in the decoder. CMD [S: 0] indicates a value indicating a specific operation of the decoder.

As described above, by providing an auxiliary processor interface unit in the decoding controller, the overall structure design and the utilization of the bus can be further improved.

8 is a state machine flowchart of a decoding controller according to the present invention.

The decoding controller controls one macroblock (composed of six 8-pixel * 8-pixel video blocks) without CPU intervention, but only if you want to process the software at the beginning and end of a specific decoder block (register setting). Processing is possible by requesting an interrupt to the CPU.

Referring to FIG. 8, the CPN represents an integer value assigned to each decoder block. For example, 0 is assigned to VLD, 1 to IQ / IDCT, and 2 to MC. Device blocks may be added depending on which standard the video decoder is applied to.

Below is a description of the above flow chart, but the register values mentioned here need to be set before macroblock start or only once before image decoding (except that the compression status information must be set for each macroblock, but the operation is extremely simple. The time required is short.) Here, the part in the dotted line is the part implemented by hardware.

In step A, OP_EN is a register value and OP_EN [OPN] represents an OP_EN value of the device block allocated to the OPN. When OP_EN [OPN] = 1, the OPN device block should operate, and when 0 indicates that the operation can be omitted.

In step B, OP_SIRQ represents a register, and OP_SIRQ [OPN] represents the OP_SIRQ value of the device block allocated to the OPN. When OP_SIRQ [OPN] is 1, an interrupt is requested (L stage) when the OPN device block starts to operate. In this case, after performing the corresponding operation in the routine that handles the generated interrupt, the interrupt is released (step M) to start the operation for the next OPN.

Step C sends a signal for operating the OPN device block. At the start of operation, the output value is shifted to "1", and when the signal from the OPN is input to the operation completed, the transition to "0" is performed again (step F). The OPN operates only while the output value is "1", otherwise it keeps the operation in the device block in the low power mode or idle state.

Step D is a state waiting for receiving the end signal from the OPN device block as described in step C above. In the case of software processing, this is the responsibility of the CPU, which reduces the availability of the CPU or increases the complexity of the program.

In step E, OP_EIRQ requests an interrupt when the operation of the OPN device block is completed when OP_EIRQ [OPN] = 1 as a register value.

Steps G and H determine a device block to be performed next or control the flow to repeat until all six image blocks are decoded when decoding of one image block is completed.

As described above, when decoding of one macro block is completed, an interrupt is generated that decoding is completed or the corresponding bit value of the state register is set to a specific value.

9 is a block diagram of a debugging interface according to the present invention. The debugging interface unit is an apparatus block for transmitting and receiving signals between interrupt and decoding device blocks.

9, the DI 902 includes a register 904 which is connected such that a control register, INT_MODE [M: 0] signals are input, and a status register signal is output; A central processing unit (CPU) 906 connected to output an NIRQ signal; A state machine (SM) 908 to which an SM_EN [M: 0] signal is input and connected so that an SM_DONE [M: 0] signal is output; A DONE [M: 0] signal is input and is interfaced with a decoding block 910 which is connected to output an EN [M: 0] signal.

At this time, the control register is the same as OP_SIRQ and OP_EIRQ described in FIG. 8, and the state register is for knowing which decoder block an interrupt has occurred in the CPU.

In addition, SM_EN and SM_DONE correspond to OP_EN and OP_DONE described in FIG. 8 and when they are actually connected to the decoder block, they are passed through a debugging interface.

For example, if the VLD device block is OPN = 1, if OP_SIRQ [1] = 1, if SM_EN [1] is input as 1 (from SM), an interrupt (NIRQ) occurs at the start of operation. SM_DONE [1] = 1 is input to SM regardless of DONE [1] (output of device block).

On the contrary, if OP_EIRQ [1] = 1, interrupt occurs after DONE [1] = 1 is input from the device block, and SM_DONE [1] = 1 is input to SM after interrupt processing.

If no interrupt is required for a particular block, set OP_SIRQ or OP_EIRQ to 0 so that SM_EN is connected directly to EN and SM_DONE is directly connected to DONE.

10A and 10B illustrate an example of applying an MPEG-4 image decoder and a decoding of a macroblock according to the present invention, and an example of applying the image decoder described above to an ISO / IEC 14496-2 MPEG-4 image decoder.

Referring to FIG. 10A, one block decoding A having a VLD, an ADR, an IQ / IDCT, an MC (1), an MC (2), and an MC (3) is composed of a HEADER (B).

Here, VLD denotes variable length code decoding, ADR denotes an AC / DC reconstructor, and IQ / IDCT denotes an inverse quantizer / inverse DCT group. MC 1 denotes a previous reference image loading, MC 2 denotes a motion vector reconstructor, MC 3 denotes a motion compensator, and HEADER (B) denotes header information decoding by a program and register setting of a controller.

The basic control flow is the same as that shown in FIG. 8, and the operation of the decoding device block, which does not need to be performed sequentially in order to further shorten the decoding time, is superimposed on the operation of other device blocks. Just modify the SM (state machine) of the controller as described.

The processing corresponding to the one block decoding A is performed by each decoder block, and the HEADER (B) only needs to be performed once when restoring one macroblock by the CPU (program).

In FIG. 10A, operations of the MC 1 and the MC 2 may be performed in parallel with the VLD, the ADR, or the IQ / IDCT (at the same time in time), except that the MC 1 and ( After 2) has been performed.

In the SM (state machine) of the controller, when the end signal is received from the IQ / IDCT, the operation completion state of the MC 2 is reported. If the operation is already completed, the MC 3 is performed. Otherwise, the operation completion of the MC 2 is completed. waiting. When a process required to decode one image block in FIG. 10 is 1 block decoding (A), decoding of one macro block proceeds as shown in FIG. 10B.

As described above, according to the present invention, in the prior art, there is a problem of reducing the utilization of the CPU or increasing the complexity of the program using a software control method, or structural complexity in the entire integrated circuit even in a hardware control method. However, there is a problem in that the control flow is fixed, but the control of the decoder control circuit unit presented in the present invention can increase the utilization of the CPU, and there is an advantage that it can be more simplified when designing a program or an integrated circuit.

In addition, when a specific decoding block is not in operation, it is automatically set to a low power mode, which is suitable for an integrated circuit for multimedia where power consumption is a problem.

The controller circuit proposed in the present invention has the advantage that it can be applied to the image encoder as well as the image decoder as it is, the use range is very wide.

Claims (4)

In the image decoding controller connected to the auxiliary processor of the multimedia integrated circuit having a central processing unit (CPU), An auxiliary processor interface (CI) interfaced with the central processing unit (CPU) to serve as an auxiliary processing for image decoding; A control register (CR) for interfacing with the coprocessor interface (CI) to set a control value for controlling a decoding controller or to read a state of a decoding controller and each decoding block; A debugging interface (DI) for interfacing with the control register (CR) to generate an interrupt during the operation of each decoding block or to generate an interrupt after the operation ends; A state machine (SM) interfaced with the debugging interface (DI) to manage the macroblock state of the decoding controller, and instructing the operation of the next decoding block after the operation of the decoding block currently in operation; A decoding block interface (DBI) interfaced with the debugging interface (DI) to communicate with each decoding block to indicate the start of an operation or to receive an end signal, and to output an interrupt to a central processing unit (CPU); And a plurality of decoding blocks (DB) for interfacing with the decoding block interface (DBI) to form an image decoder. The method of claim 1, wherein the debugging interface (DI) A register to which a control register, INT_MODE [M: 0] signals are input, and connected so that a status register signal is output; A central processing unit (CPU) connected to output an NIRQ signal; A state machine SM to which an SM_EN [M: 0] signal is input and connected so that an SM_DONE [M: 0] signal is output; A DONE [M: 0] signal is input, and an macroblock level control circuit of an image decoder, characterized in that each interface is interfaced with a decoded block connected to output an EN [M: 0] signal. The image decoder of claim 1, wherein, when decoding of one macroblock is completed, the state machine SM generates an interrupt indicating that decoding is completed or sets a corresponding bit value of a status register to a specific value. Macro block level control circuit. The video decoder of claim 1, wherein the video decoder comprises one block decoding performed by each decoder block, header information decoding by a program, and a header for setting a register of a controller. Macroblock level control circuit of the image decoder, characterized in that applied.