KR20090020460A - Method and apparatus for video decoding - Google Patents

Abstract

A method and an apparatus for decoding video are provided to interleave a slice decoding process and a transmission process of a decoded macro block in a video decoding apparatus based on a multi core processor, thereby improving decoding performance. A multi core processor(100) is an integrated circuit including a plurality of cores for powerful performance, power consumption saving and efficient job handlings. A memory unit(200) stores an application program and data and loads a decoder unit(300) to decode a bit stream inputted by the multi core processor. Moreover, the memory unit comprises a buffer or a Q(Que) which temporarily saves data before the data are processed. The decoding unit comprises various function modules for video decoding with regard to the input bit stream.

Description

Method and apparatus for video decoding {Method and apparatus for video decoding}

The present invention relates to a video decoding method and apparatus, and more particularly, to a video decoding method and apparatus for improving decoding performance in a multi-core processor-based video decoding apparatus.

In general, as information and communication technology including the Internet is developed, not only text and voice but also video communication are increasing. Conventional text-based communication methods are not enough to satisfy various needs of consumers, and accordingly, multimedia services that can accommodate various types of information such as text, video, and music are increasing. Multimedia data is huge in size and requires a large storage medium and a wide bandwidth in transmission. Therefore, it is essential to use compression coding to transmit multimedia data including text, video, and audio.

Currently used video coding methods include MPEG-2, MPEG-4, H.263 and H.264. These video coding methods are based on motion compensated predictive coding. And spatial redundancy is eliminated by transform coding.

Among these, MPEG-2 (Moving Picture Experts Group-2), which is defined by the ISO / IEC 13818-2 Video Standard, is a method of compressing video and audio. It extends MPEG-1 to convert video data used in current TV or HDTV. Its purpose is to provide a high quality video encoding technique that can be transmitted over a computer network with the main purpose of compressing efficiently.

The MPEG-2 video standard essentially eliminates spatial and temporal redundancy in the picture and displays it as a promised sequence of bits, resulting in a much shorter length of time to compress massive video data.

As a technique for removing spatial redundancy, there is a method of removing high frequency components that occupy a large amount of information while the human eye is insensitive through DCT (Discrete Cosine Transform) transformation and quantization. As a method of elimination, there is a method of detecting similarity between frames so that similar parts do not send image data, but instead send corresponding motion vector information and an error component generated when the motion vector is displayed. The error component is also subjected to DCT transformation and quantization. In addition, there is a variable length code (VLC) that losslessly compresses a bit string by assigning a much shorter code to a bit string that frequently occurs in consideration of the frequency of occurrence. In particular, the DCT coefficients may be represented by a short bit string through a run length code.

In the related art, such video decoding is generally performed by a single-core processor. However, with the recent popularization of powerful multi-core processors, the utilization of multi-core processors is increasing in areas that consume a lot of system resources such as video decoding.

However, in the case of a functional partitioning scheme in which a plurality of cores constituting one processor are each assigned only a predetermined function, the parallelization is easy because the core processing time of each core for the partitioned function is not the same. It is difficult to process and does not take full advantage of the overall performance of the processor.

In addition, in the data partitioning method of dividing a picture into a plurality of regions and allocating the same to each core, a high degree of parallelism is ensured in simple data processing, but the implementation is complicated when there is a dependency between data processing processes. There is a disadvantage in that performance is drastically reduced because additional work (predicting the relationship between the partition size of the data and the computational load) is required. In addition, since each core constituting a multi-core processor must have a full function for video decoding, it becomes inefficient in using system resources.

Accordingly, there is a need for a video decoding method that can properly display the performance of a multi-core processor to enhance video decoding performance.

SUMMARY OF THE INVENTION The present invention has been devised to solve the above problems, and the problem to be solved by the present invention is to improve decoding performance by interleaving a calculation necessary for decoding and transmission of decoded data in a multi-core processor-based video decoding apparatus. It is to provide a video decoding method and apparatus that can be improved.

Technical problem of the present invention is not limited to those mentioned above, another technical problem that is not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a video decoding apparatus according to an embodiment of the present invention, a decoder for performing video decoding and a multi-core processor for performing the video decoding on the bit stream input using the decoder unit The multi-core processor may include: a first buffer including a first core for parsing an input bit stream, dividing the bit stream into a plurality of slices, and a plurality of macroblocks generated by decoding the allocated slice; And a second core that alternately stores the second buffer and transfers the image to the main memory to restore an image of the plurality of macroblocks, wherein the decoded data is decoded from one of the first buffer and the second buffer. While a plurality of macroblocks are being transmitted, another decoded plurality of macroblocks are stored in another buffer. It is.

In order to achieve the above object, the video decoding method according to an embodiment of the present invention, in a multi-core processor-based video decoding apparatus consisting of a first core and a second core, the bit stream input from the first core Parsing and dividing into a plurality of slices and allocating any one of the plurality of slices to the second core; decoding the allocated slice in the second core to generate a plurality of macroblocks; Alternately storing the plurality of macroblocks in the first buffer and the second buffer included in the auxiliary memory and transferring the macroblocks to the main memory and using the plurality of macroblocks transferred to the main memory to the plurality of macroblocks. Restoring an image related to said decoding, wherein said decoding is performed from one of said first buffer and said second buffer. While the plurality of macroblocks are transmitted, the decoded plurality of macroblocks are stored in another buffer.

In order to achieve the above object, a video decoding apparatus according to another embodiment of the present invention, a decoder for performing video decoding and a multi-core processor for performing the video decoding on the bit stream input by using the decoder Wherein the multi-core processor is further configured to perform motion compensation for each of a plurality of macroblocks generated from the first core and the allocated slices by parsing and dividing an input bit stream into a plurality of slices. And a second core configured to transmit a plurality of macroblocks that have performed motion compensation to a main memory to reconstruct an image of the plurality of macroblocks, wherein the second core is configured to perform the motion compensation. Simultaneously perform other tasks that are not affected by the results.

In order to achieve the above object, a video decoding method according to another embodiment of the present invention, in a multi-core processor-based video decoding apparatus consisting of a first core and a second core, the bit input from the first core Parsing the stream into a plurality of slices and allocating any one of the plurality of slices to the second core; and performing motion compensation for each of the plurality of macroblocks generated from the allocated slices in the second core. And restoring an image related to the plurality of macroblocks by transmitting a plurality of macroblocks that have performed the motion compensation to a main memory, and performing the motion compensation while performing the motion compensation. Simultaneously perform other tasks that are not affected.

Specific details of other embodiments are included in the detailed description and the drawings.

According to the video decoding method and apparatus of the present invention, there are one or more effects as follows.

First, in a multi-core processor-based video decoding apparatus, decoding performance may be improved by interleaving a process of decoding a slice and a process of transmitting a decoded macro block.

Second, in a multi-core processor-based video decoding apparatus, the decoding performance can be improved by interleaving a calculation process for motion compensation and another calculation process.

Third, there is an advantage that the decoding performance can be improved while satisfying the MPEG2 standard using a multi-core processor-based video decoding apparatus.

Fourth, by improving the decoding performance of a multi-core processor-based video decoding device, it is possible to use hardware efficiently and to reduce the hardware specification in implementing the same performance.

The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, the present invention will be described with reference to the drawings for explaining a video decoding method and apparatus according to embodiments of the present invention.

At this point, it will be understood that each block of the flowchart illustrations and combinations of flowchart illustrations may be performed by computer program instructions. Since these computer program instructions may be mounted on a processor of a general purpose computer, special purpose computer, or other programmable data processing equipment, those instructions performed through the processor of the computer or other programmable data processing equipment are described in flow chart block (s). It will create a means to perform the specified functions. These computer program instructions may be stored in a computer usable or computer readable memory that can be directed to a computer or other programmable data processing equipment to implement functionality in a particular manner, and thus the computer usable or computer readable memory. It is also possible for the instructions stored in to produce an article of manufacture containing instruction means for performing the functions described in the flowchart block (s). Computer program instructions may also be mounted on a computer or other programmable data processing equipment, such that a series of operating steps may be performed on the computer or other programmable data processing equipment to create a computer-implemented process to create a computer or other programmable data. Instructions for performing the processing equipment may also provide steps for performing the functions described in the flowchart block (s).

In addition, each block may represent a portion of a module, segment, or code that includes one or more executable instructions for executing a specified logical function (s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of order. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending on the functionality involved.

1 is a block diagram illustrating a configuration of a video decoding apparatus according to an embodiment of the present invention.

The video decoding apparatus according to an embodiment of the present invention may include a multi-core processor 100, a memory unit 200, and a decoder unit 300.

The multi-core processor 100 refers to an integrated circuit including a plurality of cores for more powerful performance, lower power consumption, and more efficiently processing multiple tasks at once.

Preferably, in the video decoding apparatus according to an embodiment of the present invention, a Cell BE architecture (Cell Broadband Engine Architecture, CBEA) may be used as the multi-core processor 100. The Cell BE architecture was recently developed by Sony, Toshiba and IBM (STI, collectively known as STI) and can be used for video decoding devices that consume a lot of system resources.

2 is a block diagram schematically illustrating a structure of a Cell BE architecture according to an embodiment of the present invention.

The Cell BEband Architecture (CBEA) defines a new processor architecture based on the 64-bit power architecture and focuses on distributed processing and media-centric applications.

As shown in FIG. 2, the Cell BE architecture includes at least one Power Processor Element (PPE 110), a plurality of high performance Synergistic Processor Elements (SPE 120), and an EIB 130 (Element) that is in charge of communication therebetween. Interconnect Bus) and the memory 140 may be defined as a single chip multiprocessor.

Each SPE 120 is an independent processor capable of executing an application program. The SPE 120 enables a complete and efficient communication between all cell processing elements with a shared memory 140 and a direct memory access (DMA) instruction. In addition, since the SPE 120 is not included in the hierarchy of the main memory 140 and has only an independent Local Store (LS), the DMA method may be used to access the main memory 140. .

PPE 110 is a processor of 64-bit power architecture, which is a microprocessor core that allocates the work each SPE 120 should do. In a system based on the Cell BE architecture, the PPE 110 runs an operating system (OS) and most applications, but the calculation of the intensive portion of the operating system and applications is offloaded to the SPE 120. .

The SPE 120 is a processor that acts as an independent processor, and has an architecture of a SIMD (Single Instruction, Multiple Data) type specialized in vector and data streaming processing. The SPE 120 includes a 256 KByte Local Store (LS). As shown in FIG. 2, eight SPEs 120 may be provided, but is not limited thereto.

The EIB 130 refers to a communication path of instructions and data between all the processor elements on the Cell BE processor and the memory 140 controller and the IO. Accordingly, the EIB 130 may operate in parallel with the PPE 110 and the SPEs 120 to simultaneously perform data transmission and calculation.

Since the detailed structure of the Cell BE architecture is known, a detailed description thereof will be omitted.

The memory unit 200 stores application programs and data. The memory unit 200 may load the decoder unit 300 to be described later to enable the multi-core processor 100 to perform decoding operations on the input bit stream. In addition, the memory unit 200 may include a buffer or a queue that temporarily stores data before processing.

The storage unit may include a hard disk, a flash memory 140, a Compact Flash Card, a Secure Digital Card, an SD Card, a Smart Media Card, an MMC Card, or a Memory 140 Stick. As a module capable of inputting / outputting information such as), the module may be provided inside the video decoding apparatus or may be provided in a separate apparatus. Here, although the memory 140 provided independently of the multi-core processor 100 is taken as an example, the memory 140 inside the multi-core processor 100 may be used.

The decoder unit 300 may be configured with various functional modules for performing video decoding on the input bit stream.

3 is a block diagram showing a configuration of a decoder unit according to an embodiment of the present invention.

The decoder 300 according to an embodiment of the present invention includes a symbol decoder 310, an inverse quantizer 320, an inverse transform unit 330, a motion compensator 340, an adder 350, and a deblocking unit. And a functional module such as 360 and buffer 370.

The symbol decoder 310 performs lossless decoding on the input bit stream and obtains a motion vector and texture data. Lossless decoding includes Huffman block decoding, arithmetic decoding, variable length decoding, and the like. In general, the motion vector for a particular macroblock depends on the motion vector of the neighboring macroblock. That is, the motion vector of a specific macroblock cannot be obtained without obtaining the motion vector of the neighboring macroblock. Texture data obtained from the symbol recorder 310 may be provided to the inverse quantizer 320, and a motion vector may be provided to the motion compensator 340.

The inverse quantizer 320 inverse quantization of the texture data provided from the symbol decoder 310. The inverse quantization process refers to a process of restoring a value matched from an index generated in the quantization process by using a quantization table used in the quantization process.

The inverse transform unit 330 performs inverse transform on the inverse quantized result. Specific methods of such inverse transform include an inverse discrete cosine transform (DCT) transform and an inverse wavelet transform. The inverse transformed result, that is, the restored high frequency image is provided to the adder 350.

The motion compensator 340 motion-compensates at least one or more reference frames (previously reconstructed and stored in the picture buffer) by using a motion vector of the current macroblock provided from the symbol decoder 310. The prediction image is generated by (Motion Compensation). When such motion compensation is performed in units of 1/2 pixel or 1/4 pixel, a large amount of computation is required in an interpolation process for generating a prediction image. In addition, when motion compensation is performed using two reference frames, an average of motion compensated macroblocks is calculated. In this case, dependencies exist between the macroblocks. Thus, these macroblocks need to be processed in a single core.

The adder 350 reconstructs an image related to the current macroblock by adding the high frequency image provided from the inverse transformer 330 and the generated prediction image.

The deblock unit 360 removes block artifacts of the reconstructed image by applying a deblock filter to the reconstructed image. In general, since the reconstructed image is processed in units of macroblocks, noise is generated at the macroblock boundary part, which is called block artificiality. Such block artificiality tends to increase as the compression rate of video data increases. The reconstructed image passed through the deblocking filter may be temporarily stored in the buffer 370 and used for reconstruction of another image.

On the other hand, not all macroblocks are recovered through motion compensation. Some macroblocks may be coded through intra prediction (IP). This is called an intra macroblock. Intra prediction is a method of reconstructing a current macroblock using an image of another adjacent macroblock in the same frame. Even in this case, the current macroblock has a dependency on other macroblocks and needs to be processed in a single core.

4 is a diagram illustrating an example of decoding a video using a multi-core processor in a video decoding apparatus according to an embodiment of the present invention.

Here, a method of using the Cell BE architecture as the multi-core processor 100 will be described as an example, but is not limited thereto, and may be changed by those skilled in the art.

First, the PPE 110 may parse the input bit stream into a plurality of slices. In addition, each divided slice is sent to each SPE 120, and the SPE 120 may decode the slice to generate a plurality of macroblocks. That is, since each SPE 120 in the Cell BE architecture can decode the slice using the decoder unit 300, the concurrency of the slice level can be implemented. The macroblock is the result of decoding the slice. Since a process of decoding a slice is known, a detailed description thereof will be omitted.

When the macroblock is generated by decoding the slice, the EIB 130 may transmit the decoded macroblock using the DMA transmission from the LS of the SPE 120 to the picture buffer on the memory 140. More precisely, the YUV pixel generated by the inverse transform unit is transmitted to the picture buffer. In addition, the EIB 130 transmits prediction data from the picture data stored in the picture buffer to the SPE 120 using DMA transmission to compensate for motion.

Referring to the control method of the video decoding apparatus according to an embodiment of the present invention configured as described above are as follows.

5 is a flowchart illustrating a process of transmitting a decoded macroblock in a video decoding apparatus according to an embodiment of the present invention.

As described in FIG. 4, first, the PPE 110 parses an input bit stream and divides the input bit stream into a plurality of slices, and then the SPE 120 may decode each slice to generate a plurality of macroblocks (S401). ).

On the other hand, since the size of the LS included in the SPE 120 is not large enough to include the picture buffer with a small capacity of about 256 KB, the decoded macroblock needs to be transmitted to the picture buffer on the memory 140. have. Here, an example of transmitting to a picture buffer on the memory 140 is provided. However, the system may be transmitted to another SPE 120 in a system implementation.

In this case, it is simple but inefficient to use the DMA transmission to transmit the macro blocks one by one each time they are decoded. Therefore, when the decoded macroblocks are stored in the LS for a predetermined time and the LS is full, a plurality of decoded macroblocks are collected. Will be sent together. The number of macroblocks collected in the LS may vary depending on the capacity of the available memory 140 of the SPE 120.

6 is a diagram illustrating an example of conventionally transmitting a macroblock using DMA transfer.

As shown in FIG. 6, the decoded macroblock may be stored as a buffer in the LS of the SPE 120. When the inside of the buffer is filled with macroblocks, the EIB 130 starts transmitting the macroblocks collected in the buffer to the picture buffer on the memory 140.

In this case, when a newly decoded macroblock is stored as a buffer, the previously stored macroblock, that is, a macroblock that has not yet been transferred to the picture buffer, may be overwritten, and thus a waiting time until the macroblock transmission is completed is required. Done. This waiting time is required every time a macroblock is transmitted to the picture buffer, and the more macroblocks, the more waiting time is required. As such, since the SPE 120 cannot generate a macroblock by decoding the slice during the waiting time, the decoding time is delayed.

Therefore, in the video decoding apparatus according to an embodiment of the present invention, macroblocks may be stored and transmitted using double buffering for LS of the SPE 120.

For double buffering, the LS of the SPE 120 may be composed of two buffers, a first buffer and a second buffer. Initially, the first buffer may be set to an active state, and the second buffer may be set to a passive state. In addition, it is preferable that the capacities of the first buffer and the second buffer are set to be the same.

Referring back to FIG. 5, the SPE 120 stores the decoded macroblock in the first activated first buffer (S402), which may continue until the first buffer is full of macroblocks (S403).

When the first buffer becomes full (YES in S403), the EIB 130 requests (initializes) the transmission of the macroblocks collected in the first buffer and starts the transmission to the picture buffer (S404), and simultaneously decodes the macroblock. May be stored in the second buffer of the LS (S405). At this time, the states of the first buffer and the second buffer may be swapped with each other (Swap), so that the first buffer may be set to an inactive state and the second buffer may be set to an active state.

If the second buffer becomes full (YES in S406), the EIB 130 may start transmitting the macroblocks collected in the second buffer to the picture buffer (S407). At this time, the second buffer may be set to an inactive state, and the first buffer may be set to an active state. Then, it is determined whether decoding is completed for all macroblocks of the slice (S408), and when it is determined that there are still macroblocks, the decoded macroblocks may be stored in the first buffer of the LS (NO in S408). .

Steps 402 to 407 are repeated until decoding is completed for all macroblocks, and when decoding of all macroblocks is completed (YES in S408), that is, when storing a macroblock corresponding to the end of a slice, The macroblock may be requested to be sent to the buffer. The macroblock waits until all macroblocks are transmitted to the picture buffer (S409).

As such, when decoding of one slice is completed, steps 401 to 409 may be repeated for another slice.

7 is a diagram illustrating an example of transmitting a macroblock using DMA transmission in a video decoding apparatus according to an embodiment of the present invention.

As illustrated in FIG. 7, in the first buffer and the second buffer, storage and transmission of macroblocks may be alternately repeated. More precisely, decoding and storing the macroblock may be interleaved in the step of transmitting the macroblock. That is, while the macroblock is transmitted in the first buffer, the decoded macroblock is stored in the second buffer, and conversely, the macroblock is stored in the first buffer while the macroblock is transmitted in the second buffer. As shown in FIG. 6, no waiting time is required while transferring the macroblock to the buffer. However, since decoding a macroblock may depend on macroblocks of another picture, it is necessary to wait until all transmissions are completed at the end of one slice, but this is only needed once for one slice. .

As such, while the data is being transmitted, the entire workload of the EIB 130 can be reduced by allowing the thread of the SPE 120 to continue decoding without waiting for the data to be transmitted, thereby improving the performance of the entire decoding apparatus. You can.

In addition, since the decoding of the macroblock is not affected by the decoding of other macroblocks, the macroblock is not stored in the first buffer or the second buffer if necessary, without waiting until the decoding of the macroblock is finished. If it is full, it is possible to request the transmission of the macroblock (transmission initialization) and to decode by switching control to the SPE 120 thread immediately, thereby improving the decoding performance.

On the other hand, since the request from the first buffer or the second buffer to the transfer of the macroblock until the transfer is completed takes less time than storing the macroblock in another buffer, the first buffer or the second buffer is immediately stored. It can be made possible. Thus, although FIG. 5 and FIG. 7 illustrate an example in which transmission is performed when the macroblock is filled in the first buffer or the second buffer, the transmission request may be made in consideration of the storage time and the transmission time of the macroblock. That is, even when the macroblock is not full in the first buffer, the macroblock may be requested to be transmitted to the first buffer and then started to be stored in the second buffer.

As described above, according to an embodiment of the present invention, by interleaving the process of storing and transmitting the decoded macroblock, the decoding performance can be improved while satisfying the MPEG-2 standard standard defined by the ISO / IEC 13818-2 Video Standard. have. Therefore, the hardware can be used more efficiently, and the hardware specification can be reduced in achieving the same performance.

Meanwhile, it will be described that the video decoding method according to another embodiment of the present invention to be described below can improve decoding performance by interleaving another step independent of motion compensation to the motion compensation step during the decoding process.

Since the configuration and operation of the video decoding apparatus according to another embodiment of the present invention are the same as those described with reference to FIGS. 1 to 4, description thereof will be omitted.

In general, in the motion compensation step of the MPEG-2 decoding process, motion prediction may be performed on a previous video frame by using a motion vector obtained from a macroblock of a current video frame for two consecutive video frames. In this case, in order to perform motion prediction, prediction data (or also referred to as a prediction pixel) may be obtained from a previous image frame, that is, a picture (reference frame) already decoded.

As described in FIG. 4, since the decoded macroblock is transmitted to the picture buffer and reconstructed as a picture, it is necessary to transmit prediction data from the already reconstructed picture to the SPE 120 for motion compensation.

8 is a flowchart illustrating a process of performing motion compensation in a video decoding apparatus according to another embodiment of the present invention.

First, the SPE 120 may decode a motion vector in a macroblock of a current image frame (S501). The EIB 130 may calculate an offset in the picture buffer in order to obtain prediction data from a picture (reference frame) already decoded from the picture buffer on the memory 140 (S502). In addition, the EIB 130 may initialize the DMA transmission to transmit the prediction data to the LS of the SPE 120 (S503). The process of steps S501 to S503 is called a preparation stage in motion compensation. After the preparation phase, the DMA transfer for the prediction data is started.

When the DMA transmission for the prediction data is started, the SPE 120 may perform another step independent of the motion compensation step, that is, not affected by the motion compensation step (S504).

9 is a diagram illustrating an example of performing motion compensation in a conventional video decoding apparatus.

As shown in FIG. 9, conventionally, after completing the step of preparing motion compensation, the SPE 120 is in a standby state until the transmission of the prediction data to the SPE 120 is completed. After the transmission of the prediction data is completed, the motion prediction is performed using the transmitted prediction data. As such, there is a problem that the entire decoding time is delayed due to the waiting time for the SPE 120 to wait for the transmission of the prediction data.

Accordingly, the video decoding apparatus according to another embodiment of the present invention allows the SPE 120 to perform other tasks while transmitting the predictive data.

10 is a diagram illustrating an example of performing motion compensation in a video decoding apparatus according to another embodiment of the present invention.

As shown in FIG. 10, when the transmission of the prediction data starts after completing the preparation step of the motion compensation, the SPE 120 may perform another step of the decoding process. Preferably, the SPE 120 may perform a step that is not affected by the motion compensation step, that is, a step independent of the result of the motion compensation, for example, Huffman block decoding, a quantization matrix. Steps such as decoding (Quantizer matrix decoding) may be performed.

Referring back to FIG. 8, the SPE 120 performs another step independent of the motion compensation step until the transmission of the prediction data is completed (NO in S505), and when the transmission of the prediction data is completed (YES in S505). The SPE 120 may perform motion prediction using the transmitted prediction data and the motion vector obtained from the current macroblock (S506). Finally, motion compensation may be performed through motion prediction to generate a predicted image (S507).

Meanwhile, the video decoding method according to another embodiment of the present invention includes all types of macroblocks, that is, intra macroblocks, non-intra macroblocks, and skipped macroblocks. Applicable

11 is a diagram illustrating an example of implementing motion compensation for a non-intra macroblock in a video decoding apparatus according to another embodiment of the present invention.

As shown in FIG. 11, in order to compensate for motion with respect to the non-intra macroblock, first, a preparation step for motion compensation may be performed (S601). Then, branching according to various conditions, zeroing DC prediction (S602), quantization matrix decoding (S603), and Huffman block decoding (D) during DMA transmission of prediction data ( S604) may be performed. As shown in FIG. 11, it can be seen that the SPE 120 may perform at least a zeroing DC prediction step S602 during DMA transmission of prediction data. Finally, when the transmission of the prediction data is completed, motion prediction may be performed using the prediction data (S605, S607 or S608). Here, the StartMotionCompensation () function may include a function for decoding a motion vector, a function for calculating an offset of the memory 140, and a function for initializing a DMA transfer, and the FinishMotionCompensation () function may include a function for performing motion prediction. have.

On the other hand, by performing the non-intra IDCT step (S606) after the motion compensation is completed, it can satisfy the MPEG-2 standard standard prescribed in ISO / IEC 13818-2 Video Standard.

Although only the non-intra macroblock has been described herein, the intra macroblock and the skipped macroblock may be implemented in a similar manner.

As described above, in the case of a video decoding apparatus according to another embodiment of the present invention, the MPEG-2 standard standard defined by ISO / IEC 13818-2 Video Standard by interleaving a motion compensation step and another step independent of motion compensation Can improve the decoding performance. Therefore, the hardware can be used more efficiently, and the hardware specification can be reduced in achieving the same performance.

In this case, the term '~ part' used in the present embodiment refers to software or a hardware component such as an FPGA or an ASIC, and '~ part' performs certain roles. However, '~' is not meant to be limited to software or hardware. '~ Portion' may be configured to be in an addressable storage medium or may be configured to play one or more processors. Thus, as an example, '~' means components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, procedures, and the like. Subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functionality provided within the components and the 'parts' may be combined into a smaller number of components and the 'parts' or further separated into additional components and the 'parts'. In addition, the components and '~' may be implemented to play one or more CPUs in the device or secure multimedia card.

Those skilled in the art will appreciate that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is indicated by the scope of the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and the equivalent concept are included in the scope of the present invention. Should be interpreted.

1 is a block diagram illustrating a configuration of a video decoding apparatus according to an embodiment of the present invention.

2 is a block diagram schematically illustrating a structure of a Cell BE architecture according to an embodiment of the present invention.

3 is a block diagram showing a configuration of a decoder unit according to an embodiment of the present invention.

4 is a diagram illustrating an example of decoding a video using a multi-core processor in a video decoding apparatus according to an embodiment of the present invention.

5 is a flowchart illustrating a process of transmitting a decoded macroblock in a video decoding apparatus according to an embodiment of the present invention.

6 is a diagram illustrating an example of conventionally transmitting a macroblock using DMA transfer.

7 is a diagram illustrating an example of transmitting a macroblock using DMA transmission in a video decoding apparatus according to an embodiment of the present invention.

8 is a flowchart illustrating a process of performing motion compensation in a video decoding apparatus according to another embodiment of the present invention.

9 is a diagram illustrating an example of performing motion compensation in a conventional video decoding apparatus.

10 is a diagram illustrating an example of performing motion compensation in a video decoding apparatus according to another embodiment of the present invention.

11 is a diagram illustrating an example of implementing motion compensation for a non-intra macroblock in a video decoding apparatus according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: multi-core processor

110: PPE 120: SPE

130: EIB 140: memory

200: memory

300: decoder

310: symbol decoder 320: inverse quantization unit

330: inverse transform unit 340: motion compensation unit

350: adder 360: deblock unit

370: buffer

Claims (20)

A decoder unit for performing video decoding; And A multi-core processor which performs the video decoding on the bit stream input by using the decoder unit; The multi-core processor, A first core for parsing the input bit stream and dividing the input bit stream into a plurality of slices; And A second block for alternately storing a plurality of macroblocks generated by decoding the allocated slices in a first buffer and a second buffer included in an auxiliary memory, and then transferring the macroblocks to a main memory to restore an image of the plurality of macroblocks; Includes a core, And a plurality of decoded macroblocks are stored in another buffer while the decoded plurality of macroblocks are transmitted from one of the first buffer and the second buffer. The method of claim 1, The auxiliary memory is provided inside the second core, and the main memory is provided separately from the second core in the multi-core processor. The method of claim 1, The second core, Storing the decoded plurality of macroblocks in the first buffer, When the first buffer is full, simultaneously transmitting the plurality of macroblocks stored in the first buffer to the main memory, and storing the decoded plurality of macroblocks in the second buffer, When the second buffer is full, transferring the plurality of macroblocks stored in the second buffer to the main memory, and simultaneously storing the decoded plurality of macroblocks in the first buffer. A video decoding apparatus for repeating until all the macroblocks for the slice assigned to is transmitted. The method of claim 1, And the plurality of decoded macroblocks are transmitted to the main memory in a direct memory access (DMA) manner. The method of claim 1, The multi-core processor, At least one power processor element (PPE); A plurality of synergistic processor elements (SPEs); And A Cell BE Architecture (Cell Broadband Engine Architecture) including the at least one PPE and an EIB controlling the plurality of SPEs, And the first core is the at least one PPE, and the second core is any one of the plurality of SPEs. A decoder unit for performing video decoding; And A multi-core processor which performs the video decoding on the bit stream input by using the decoder unit; The multi-core processor, A first core for parsing the input bit stream and dividing the input bit stream into a plurality of slices; And A second core configured to perform motion compensation on each of the plurality of macroblocks generated from the allocated slices, and transmit the plurality of macroblocks on which the motion compensation has been performed to main memory to restore an image of the plurality of macroblocks Including; And the second core simultaneously performs another task that is not affected by the result of the motion compensation while performing the motion compensation. The method of claim 6, The second core extracts a motion vector for each of the plurality of macroblocks, extracts prediction data from a pre-reconstructed image in the main memory, and transmits the prediction data to the second core, thereby transmitting the predicted data and the motion vector. A video decoding apparatus for generating a predictive image by performing motion prediction using a. The method of claim 7, wherein The other operation is performed simultaneously while the prediction data is transmitted to the second core. The method of claim 7, wherein And the prediction data is transmitted to the second core in a direct memory access (DMA) manner. The method of claim 6, The multi-core processor, At least one power processor element (PPE); A plurality of synergistic processor elements (SPEs); And A Cell BE Architecture (Cell Broadband Engine Architecture) including the at least one PPE and an EIB controlling the plurality of SPEs, And the first core is the at least one PPE, and the second core is any one of the plurality of SPEs. In the multi-core processor-based video decoding method consisting of a first core and a second core, Parsing the bit stream input from the first core into a plurality of slices and assigning one of the plurality of slices to the second core; Decoding the allocated slice in the second core to generate a plurality of macroblocks; Alternately storing the decoded macroblocks in a first buffer and a second buffer included in an auxiliary memory, and then transferring the decoded macroblocks to a main memory; And Restoring images of the plurality of macroblocks using the plurality of macroblocks transmitted to the main memory; And while the decoded plurality of macroblocks are transmitted from one of the first buffer and the second buffer, the decoded plurality of macroblocks are stored in another buffer. The method of claim 11, wherein The auxiliary memory is provided inside the second core, and the main memory is provided separately from the second core in the multi-core processor. The method of claim 11, wherein Alternately storing the first buffer and the second buffer and transferring the same to the main memory; A first step of storing the decoded plurality of macroblocks in the first buffer; If the first buffer is full, transmitting a plurality of macroblocks stored in the first buffer to the main memory and storing the decoded plurality of macroblocks in the second buffer; A third step of, when the second buffer is full, transferring a plurality of macroblocks stored in the second buffer to the main memory and simultaneously storing the decoded plurality of macroblocks in the first buffer; And And a fourth step of repeating the first to third steps until all macroblocks for the slice assigned to the second core are transmitted. The method of claim 11, wherein And the plurality of decoded macroblocks are transmitted to the main memory in a direct memory access (DMA) manner. The method of claim 11, wherein The multi-core processor, At least one power processor element (PPE); A plurality of synergistic processor elements (SPEs); And A Cell BE Architecture (Cell Broadband Engine Architecture) including the at least one PPE and an EIB controlling the plurality of SPEs, The first core is the at least one PPE, and the second core is any one of the plurality of SPEs. In the video decoding apparatus based on a multi-core processor comprising a first core and a second core, Parsing the bit stream input from the first core into a plurality of slices and assigning one of the plurality of slices to the second core; Performing motion compensation on each of the plurality of macroblocks generated from the allocated slice in the second core; Restoring an image of the plurality of macroblocks by transmitting a plurality of macroblocks that have performed the motion compensation to a main memory, While performing the motion compensation, simultaneously performing other tasks not affected by the result of the motion compensation. The method of claim 16, Performing the motion compensation, Extracting a motion vector for each of the plurality of macroblocks; Extracting prediction data from a pre-reconstructed image in the main memory and transmitting the prediction data to the second core; And And performing a motion prediction using the transmitted prediction data and the motion vector to generate a prediction image. The method of claim 17, Said other operation being performed simultaneously while said prediction data is being sent to said second core. The method of claim 17, And the prediction data is transmitted to the second core in a direct memory access (DMA) manner. The method of claim 16, The multi-core processor, At least one power processor element (PPE); A plurality of synergistic processor elements (SPEs); And A Cell BE Architecture (Cell Broadband Engine Architecture) including the at least one PPE and an EIB controlling the plurality of SPEs, The first core is the at least one PPE, and the second core is any one of the plurality of SPEs.

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