CN116489380A - Micro-control processor and video code stream decoding method - Google Patents
Micro-control processor and video code stream decoding method Download PDFInfo
- Publication number
- CN116489380A CN116489380A CN202310425232.0A CN202310425232A CN116489380A CN 116489380 A CN116489380 A CN 116489380A CN 202310425232 A CN202310425232 A CN 202310425232A CN 116489380 A CN116489380 A CN 116489380A
- Authority
- CN
- China
- Prior art keywords
- decoding
- image data
- core
- initial
- decoded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012545 processing Methods 0.000 claims abstract description 114
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 239000000872 buffer Substances 0.000 claims description 8
- 230000003139 buffering effect Effects 0.000 claims description 5
- 230000001680 brushing effect Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 6
- 238000004891 communication Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Computing Systems (AREA)
- Theoretical Computer Science (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention provides a micro-control processor and a decoding method of a video code stream, comprising the following steps: the control unit is used for acquiring an initial data packet; the register unit is used for caching the initial data packet; the processing unit comprises a processing core and a decoding core, the processing core sends the initial data packet to the decoding core for decoding processing, the decoded target data is displayed, and meanwhile, the decoding core decodes the rest initial data packets. According to the micro-control processor and the decoding method of the video code stream, disclosed by the invention, the decoding efficiency can be improved.
Description
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a micro control processor and a decoding method of a video code stream.
Background
When decoding an initial packet by a micro-control processor, a separate hardware decoding module or a built-in hardware decoding module is generally used for hardware decoding or software decoding. The hardware decoding is used to increase the difficulty of the micro control processor in selecting the type, which is not beneficial to the miniaturization design of the circuit board, and the micro control processor decodes through a single core, so that the decoding efficiency is lower.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a micro-control processor and a decoding method for a video bitstream, which can improve decoding efficiency.
To achieve the above and other related objects, the present invention provides a micro control processor comprising:
the control unit is used for acquiring an initial data packet;
the register unit is used for caching the initial data packet; and
the processing unit comprises a processing core and a decoding core, wherein the processing core sends the initial data packet to the decoding core for decoding processing, and displays decoded target data, and meanwhile, the decoding core decodes the rest initial data packets.
In an embodiment of the present invention, the processing core buffers the initial data packet into the register unit based on the control unit, where the initial data packet includes at least one initial image data.
In one embodiment of the present invention, the processing core invokes the initial packet in the register unit and sends the initial packet to the decoding core for decoding to generate decoded image data.
In an embodiment of the present invention, after the decoding core decodes a certain initial image data, the decoding core determines whether to decode the decoded image data, when the decoded image data is decoded, the decoded image data is sent to the processing core, and when the decoded image data is not decoded, the certain initial image data is cached in the decoding core to repeat decoding.
In an embodiment of the present invention, after receiving the decoded image data, the processing core performs format conversion processing on the decoded image data to generate the target data, and invokes a corresponding driver to perform screen-swiping display on the target data, and at the same time, the decoding core decodes the remaining initial image data.
In one embodiment of the invention, the processing core operates in synchronization with the decoding core.
The invention also provides a decoding method of the video code stream of the micro-control processor, which comprises the following steps:
the processing core caches the initial data packet into a register unit through a control unit;
the processing core sends the initial data packet to a decoding core for decoding processing;
and the processing core displays the decoded target data, and meanwhile, the decoding core decodes the rest initial data packets.
In an embodiment of the present invention, the step of sending the initial data packet to a decoding core by the processing core for decoding includes:
the decoding core decodes a certain initial image data in the initial data packet and judges whether the decoding is successful or not;
transmitting the decoded image data to the processing core when the decoded image data is decoded;
when the decoded image data is not decoded, the certain initial image data is cached in the decoding core.
In an embodiment of the present invention, the step of buffering the certain initial image data into the decoding core when the decoded image data is not decoded includes:
combining the certain initial image data with the rest initial image data to generate a new initial data packet, and decoding the new initial data packet again to judge whether the decoding is successful;
transmitting the decoded image data to the processing core when the decoded image data is decoded;
and deleting the certain initial image data when the decoded image data is not decoded.
In an embodiment of the present invention, the processing core displays the decoded target data, and the step of decoding the remaining initial data packets by the decoding core includes:
performing format conversion processing on the decoded image data based on a format supported by a display screen to generate target data;
calling a driver program to perform screen brushing display on the target data;
and the decoding core decodes the rest initial image data until all the initial image data are decoded.
As described above, the invention provides a micro-control processor and a decoding method of a video code stream, which realize real-time decoding of h264 code stream data without a hardware coding and decoding chip. The processing core is used for realizing the reading of the code stream data, the format conversion and the screen display, the decoding core is used for decoding, the task is reasonably distributed to the processing core and the decoding core through reasonably splitting the decoding task step, the processing core and the decoding core can synchronously work, the optimization of the processes of code stream receiving, code stream decoding, screen display and the like on the micro-control processor is realized, the decoding delay can be effectively reduced, the decoding efficiency is improved, the cost of equipment is obviously reduced, and the requirement of the equipment on the area of a circuit board is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a micro-control processor according to the present invention;
FIG. 2 is a process flow diagram of a processing core of the present invention;
FIG. 3 is a flow chart of the process of the decoding core of the present invention;
FIG. 4 is a flow chart showing a method for decoding a video code stream of a micro-control processor according to the present invention;
FIG. 5 is a flowchart showing step S20 in FIG. 4;
FIG. 6 is a flowchart showing step S23 in FIG. 5;
fig. 7 is a flowchart of step S30 in fig. 4.
Description of element numbers:
10. a control unit; 20. a registering unit; 30. a processing unit; 31. a processing core; 32. and (5) decoding the core.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides a micro-control processor, which can be applied to a real-time decoding process of image data, for example, can decode H264 video data in real time. One video image coded data in the H264 video data is called one frame, one frame is composed of one slice (slice) or a plurality of slices, one slice is composed of one or a plurality of Macro Blocks (MBs), and one macro block is composed of yuv data of 16x 16. The macroblock is used as a basic unit of H264 coding, and H264 video data increases the coding compression rate by using intra-frame compression and inter-frame compression. Therefore, after the micro-control processor decodes the H264 video data in real time, the corresponding screen-brushing display can be performed. The micro control processor may include a control unit 10, a registering unit 20, and a processing unit 30.
Referring to fig. 1, in one embodiment of the present invention, the control unit 10 may be configured to acquire an initial data packet in real time. The registering unit 20 may be used to buffer the initial data packet. When the initial data packet is H264 video data, the H264 video data may include at least one video image, and the video image may be one frame or less than one frame, so that the initial data packet may include at least one initial image data. The initial image data may be one frame image or less than one frame image. The control unit 10 acquires initial data packets in real time, each of which may include a different amount of initial image data. For example, a first initial data packet may include three frames of initial image data, a second initial data packet may include less than one frame of initial image data, a third initial data packet may include four frames of initial image data, one less than one frame of initial image data, and so on.
Referring to FIG. 1, in one embodiment of the present invention, the processing unit 30 may be a multi-core processing unit, such as a dual-core processing unit, a tri-core processing unit, a quad-core processing unit, etc. In the present embodiment, the processing unit 30 is exemplified as a dual-core processing unit. The dual core processing unit (DualCore Processor) is to integrate two operation cores on one processing unit, thereby improving the computing power. Dual core processing units are cores of processing units having two identical functions on one processing unit based on a single semiconductor. The processing unit 30 may include two cores, which may be distinguished into a processing core 31 and a decoding core 32.
Referring to fig. 1, 2 and 3, in one embodiment of the present invention, the processing core 31 may buffer the initial data packet into the register unit 20 based on the control unit 10. For example, when it is necessary to decode an initial packet from the outside, the processing core 31 may communicate with the control unit 10 and further send an instruction to the control unit 10 to enable the control unit 10 to receive the initial packet. When the control unit 10 receives an initial data packet from the outside, the initial data packet needs to be sent to the register unit 20 for buffering, so as to be decoded in real time later. After the register unit 20 caches the initial data packet, the processing core 31 may send the initial data packet in the register unit 20 to the decoding core 32 for decoding, so as to decode the corresponding decoded image data through the decoding core 32. At this time, the processing core 31 may perform format conversion processing on the decoded image data, convert the format thereof into a color format supported by the display screen, so as to generate target data, and call a corresponding driver to perform screen-brushing display on the target data.
Referring to fig. 1, 2 and 3, in one embodiment of the present invention, the decoding core 32 may decode the initial data packet. Since the initial data packet may include one initial image data or a plurality of initial image data, and the initial image data may be one frame image or less than one frame image, the decoding core 32 may process different initial data packets according to different processing methods.
Referring to fig. 1, 2 and 3, in one embodiment of the present invention, an initial data packet includes a plurality of initial image data, and a frame of image is taken as an example. When the processing core 31 transmits the initial data packet to the decoding core 32 for decoding, the decoding core 32 may sequentially decode a plurality of initial image data in the initial data packet. The decoding core 32 may decode the first initial image data to generate corresponding decoded image data. The decoding core 32 may send the decoded image data to the processing core 31, and the processing core 31 may perform format conversion processing on the decoded image data, convert the format of the decoded image data into a color format supported by the display screen, so as to generate target data, and invoke a corresponding driver to perform screen-brushing display on the target data. While the processing core 31 processes the decoded image data corresponding to the first initial image data, the decoding core 32 may decode the second initial image data to generate corresponding decoded image data. That is, while the processing core 31 performs the screen-swiping display on the target data of the previous frame, the decoding core 32 may decode the initial image data of the next frame, and the processing core 31 and the decoding core 32 may operate synchronously, so that the decoding efficiency may be improved.
Referring to fig. 1, 2 and 3, in one embodiment of the present invention, after the decoding core 32 completes decoding a certain initial image data, the decoding core 32 needs to determine whether to successfully decode the corresponding decoded image data. When the corresponding decoded image data is decoded, the decoding core 32 may transmit the decoded image data to the processing core 31 for processing. When the corresponding decoded image data is not decoded, it may be indicated that the initial image data may have a data error or that the initial image data is an image of less than one frame. The decoding core 32 may then buffer the initial image data into the decoding core 32 to combine the initial image data with other initial image data to generate a new initial data packet and re-decode the new initial data packet. When the decoding core 32 decodes the initial image data again, it is again determined whether the corresponding decoded image data is successfully decoded. When the corresponding decoded image data is decoded, the decoding core 32 may transmit the decoded image data to the processing core 31 for processing. When the corresponding decoded image data is not decoded, it may be indicated that the initial image data has a data error at this time, the initial image data is discarded, and the remaining initial image data is decoded in sequence.
Referring to fig. 1, 2 and 3, in one embodiment of the present invention, the processing core 31 and the decoding core 32 may perform data interaction based on mailbox communication and/or shared memory (shared memory) communication, or may use ERPC (embedded remote procedure call) instead of the inter-core communication manner of mailbox and shared memory. The ERPC is used, so that the programming process is more convenient and rapid, and the debugging difficulty is reduced. Further, the processing core 31 and the decoding core 32 may implement functions such as transmission of an initial data packet, transmission of data parameters (resolution, frame rate, etc.), transmission of decoded image data, transmission of a decoding task state, and transmission of an initial data packet size to be decoded.
Referring to fig. 2, in one embodiment of the present invention, after an initial data packet to be decoded appears in the register unit 10, the processing core 31 may send the initial data packet to the decoding core 32 for decoding through the data transmission 41. After the decoding is completed, a case may occur in which one frame 42 is decoded or one frame 43 is not decoded. When a frame 42 is decoded, the decoded frame 42 may be sent to the processing core 31 for format conversion 44, and after format conversion 44 is completed, it may be denoted as decoding completion 45. When a situation occurs in which a frame 43 is not decoded, the frame 43 may be sent to the processing core 31, and the processing core 31 may represent the corresponding data of the frame 43 as unprocessed data 46, and send the unprocessed data 46 to the decoding core 32 for decoding again. When the processing core 31 finishes the image brushing, this may be denoted as processing completion 47, and the processing core 31 may continue to read the buffered initial data packet in the register unit 10 to achieve real-time decoding.
Referring to fig. 3, in one embodiment of the present invention, the initial packet sent to the decoding core 32 may be represented as the code stream data 51, and when the code stream data 51 is stored in the decoding core 32 for data decoding 52, a situation may occur in which one frame 42 is decoded or one frame 43 is not decoded. When a frame 42 is decoded, the decoding core 32 may send the decoded data to the processing core 31, and the processing core 31 may perform the fetch data 53 processing on the decoded data. When a frame 43 is not decoded, the decoding core 32 may retransmit the data to the code stream data 51 and decode the remaining code stream data 51.
It can be seen that in the above scheme, the real-time decoding of the h264 bitstream data is realized without the aid of a hardware codec chip. The processing core is used for realizing the reading of the code stream data, the format conversion and the screen display, the decoding core is used for decoding, the task is reasonably distributed to the processing core and the decoding core through reasonably splitting the decoding task step, the processing core and the decoding core can synchronously work, the optimization of the processes of code stream receiving, code stream decoding, screen display and the like on the micro-control processor is realized, the decoding delay can be effectively reduced, the decoding efficiency is improved, the cost of equipment is obviously reduced, and the requirement of the equipment on the area of a circuit board is reduced.
Referring to fig. 4, the present invention further provides a decoding method of a video code stream of a micro-control processor, where the decoding method can be applied to the real-time decoding process of image data of the micro-control processor, for example, decoding processing can be performed on H264 video data in real time. The decoding method may include the steps of:
step S10, the processing core caches the initial data packet into a register unit through a control unit;
step S20, the processing core sends the initial data packet to the decoding core for decoding processing so as to generate corresponding decoded image data;
and step S30, the processing core displays the decoded image data, and the decoding core decodes the residual initial image data.
Referring to fig. 4, in one embodiment of the present invention, when step S10 is performed, specifically, the control unit 10 may be configured to acquire the initial data packet in real time. The registering unit 20 may be used to buffer the initial data packet. When the initial data packet is H264 video data, the H264 video data may include at least one video image, and the video image may be one frame or less than one frame, so that the initial data packet may include at least one initial image data. The initial image data may be one frame image or less than one frame image. The processing core 31 may buffer the initial data packet into the registering unit 20 based on the control unit 10. For example, when it is necessary to decode an initial packet from the outside, the processing core 31 may communicate with the control unit 10 and further send an instruction to the control unit 10 to enable the control unit 10 to receive the initial packet. When the control unit 10 receives an initial data packet from the outside, the initial data packet needs to be sent to the register unit 20 for buffering, so as to be decoded in real time later.
Referring to fig. 5, in an embodiment of the present invention, step S20 may include the following steps:
step S21, the decoding core decodes a certain initial image data in the initial data packet and judges whether the decoding is successful or not;
step S22, when decoding the decoded image data, transmitting the decoded image data to a processing core;
step S23, when the decoded image data is not decoded, buffering a certain initial image data into a decoding core.
Referring to fig. 5, in an embodiment of the present invention, when step S20 is performed, specifically, after the decoding core 32 completes decoding of a certain initial image data, the decoding core 32 needs to determine whether to successfully decode the corresponding decoded image data. When the corresponding decoded image data is decoded, the decoding core 32 may transmit the decoded image data to the processing core 31 for processing. When the corresponding decoded image data is not decoded, it may be indicated that the initial image data may have a data error or that the initial image data is an image of less than one frame. The decoding core 32 may then buffer the initial image data into the decoding core 32 to combine the initial image data with other initial image data to generate a new initial data packet and re-decode the new initial data packet.
Referring to fig. 6, in an embodiment of the present invention, step S23 may include the following steps:
step S231, combining some initial image data with other initial image data to generate a new initial data packet, and decoding the new initial data packet again to judge whether the decoding is successful;
step S232, when decoding the decoded image data, transmitting the decoded image data to a processing core;
step S233, deleting a certain initial image data when the decoded image data is not decoded.
Referring to fig. 6, in one embodiment of the present invention, when step S23 is performed, specifically, after the decoding core 32 decodes the initial image data again, it is determined whether the corresponding decoded image data is successfully decoded again. When the corresponding decoded image data is decoded, the decoding core 32 may transmit the decoded image data to the processing core 31 for processing. When the corresponding decoded image data is not decoded, it may be indicated that the initial image data has a data error at this time, the initial image data is discarded, and the remaining initial image data is decoded in sequence.
Referring to fig. 7, in an embodiment of the present invention, step S30 may include the following steps:
step S31, performing format conversion processing on the decoded image data based on the format supported by the display screen to generate target data;
s32, calling a driver program to perform screen-brushing display on target data;
and step S33, the decoding core decodes the residual initial image data until all the initial image data are decoded.
Referring to fig. 7, in an embodiment of the present invention, when step S30 is performed, specifically, after the register unit 20 caches the initial data packet, the processing core 31 may send the initial data packet in the register unit 20 to the decoding core 32 for decoding, so that the decoding core 32 decodes the corresponding decoded image data. At this time, the processing core 31 may perform format conversion processing on the decoded image data, convert the format thereof into a color format supported by the display screen, so as to generate target data, and call a corresponding driver to perform screen-brushing display on the target data. The decoding core decodes the remaining initial image data until all the initial image data are decoded.
In summary, by the micro-control processor and the decoding method of the video code stream provided by the invention, the real-time decoding of the h264 code stream data is realized under the condition of not using a hardware coding and decoding chip. The processing core is used for realizing the reading of the code stream data, the format conversion and the screen display, the decoding core is used for decoding, the task is reasonably distributed to the processing core and the decoding core through reasonably splitting the decoding task step, the processing core and the decoding core can synchronously work, the optimization of the processes of code stream receiving, code stream decoding, screen display and the like on the micro-control processor is realized, the decoding delay can be effectively reduced, the decoding efficiency is improved, the cost of equipment is obviously reduced, and the requirement of the equipment on the area of a circuit board is reduced.
In the description of the present specification, the descriptions of the terms "present embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A micro-control processor, comprising:
the control unit is used for acquiring an initial data packet;
the register unit is used for caching the initial data packet; and
the processing unit comprises a processing core and a decoding core, wherein the processing core sends the initial data packet to the decoding core for decoding processing, and displays decoded target data, and meanwhile, the decoding core decodes the rest initial data packets.
2. The micro-control processor of claim 1, wherein the processing core buffers the initial data packet into the register unit based on the control unit, the initial data packet including at least one initial image data.
3. The micro-control processor of claim 1, wherein the processing core invokes the initial data packet in the register unit and sends to the decoding core for decoding to generate decoded image data.
4. A micro control processor according to claim 3, wherein when the decoding core decodes a certain initial image data, the decoding core judges whether or not to decode the decoded image data, when the decoded image data is decoded, the decoded image data is sent to the processing core, and when the decoded image data is not decoded, the certain initial image data is buffered in the decoding core to repeat decoding.
5. The micro control processor as set forth in claim 4 wherein said processing core receives said decoded image data and then performs a format conversion process on said decoded image data to generate said target data, and invokes a corresponding driver to swipe said target data while said decoding core decodes the remaining initial image data.
6. The micro-control processor as set forth in claim 5 wherein said processing core operates in synchronization with said decoding core.
7. A method for decoding a video bitstream of a micro-control processor, comprising:
the processing core caches the initial data packet into a register unit through a control unit;
the processing core sends the initial data packet to a decoding core for decoding processing;
and the processing core displays the decoded target data, and meanwhile, the decoding core decodes the rest initial data packets.
8. The method of decoding a video stream of a micro-control processor according to claim 7, wherein the step of the processing core sending the initial data packet to a decoding core for decoding processing comprises:
the decoding core decodes a certain initial image data in the initial data packet and judges whether the decoding is successful or not;
transmitting the decoded image data to the processing core when the decoded image data is decoded;
when the decoded image data is not decoded, the certain initial image data is cached in the decoding core.
9. The method of decoding a video bitstream of a micro-control processor according to claim 8, wherein the step of buffering the certain initial image data into the decoding core when the decoded image data is not decoded comprises:
combining the certain initial image data with the rest initial image data to generate a new initial data packet, and decoding the new initial data packet again to judge whether the decoding is successful;
transmitting the decoded image data to the processing core when the decoded image data is decoded;
and deleting the certain initial image data when the decoded image data is not decoded.
10. The method of decoding a video bitstream of a micro-control processor according to claim 7, wherein the processing core displays the decoded target data, and the decoding core decodes the remaining initial data packets, comprising:
performing format conversion processing on the decoded image data based on a format supported by a display screen to generate target data;
calling a driver program to perform screen brushing display on the target data;
and the decoding core decodes the rest initial image data until all the initial image data are decoded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310425232.0A CN116489380A (en) | 2023-04-20 | 2023-04-20 | Micro-control processor and video code stream decoding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310425232.0A CN116489380A (en) | 2023-04-20 | 2023-04-20 | Micro-control processor and video code stream decoding method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116489380A true CN116489380A (en) | 2023-07-25 |
Family
ID=87222626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310425232.0A Pending CN116489380A (en) | 2023-04-20 | 2023-04-20 | Micro-control processor and video code stream decoding method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116489380A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090020460A (en) * | 2007-08-23 | 2009-02-26 | 삼성전자주식회사 | Method and apparatus for video decoding |
| CN109544439A (en) * | 2018-10-23 | 2019-03-29 | 百富计算机技术（深圳）有限公司 | A kind of coding/decoding method based on multi-core processor, terminal device and storage medium |
-
2023
- 2023-04-20 CN CN202310425232.0A patent/CN116489380A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090020460A (en) * | 2007-08-23 | 2009-02-26 | 삼성전자주식회사 | Method and apparatus for video decoding |
| CN109544439A (en) * | 2018-10-23 | 2019-03-29 | 百富计算机技术（深圳）有限公司 | A kind of coding/decoding method based on multi-core processor, terminal device and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI536811B (en) | Method and system for image processing, decoding method, encoder and decoder | |
| US10027970B2 (en) | Render-orientation information in video bitstream | |
| CN101461247B (en) | Parallel batch decoding of video blocks | |
| WO2021036795A1 (en) | Video super-resolution processing method and device | |
| CN1825964B (en) | Method and system for processing video frequency data on chip | |
| WO2013064120A1 (en) | Method and device for encoding and decoding based on transformation mode | |
| WO2017041551A1 (en) | Spice protocol-based image transmission method and apparatus | |
| TW201244493A (en) | A method for decoding video | |
| WO2014079303A1 (en) | Method, device and system for synthesizing multi-screen video | |
| TWI590653B (en) | Image frame processing method | |
| CN111432213B (en) | Method and apparatus for tile data size coding for video and image compression | |
| CN106412588B (en) | Image frame processing method | |
| CN110730364A (en) | Cloud mobile phone data transmission method and device and storage medium | |
| WO2024078066A1 (en) | Video decoding method and apparatus, video encoding method and apparatus, storage medium, and device | |
| CN116489380A (en) | Micro-control processor and video code stream decoding method | |
| JP2022504379A (en) | Intra mode selection in intra prediction | |
| JP2005033763A (en) | Transmission apparatus, image processing system, image processing method, program, and recording medium | |
| CN113422983B (en) | Data processing method, computer device, and storage medium | |
| WO2021237475A1 (en) | Image encoding/decoding method and device | |
| CN104159106A (en) | Video encoding method and device, and video decoding method and device | |
| CN104780390A (en) | Video processing method and device | |
| CN111314701A (en) | Video processing method and electronic equipment | |
| WO2021237474A1 (en) | Video transmission method, device and system | |
| WO2015188729A1 (en) | Video coding method and video decoding method and related device | |
| TWI835238B (en) | Image processing method and image processing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |