JPH07325912A - Data processor and its method - Google Patents

Abstract

PURPOSE:To provide a data processor and its method which need not be provided with dedicated processing parts by applied encoding systems even when plural encoding systems are applied. CONSTITUTION:When image data to be encoded are present in an image memory 102, a CPU 109 sets divided encoding procedures in instruction memories 107a and 107b and makes DSPs 104a and 104b encode the image data associatively. Further, when the image data to be encoded are present in the image memory 102 and code data to be decoded are present in a code memory 105, the CPU 109 sets the encoding procedure in the instruction memory 107a and a decoding procedure in the instruction memory 107b respectively and makes the DSP 104a encode the image data and the DSP 104b decodes the code data respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device,
For example, the present invention relates to a data processing device such as an image processing device that encodes / decodes image data.

[0002]

2. Description of the Related Art In order to transmit a huge amount of image data, its compression technique is indispensable. Image data encoding methods include monochrome image data encoding methods such as MR encoding method used in group 3 facsimile and MMR encoding method used in group 4 facsimile, JPEG (Joint Photographic Experts Group). ), Which is being standardized by JBIG (Joint Bi-level Image Experts Group) and JBIG (Joint Bi-level Image Experts Group). There is a color image data encoding method.

The JPEG system is composed of a plurality of systems, the most basic of which is the baseline system. FIG. 1 is a diagram showing a data compression procedure of the baseline system. First, the input image data read by a document reading device such as an image scanner is divided into blocks of 8 × 8 pixels. The subsequent compression processing is performed in this block unit. In the JPEG method, there is no regulation on the color space in which the image data read by the document reading device is coded, but a color space conversion process is often performed as a process prior to the coding process. As the color space to be converted, a color space that enables highly efficient coding processing, for example, a color space YCbCr, YIQ, Lab or the like composed of a luminance signal and a color signal is often used. In many cases, subsampling processing is performed on the color signal after color space conversion. In the baseline system, DCT, which is a kind of orthogonal transformation, is applied to the divided image data of each block (color space read by an image scanner or the like or image data after color space conversion) (401).

The DCT converts input image data into spatial frequency component data. The upper leftmost coefficient of the 8 × 8 coefficient after conversion is called a direct current (DC) component, and has a value corresponding to the average value of the image data of the block before conversion. Excluding that
The 63 coefficients are called alternating current (AC) components, and indicate how many spatial frequency components corresponding to the position are included in the image data of the block before conversion.

Quantization is performed by dividing the converted DCT transform coefficient by a value obtained by multiplying 8 × 8 threshold values (hereinafter referred to as “quantization table”) by a scale factor (hereinafter referred to as “Q factor”) (402). ). In the case of the JPEG method, quantization is a major factor in determining the compression rate. In other words, if the Q factor is increased, the threshold value of the quantization table to be used is increased as a whole, so that the compression rate is improved, but the image information is suppressed as much, and the image quality is deteriorated. Conversely, if the Q factor is made smaller, the threshold value of the quantization table to be used becomes smaller as a whole, so the compression rate becomes worse, but the image quality improves.
In the JPEG-based baseline system, the quantization table used to quantize one page of image data has only one type of luminance component and one color component.

The quantized DCT coefficient is subjected to different encoding processing for the DC component and the AC component. The DC component uses the strength of the correlation between adjacent blocks to
Huffman coding is performed on the difference from the DC component of the × 8 block (403, 404). The AC component is subjected to zigzag scanning from low to high spatial frequencies in the block, rearranged in a one-dimensional array, and coefficients other than zero (effective coefficient) and the number of consecutive zeros (ineffective coefficient) ( Run length) and perform two-dimensional Huffman coding (405 to 40).
9).

The JPEG decoding process is basically the reverse of the encoding process. FIG. 2 is a diagram showing a decoding procedure of the baseline system. First, the coded data transmitted through the transmission path is decoded by Huffman decoding processing (901), the decoded one-dimensional array data is rearranged into the original two-dimensional array data (902), and the DC component is The DC component of the current block is obtained by adding the DC component of the block and the DC component of the current block (903). Since the AC component is not subjected to difference processing or the like at the time of encoding, the rearranged data is subjected to the subsequent processing as it is (904).

The DC component and the AC component after the addition processing are inversely quantized (905), and the two-dimensional inverse discrete cosine transform (hereinafter referred to as "IDCT
By performing (Inverse Discrete Cosine Transform), decoding of one block is completed (906). However, if the color space conversion is required, the color space conversion process is further performed, and the decoding of one block is completed. Therefore, many color image communication devices applying the JPEG baseline system perform color space conversion, DCT, quantization, Huffman coding, and other processing on image data during encoding, and perform all processing during decoding. Huffman decoding, inverse quantization, IDCT, color space conversion, and other processing are performed on the coded data. It should be noted that the JPEG method and the JBIG method are optimally applied according to the property of the image data to be encoded, the decoded image quality, and the encoding efficiency (compression rate).

3 to 6 are block diagrams showing the configuration of the encoding / decoding unit in the conventional data processing apparatus. In a conventional data processing device, when a monochrome image is MR-coded or MMR-coded, a binary coding unit 2 is configured as shown in FIG. 3, and a color image is JPEG system or JBIG-coded.
When encoding by the method, the multi-level encoding unit 3 is configured as shown in FIG. Further, when encoding a monochrome image and encoding a color image at the same time, simultaneous processing is enabled by configuring the encoding units of the respective encoding methods as shown in FIG.

Further, in the band scan system encoding / decoding process, when encoding and decoding by the same encoding system or encoding and decoding by different encoding systems are alternately performed, as shown in FIG. Dedicated units 5 and 6 for encoding and decoding respectively are provided.

[0011]

However, the above-mentioned conventional example has the following problems. When applying a plurality of coding methods, there is a drawback that a dedicated processing unit must be provided for each coding method to be applied. Also, when performing encoding and decoding, there is a drawback that dedicated processing units, that is, an encoding unit and a decoding unit, are required. In that case, the space and cost including the peripheral circuit of the encoding / decoding unit, and in the case of applying a plurality of encoding systems, the control of the peripheral circuit and each encoding / decoding unit becomes complicated, which is a problem.

The present invention is to solve all or each of the above problems. For example, even when a plurality of coding systems are applied, it is necessary to provide a dedicated processing unit for each coding system to be applied. It is an object of the present invention to provide a data processing device and a method therefor, which reduce the space and cost for providing a dedicated processing unit. Further, for example, even when encoding and decoding are performed, a dedicated processing unit is not required, a space and cost for providing the dedicated processing unit are reduced, and a data processing device and method for controlling the same are provided. The purpose is to provide.

[0013]

[Means for Solving the Problems] and

The present invention has the following structure as one means for achieving the above object. A data processing apparatus according to the present invention includes first storage means and second storage means for storing data, first processing means and second processing means for processing data according to a set processing procedure. , A control means for setting different processing procedures to the two processing means, and when data to be processed exists in one of the two storage means, the control means performs a processing procedure obtained by dividing a series of processing procedures. When the two processing means are set, the two processing means process the data in cooperation with each other, and the data to be processed exists in both of the two storage means, the control means controls the two processing means. The first processing procedure is set on one side and the second processing procedure is set on the other side, and the two processing means store the data to be processed stored in either of the two storage means according to the set processing procedure. Each place Characterized in that it.

The data processing method according to the present invention is
When there is data to be processed in one of the two storage means, a processing procedure obtained by dividing a series of processing procedures is set in the two processing means, and the data is processed in cooperation with the two processing means, If there is data to be processed in both of the two storage means, set the first processing procedure in one of the two processing means, the second processing procedure in the other, respectively,
It is characterized in that the two processing means are made to respectively process the data to be processed stored in either of the two storage means.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A data processing apparatus according to an embodiment of the present invention will be described in detail below with reference to the drawings. As a method for solving the above-mentioned problems of the prior art, a digital signal processor (hereinafter referred to as “DSP”) 7 as shown in FIG.
A data processing device having a configuration in which the encoding system is switched by changing the processing program downloaded to the instruction memory 8 by using the encoding / decoding unit.

FIG. 8 is a schematic block diagram showing an example of an encoding / decoding unit using such a DSP. In the figure, 102 is an image memory for storing image data to be encoded, 104a is a DSP for encoding the image data stored in the image memory 102, 111 is a dual port RAM (hereinafter referred to as a dual port RAM for storing data processed by the DSP 104a). "DPRA
M ”), 104b is a DSP for continuously encoding the data stored in the DPRAM 111, and 105 is a code memory for storing the code data obtained by the DSP 104b. The image memory 102 and the code memory 105 may be one memory divided into two areas.

Further, 107a and 107b are instruction memories, respectively, which store the processing programs of the DSPs 104a and 104b. Reference numeral 109 denotes a CPU, which is composed of, for example, a one-chip microprocessor, and which stores image memory 102, according to a program stored in a built-in ROM or the like.
DSP 104a and 104b, DPRAM 111, code memory 10
5 is controlled to download the processing programs of the DSPs 104a and 104b to the instruction memories 107a and 107b. The instruction memory 1
07a and 107b may be one memory divided into two areas.

According to the above configuration, the two DSPs are connected to the DPRAM1.
By connecting in series via 11, the encoding or decoding processing can be divided into two DSPs, the processing load per DSP can be reduced, and the encoding or decoding processing can be performed at high speed. For example, when JPEG encoding is performed with this configuration, the DSP 104a is caused to perform color space conversion and DCT of image data, the data in the process of processing is stored in the DPRAM 111, and the DSP
104b is made to perform subsequent processing, that is, quantization and Huffman coding. Also, JPEG decoding is the opposite. The DSP 104b is caused to perform Huffman decoding and inverse quantization of coded data, and the data in the process is processed by the DPRAM111.
And the subsequent processing, that is, IDC, in the DSP 104a.
Let T and color space conversion. Note that the processing contents assigned to the two DSPs are not limited to this.

FIG. 9 is a schematic block diagram showing a second example of the encoding / decoding unit using the DSP. In the figure, 116
Memory controllers 117 and 117 control data input / output of the image memory 102 and the code memory 105.
Then, the DSP 104a accesses the memory controller 116 to encode the image data, and the DSP 104b decodes the encoded data obtained via the memory controller 117.

According to this structure, two DSPs can be operated in parallel to perform encoding and decoding at the same time. Since encoding and decoding are performed by different configurations (DSP), the encoding and decoding may be the same encoding method or different encoding methods. Further, by making the processing programs downloaded to the instruction memories 107a and 107b both encoding programs, it is possible to cause two DSPs to perform encoding or decoding of different encoding methods.

However, the configuration example shown in FIG.
Since DSPs are connected in series via DPRAM, there remains a problem that encoding and decoding cannot be performed at the same time. Further, in the second configuration example shown in FIG. 9, two DSPs are operated in parallel between the image data memory and the code data data, one DSP is dedicated for encoding, and the other DSP is dedicated for decoding. In the case of only the operation of encoding or decoding, one DSP is stopped, and there remains a problem that the capacity of the device cannot be fully utilized.

FIG. 10 is a block diagram showing an example of the arrangement of a data processing apparatus according to an embodiment of the present invention. [Configuration] First, the main configuration of this embodiment will be outlined based on the operation at the time of encoding. The image memory 102 stores image data read by an image scanner and the like under the control of the memory controller 116.

The DSP 104a uses the access request signal 204
The image memory 102 is accessed via the memory controller 102, the read image data is encoded, and the processed data is stored in the DPRAM 111. The memory controller 116 also outputs an access permission signal 205 to the DSP 104a. DSP104b
Reads the data stored in the DPRAM 111, continuously performs an encoding process on the data, accesses the code memory 105 via the memory controller 117 by the access request signal 210, and processes the processed data (code data). It is stored in the code memory 105. The memory controller 117 also outputs an access permission signal 211 to the DSP 104b.

The instruction memories 107a and 107b respectively store the processing programs of the DSPs 104a and 104b downloaded by the CPU 109. Next, signals input to and output from the CPU 109 will be described. First, for the signal 215, the CPU 109 sends the image memory 10
2 is an access request signal that is output to the memory controller 116 when accessing 2, and a signal 216 is an access permission signal to the image memory 102 that the memory controller 116 outputs to the CPU 109. Similarly, the signal 217 is an access request signal output to the memory controller 117 when the CPU 109 accesses the code memory 105, and the signal 218 is the memory controller 11.
Reference numeral 7 is an access permission signal to the code memory 105 output to the CPU 109.

The signals 219 and 220 are respectively CP
U109 is a write signal and a read signal output to the image memory 102, the instruction memory 107a, and the code memory 105 when writing and reading data.
The signals 221 and 223 are output by the CPU 109 to the DSP.
An interrupt signal output to 104a and 104b,
The signals 222 and 224 are the DSPs 104a and 104b, respectively.
Is an interrupt signal output to the CPU 109.

Next, signals input to and output from the DSPs 104a and 104b will be described. First, for signals 225 and 226, the DSP 104a outputs the image memory 102 and the DPRAM 11 respectively.
1, a write signal and a read signal output to the code memory 105 when writing and reading data. Similarly,
Signals 227 and 228 are a write signal and a read signal, which are output when the DSP 104b writes and reads data in the image memory 102, DPRAM 111, and code memory 105, respectively.

The signals 114 and 115 are also sent to the DSP 104.
Reference symbols a and 104b are synchronization signals for synchronizing the processing with each other. The signal 237 is also used by the memory controller 11 when the DSP 104a accesses the code memory 105.
7 is a signal for requesting access to the code memory 105, which is output to the memory controller 7.
Is an access permission signal to the code memory 105 output to the DSP 104a. Similarly, the signal 239 is the DSP
The image memory 10 which is output to the memory controller 117 when the image memory 102 is accessed by the image memory 102.
The signal 240 is an access request signal to the image memory 102, and the signal 240 is an access permission signal to the image memory 102 output from the memory controller 116 to the DSP 104b.

Further, the bold lines in FIG. 10 are the main buses, and 231 is the data bus of the encoding / decoding processing unit, and 2
32 is the data bus of the DSP 104a, 233 is the DSP 104a
Address bus, 234 is the data bus of the DSP 104b,
235 is the address bus of the DSP 104b, 236 is the CPU 10
9 system buses. [Operation] Next, the operation of this embodiment will be described in detail.

FIG. 11 is a flow chart showing an example of the operation procedure of the present embodiment, which is executed by the CPU 109 when the present embodiment is started by turning on the power, resetting or the like. The CPU 109 executes the code memory 10 in step S1.
Check whether there is code data to be decoded in 5,
In steps S2 and S3, it is confirmed whether or not the image data to be encoded exists in the image memory 102.

Code data received from a communication line or the like exists in the code memory 105, and the image memory 102
If there is no image data to be encoded in, the decoding program is downloaded to the instruction memories 107a and 107b in step S4, and the decoding process whose details will be described later is executed in step S5. The program downloaded here is a program that causes two DSPs to perform decoding at high speed via the DPRAM 111, that is, a program that causes pipeline processing to perform decoding. For example, JP
Taking EG decoding as an example, the DSP 104b is caused to perform Huffman decoding and inverse quantization of code data, and the DSP 10b
4a is made to perform IDCT and color space conversion.

If there is no code data to be decoded in the code memory 105 and there is image data read by the image scanner in the image memory 102, the coding program is read in the instruction memories 107a and 107b in step S6. Download to step S7
Then, the encoding process whose details will be described later is executed. The program downloaded here is via DPRAM111
It is one that allows two DSPs to perform encoding at high speed, that is, one that causes pipeline processing to perform encoding. For example, taking JPEG encoding as an example, the DSP 104a
To perform color space conversion of image data and DCT, and DSP1
04b is made to perform quantization and Huffman coding.

Although the boundary of the process sharing related to the pipeline processing is not limited to the above, the operation when the above sharing is applied will be described below. Also,
If there is code data to be decoded in the code memory 105 and image data to be coded in the image memory 102, the coding program is downloaded to the instruction memory 107a and the decoding program is downloaded to the instruction memory 107b in step S8. Then
In step S9, an encoding / decoding process whose details will be described later is executed.

Next, the encoding process of step S7 will be described. FIG. 12 shows an example of the processing procedure of the DSP 104a, as shown in FIG.
Reference numeral 3 is a flow chart showing an example of the processing procedure of the DSP 104b, which will be described in detail later.
15 is executed in synchronization. First, the CPU
A reference numeral 109 downloads a program for performing initial processing into the instruction memories 107a and 107b. The DSPs 104a and 104b respectively perform step S30.
1. In S401, the download of the initial processing program is monitored, and when the download is completed, step S3
In 02 and S402, initial processing such as setting the above-mentioned access request signal, synchronization signal, and interrupt signal to initial values is executed.

Next, the CPU 109, for example, the instruction memory 107a, 1 of the JPEG processing program.
The download to 07b is started, and at the same time, a control signal is sent to an image scanner (not shown) to start reading the original. The image data for one scan output from the image scanner is sequentially stored in the image memory 102. The supply source of the image data is not limited to the image scanner, and may be an external device such as a host computer or a magnetic disk device. Then, when the image data to be encoded is accumulated in the image memory 102, the CPU 109 instructs the DSPs 104a and 104b to start the encoding process by the interrupt signals 221 and 223.

Processing procedure of DSP 104a The DSP 104a monitors the download of the processing program in step S303, and when the download is completed, waits for an instruction to start the processing by the interrupt signal 221 in step S304. Then, when instructed, the memory controller 11
6, the access request signal 204 indicating that the image memory 102 is accessed is output.

The memory controller 116 uses the DSP 104
When the access request signal 204 from a is received, DS
If the P104b or the CPU 109 is not accessing the image memory 102, the access permission signal 205 is output to the DSP 104a. When the access permission signal 205 is output from the memory controller 116, the DSP 104a passes the image memory 102 via the data bus 231 and the memory controller 116 in step S305.
Read the image data from. It should be noted that the DSP 104a is a predetermined unit (for example, 8
Read the image data of (× 8 block unit).

Subsequently, the DSP 104a carries out step S30.
The synchronization signal 115 is judged at 6 and waits until writing to the DPRAM 111 becomes possible, and when it becomes possible, step S307
Then, the program stored in the instruction memory 107a performs an encoding process (for example, color space conversion or DCT) on the read image data of a predetermined unit, and writes the processed data in the DPRAM 111 in step S308.

Subsequently, the DSP 104a carries out step S30.
At 9, the sync signal 114 is inverted and the DSP 104b is DPRAM.
After enabling the data to be read from 111, step S
In 310, it is determined whether or not there is image data to be encoded in the image memory 102, and if there is, the process returns to step S305. That is, steps S305 to S31 are performed until all the image data stored in the image memory 102 are processed.
Repeat 0.

Further, the DSP 104a is the image memory 102.
If there is no image data to be encoded in step S31, step S31
In step 1, the CPU 109 requests the next image data with the interrupt signal 222, and in step S321, the CP with the interrupt signal 221 is sent.
The process waits for an instruction to restart the process from U109, and if there is an instruction to restart the process, the process returns to step S305. For example, when processing band scan type image data as shown in FIG. 14 or processing a plurality of pages of image data, the CPU
A processing restart instruction is issued from 109. Further, in the standby state, when the CPU 109 issues a processing instruction again, the processing is restarted from step S305.

Processing procedure of DSP 104b The DSP 104b monitors the download of the processing program in step S403, and when the download is completed, determines the synchronization signal 114 in step S404 to determine the DPRAM 11
It waits until the reading from 1 becomes possible, and when the reading becomes possible, the processing of the data stored in the DPRAM 111 is started. That is, the data is read from the DPRAM 111 in a predetermined unit in step S405, the synchronization signal 115 is inverted in step S406 so that the DSP 104a can write the data in the DPRAM 111, and then the data is stored in the instruction memory 107b in step S407. The program performs an encoding process (for example, quantization or Huffman encoding) on the read image data of a predetermined unit, writes the code data in the code memory 105 in step S408, and then returns to step S404.

Writing to the code memory 105 by the DSP 104b is started by outputting an access request signal 210 to the code memory 105 to the memory controller 117. The memory controller 117, when the access request signal 210 is output, outputs the DSP 104a or C
If the PU 109 is not accessing the code memory 105, the access permission signal 211 is output. Therefore, DSP
104b is in a writing standby state of code data until the access permission signal 211 is output.

The DSP 104b enters the standby state if there is an instruction from the CPU 109 to end the processing by the interrupt signal 223 while waiting in step S404. Further, in the standby state, when the CPU 109 issues a processing instruction again, the processing is restarted from step S404. Further, the code data stored in the code memory 105 is sent to a line from a communication control device (not shown) or stored in a storage device (not shown) under the control of the CPU 109.

● Synchronization method Both DSPs use D based on the states of the synchronization signals 114 and 115.
The processing data is written in the PRAM111 and the data is read from the DPRAM111. That is, at the time of encoding, when the states of both synchronization signals are different, the DSP 104a causes the DPRAM 111
When the processed data is written to
The process is synchronized by reading the data from the PRAM 111.

FIG. 15 is a timing chart for explaining the synchronous relationship between the DSPs 104a and 104b. In the figure, if the synchronizing signal 114 is set to L level and the synchronizing signal 115 is set to H level in the initial processing of 601 and 613, the states of both synchronizing signals are different,
The DSP 104a reads the image data from the image memory 102 in 603, performs encoding processing in 604, and performs DP processing in 605.
Since the processing data is written in the RAM 111 and the synchronization signal 114 is inverted, after the image data is read again in 606, 6
At 07, it goes into the standby state.

On the other hand, the DSP 104b is the DPRAM 111 at first.
Since the data cannot be read from the device, the device enters the standby state at 614. When the sync signal 114 is inverted, 61
The processing data is read from the DPRAM 111 at 5 and the synchronization signal 1
After inverting 15 and performing encoding processing in 616, the code data is written in the code memory 105 in 617, and then the standby state is entered in 618.

When the sync signal 115 is inverted, the DSP 104
a performs encoding processing at 608 and DPRAM 11 at 609.
Write the processed data to 1 and invert the sync signal 114,
After the image data is read again in 10, the standby state is entered in 611. When the sync signal 114 is inverted, the DSP 10
4b again reads the data from DPRAM 111 at 619 and inverts the synchronization signal 115.

In this way, both DSPs repeat the above-mentioned encoding while taking the processing timing, and when the CPU 109 gives an instruction to end the processing, they enter the standby state. Although the encoding process has been described above, when the code data to be decoded exists in the code memory 105, the decoding process program is downloaded to the instruction memories 107a and 107b, and when the states of both sync signals are different, the DSP is used.
If the processing data is written in the DPRAM 111 by the 104b and the DSP 104a reads the data from the DPRAM 111 when they match each other, the decoding processing (step S5 of FIG. 11) can be realized by a procedure substantially reverse to the above. Alternatively, the states of the synchronization signals at the start of processing may be made to coincide with each other, and the DSP 104b may write processing data to the DPRAM 111 when the states of both synchronization signals coincide, and the DSP 104a may read the data from the DPRAM 111 when the states of the synchronization signals are different.

Simultaneous Processing of Encoding and Decoding In addition to the above-mentioned first processing operation of performing encoding or decoding, the present embodiment is the second processing operation of simultaneously performing encoding and decoding (step of FIG. 11). S9) is provided. The case where the image data stored in the image memory 102 is encoded by the JPEG method and the code data stored in the code memory 105 is decoded by the MMR method will be described below. However, as described above, the image data is downloaded to the instruction memory. The processing program is not limited by the encoding method.

FIG. 16 is a flowchart showing an example of the procedure of the encoding process of the DSP 104a, and FIG. 17 is a flowchart showing an example of the procedure of the decoding process of the DSP 104b. The same steps as those shown in FIG. 13 or 14 are designated by the same reference numerals, and detailed description thereof will be omitted. DSP104a
Is an interrupt signal 221 from the CPU 109 in step S304.
When a processing start instruction is issued by the memory controller 1,
16 to the access request signal 204 indicating that the image memory 102 is to be accessed, and step S305
The image data of a predetermined unit is read from the image memory 102. The CPU 109 instructs both DSPs to start processing at substantially the same time.

Subsequently, the DSP 104a carries out step S32.
In step 1, the read image data of a predetermined unit is encoded (for example, JPEG encoded) by the program stored in the instruction memory 107a, and the encoded data is written in the code memory 105. However, CP is stored in the code memory 105.
Since the U109 and the DSP 104b are also connected, this writing procedure is as follows.

First, the DSP 104a outputs an access request signal 237 to the code memory 105 to the memory controller 117. The memory controller 117 is a DS
When the access request signal 237 from the P104a is received, the DSP 104b or the CPU 109 causes the code memory 10
If not accessing 5, the access permission signal 238 is output to the DSP 104a. When the access permission signal 238 is output from the memory controller 117, the DSP 104a writes the code data in the code memory 105 via the data bus 231 and the memory controller 117 in step S322. However, the area of the code memory 105 in which the code data is written is a different area from the area in which the code data to be decoded is stored.

Subsequently, the DSP 104a carries out step S310.
The following processing is executed, but since these steps have been described above, the description thereof will be omitted. On the other hand, DSP104b
In step S421, when the CPU 109 gives an instruction to start processing by the interrupt signal 223, the memory controller 117
To the memory controller 11 by outputting an access request signal 210 indicating that the code memory 105 is to be accessed.
When the access permission signal 211 is output from 7, the code data of a predetermined unit is read from the code memory 105 in step S422.

Subsequently, the DSP 104b carries out step S42.
At 3, the program stored in the instruction memory 107b decodes the read code data of a predetermined unit (for example, MMR method), and writes the decoded data (that is, image data) to the image memory 102. However, since the CPU 109 and the DSP 104a are also connected to the image memory 102, the writing procedure is as follows.

First, the DSP 104b outputs an access request signal 239 to the image memory 102 to the memory controller 116. The memory controller 116 is a DS
At the time when the access request signal 239 from the P104b is received, the DSP 104a or the CPU 109 makes the image memory 10
If not accessing 2, the access permission signal 240 is output to the DSP 104b. When the access permission signal 240 is output from the memory controller 116, the DSP 104b writes the decoded data to the image memory 102 via the data bus 231 and the memory controller 116 in step S424. However, the area of the image memory 102 where the decoded data is written is a different area from the area where the image data to be encoded is stored.

The DSP 104b then proceeds to step S42.
In step 5, it is determined whether or not there is code data to be decoded in the code memory 105, and if there is code data, the process returns to step S422, and if not, the standby state is entered. That is, the code memory 105
Steps S422 to S425 are repeated until all the code data stored in is decoded. The CPU 109
Under the control of the DSP 104a, the code data encoded by the DSP 104a is sent to a line from a communication control device (not shown) or stored in a storage device (not shown).
The image data decoded by 4b is sent to a printer (not shown) of a laser beam system or an inkjet system to be recorded on recording paper or the like, or sent to a host computer or a display (not shown) to be stored or displayed.

The access request signal to the image memory 102 and the access request signal to the code memory 105 of the DSPs 104a and 104b described above are active while the memory is being accessed. As described above, the second processing operation independently encodes the image data stored in the image memory 102 and decodes the code data stored in the code memory 105 without using the DPRAM 111. is there.

The CPU 109 uses the DSP 10 for each transmission original.
It is possible to download the encoding or decoding processing program into the instruction memories 4a and 104b. As described above, according to this embodiment, even when a plurality of coding methods are applied, it is not necessary to provide a dedicated processing section for each coding method to be applied, and a space for providing a dedicated processing section is provided. And cost can be reduced. Further, even when performing encoding and decoding, it is possible to reduce the space and cost for providing the dedicated processing unit and facilitate the control without requiring the dedicated processing unit for each.

Furthermore, two DSPs can be connected in series via DPRAM to operate, or two DSPs can be operated in parallel, and an appropriate operation according to processing can be performed. In other words, when encoding and decoding, the two DSPs can be operated in parallel to fully utilize the capabilities of the device. Also, when only encoding or decoding is performed, two DSPs can be connected in series and operated to obtain high-speed processing.

The present invention may be applied to either a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0060]

As described above, according to the present invention,
Even when applying a plurality of encoding methods, it is not necessary to provide a dedicated processing section for each encoding method to be applied, and a data processing apparatus and method for reducing the space and cost for providing the dedicated processing section are provided. can do.

Further, even when encoding and decoding are performed, a dedicated processing unit is not required for each, a space and cost for providing a dedicated processing unit are reduced, and a data processing device and its control are facilitated. A method can be provided. Further, the two processing units can be connected in series to operate, or the two processing units can operate in parallel, and an appropriate operation according to the processing can be performed. For example, when performing encoding and decoding, the two processing units can be operated in parallel to make full use of the capabilities of the device. When only encoding or decoding is performed, two processing units can be connected in series and operated to obtain high-speed processing.

[Brief description of drawings]

FIG. 1 is a diagram showing a data compression procedure of a JPEG baseline system.

FIG. 2 is a diagram showing a decoding procedure of a JPEG baseline system.

FIG. 3 is a block diagram showing a configuration of an encoding / decoding unit in a conventional data processing device.

FIG. 4 is a block diagram showing a configuration of an encoding / decoding unit in a conventional data processing device.

FIG. 5 is a block diagram showing a configuration of an encoding / decoding unit in a conventional data processing device.

FIG. 6 is a block diagram showing a configuration of an encoding / decoding unit in a conventional data processing device.

FIG. 7 is a diagram showing a data processing device configured to switch encoding systems by changing a processing program to be downloaded according to the present invention.

FIG. 8 is a schematic block diagram showing an example of an encoding / decoding unit of the apparatus in FIG.

9 is a schematic block diagram showing a second example of the encoding / decoding unit in FIG. 7. FIG.

FIG. 10 is a block diagram showing a configuration example of a data processing device according to an embodiment of the present invention.

FIG. 11 is a flowchart showing an example of an operation procedure of the present embodiment.

12 is a flowchart showing an example of the processing procedure of the DSP 104a in FIG.

13 is a flowchart showing an example of the processing procedure of the DSP 104b in FIG.

FIG. 14 is a diagram showing an example of a band scan method.

FIG. 15 is a timing chart illustrating a synchronization relationship between DSPs 104a and 104b in FIG.

16 is a flowchart showing an example of the procedure of an encoding process of the DSP 104a in FIG.

17 is a flowchart showing an example of the procedure of a decoding process of the DSP 104b shown in FIG.

[Explanation of Codes] 102 Image Memory 104a, 104b DSP 105 Code Memory 107a, 107b Instruction Memory 109 CPU 111 DPRAM 116, 117 Memory Controller

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Claims (6)

[Claims] 1. A first storage means and a second storage means for storing data; a first processing means and a second processing means for processing data according to a set processing procedure; The processing means includes a control means for setting different processing procedures, and when data to be processed exists in one of the two storage means, the control means divides a series of processing procedures into the two processing procedures. When the two processing means cooperate with each other to process the data, and the data to be processed exists in both of the two storage means, the control means sets the first processing means in one of the two processing means. A second processing procedure is set to one processing procedure to the other, and the two processing means process the data to be processed stored in either of the two storage means according to the set processing procedure. Features Data processing apparatus for. 2. When the image data to be encoded exists in the first storage means and the code data to be decoded exists in the second storage means, the control means encodes in the first processing means. A decoding procedure is set in each of the second processing means, the first processing means encodes the image data, and the second processing means decodes the encoded data. Item 1. The data processing device according to item 1. 3. The first processing means stores the coding result of the image data in the second storage means, and the second processing means stores the decoding result of the code data in the first storage means. The data processing device according to claim 2, wherein the data processing device stores the data in the data processing device. 4. Further, a third storage means is provided between the two processing means, and when the two processing means cooperate with each other to execute a series of processing, the third storage means is used. The data processing apparatus according to claim 1, wherein the data processing apparatus exchanges data. 5. The data processing apparatus according to claim 1, wherein the division of the processing procedure is set in advance so that loads of the two processing means are substantially equal to each other. 6. When data to be processed exists in one of the two storage means, a processing procedure obtained by dividing a series of processing procedures is set in the two processing means, and the processing procedure is performed in cooperation with the two processing means. When data is to be processed, and there is data to be processed in both of the two storage means, the first processing procedure is set in one of the two processing means and the second processing procedure is set in the other, respectively, and A data processing method comprising causing two processing means to respectively process the data to be processed stored in either of the two storage means.