JP3382298B2 - Image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, for example, an image processing apparatus such as a color image communication apparatus which encodes and decodes multivalued color image data by the ADCT method.

[0002]

2. Description of the Related Art FIG. 16 is a diagram showing the configuration of a conventional color image communication apparatus. In the figure, an image reading unit 101 scans a document image and outputs multivalued RGB digital signals. An image memory 103 is an image reading unit 1
The image data read at 01 or the image data obtained by decoding the code data received via the line is accumulated.

An image printing unit 102 is an image memory 103.
The image represented by the color multi-valued digital signal input from is printed in color. Reference numeral 110 denotes a digital signal processing unit (hereinafter referred to as “DSP”) that encodes image data read from the image memory 103 or decodes code data received via a line.

A code memory 107 stores code data coded by the DSP 110 or code data received via a line. A line control unit 108 controls transmission of code data to the line or reception of code data from the line. A CPU 109 monitors and controls each component via the CPU bus B109. Note that I111
Is an interrupt signal line from the CPU 109 to the DSP 110, I
Reference numeral 112 is an interrupt signal line from the DSP 110 to the CPU 109.

First, the operation of encoding image data will be described. FIG. 17 is a flowchart showing the encoding processing procedure of the DSP 110, showing encoding of one block of image data. The image reading unit 101 scans the original image, and the image data output from the image reading unit 101 is temporarily stored in the image memory 103. The image memory 103 has three
A port memory, which is an input / output device for the image reading unit 101 or the image printing unit 102, and the CPU 109 and DS
It can be accessed asynchronously from P110.

In step S1, the DSP 110 adds a margin as necessary to fit a predetermined size, reads one block of image data from the image memory 103 in the image area other than the margin area, and in step S2. , The color space of the image data is converted to the color space on the line, for example, the YCbCr color space. Subsequently, the DSP 110 performs sub-sampling processing in step S3, DCT processing in step S4, quantization in step S5, and zigzag scanning in step S6 on the image data subjected to color space conversion,
In step S7, Huffman coding is performed, the obtained code data is stored in the code memory 107, and the coding for one block of image data is completed.

The code memory 107 is also a three-port memory, and includes a DSP 110, a line controller 108 and a CPU.
It is possible to access from 109 asynchronously. The line control unit 108 also reads the code data from the code memory 107 and sends the code data to the line. Next, the operation of decoding the received coded data will be described. Figure 18 shows DSP1
10 is a flowchart showing a decoding process procedure of 10, showing decoding of one block of image data.

Code data received from the line by the line control unit 108 is stored in the code memory 107. D
The SP 110 reads the code data from the code memory 107, performs Huffman decoding in step S11, and
At 12, the order of the data rearranged by the zigzag scan at the time of encoding is returned.

Subsequently, the DSP 110 dequantizes the data whose order has been restored in step S13, and in step S14, performs inverse DCT (hereinafter referred to as "IDCT") processing and incorporates the operation result. Store in RAM. Subsequently, the DSP 110 reads out the operation result stored in the built-in RAM, returns the sub-sampling at the time of encoding in step S15, and converts the color space of the image data into the color space on the line (for example, YCbCr color space) in step S16. From a color space that can be printed out (for example, CMYK color space),
In step S17, the blank space added at the time of encoding is removed and stored in the image memory 103, and the decoding of one block of image data is completed.

The image data stored in the image memory 103 is sent to the image printing unit 102 to print the received image.

[0011]

However, the above-mentioned conventional example has the following problems. That is, the above-mentioned conventional example has a drawback that the processing time becomes long because the image processing is performed by one DSP.

The present invention is intended to solve the above problems, and an object of the present invention is to reduce the processing time by causing two signal processing means to perform image processing.

[0013]

The present invention has the following structure as one means for achieving the above object. An image processing apparatus according to the present invention processes a first storage unit for storing image data, a second storage unit for storing code data, and image data stored in the first storage unit in block units. Then, the image processing apparatus is provided with a processing unit that stores the data in the second storage unit, decodes the code data stored in the second storage unit in block units, and stores the decoded data in the first storage unit. In the processing or decoding, the processing means performs the first signal processing means and the other processing that perform one of the first and second processings that should be continuously performed in the block unit. A RAM that mediates the exchange of processing target data in block units between the second signal processing means and the two signal processing means.
And the two signal processing means, the two signal lines connecting the two, mutually transmit a status signal indicating the access state to the RAM, the status signal of the two signal lines of Whether or not the data writing operation in the block unit to the RAM or the data reading operation in the block unit from the RAM is determined according to the coincidence or non-coincidence.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image processing apparatus according to an embodiment of the present invention will be described in detail below with reference to the drawings.

[0015]

[First Embodiment] FIG. 1 is a block diagram showing an example of the arrangement of a color image communication apparatus according to the first embodiment. It should be noted that, in FIG. 1, for the configuration substantially similar to the conventional example shown in FIG.
The same reference numerals are given and detailed description thereof is omitted. In the figure, reference numeral 104 denotes DSPa, which performs pre-coding processing or post-decoding processing to be described later in detail.

Reference numeral 105 denotes a DSPb which performs post-coding processing or pre-decoding processing, which will be described in detail later. 106 is a RAM, which is composed of a dual-port RAM,
It mediates data between Pa104 and DSPb105. In addition, there are the following signal lines related to the two DSPs. P101 is DSPa104 to DSPb1
Signal line for sending status to 05, P102 is DSPb10
Signal line for sending status from 5 to DSPa104, I10
1 is an interrupt signal line from CPU 109 to DSPa 104, I 102 is an interrupt signal line from DSPa 104 to CPU 109, I 103 is an interrupt signal line from CPU 109 to DSPb 105, and I 104 is DSPb 105 to CPU 1.
It is an interrupt signal line to 09.

First, the operation of encoding image data will be described. FIG. 2 is a flowchart showing an example of the coding processing procedure of this embodiment, and shows coding of one block of image data. Note that FIG. 9A is executed by the DSPa 104, and FIG. 9B is executed by the DSP b 105. Further, in the following description, an example in which one block has 8 × 8 pixels is shown, but the present embodiment is not limited to this.

The original image is scanned by the image reading unit 101,
The RGB image data output from the image reading unit 101 is
It is temporarily stored in the image memory 103. DSPa104
In step S21, a blank space is added as necessary to fit a predetermined size, and one block of image data is read from the image memory 103 in the image region other than the blank region.

FIG. 3 is a diagram showing an example of a margin added in step S21.
Margin 8 in the image area 803 scanned with a scanning resolution of 400 dpi
01 and 802 are added, and A4 of G4 facsimile is added.
An example of matching the size is shown. Then, DSPa1
A step 04 converts the color space of the image data into a color space on the line, for example, a YCbCr color space in step S22. This conversion is performed by the following equation, for example.

[0020] Then, DSPa104 performs a sub-sampling process by step S23. This processing reduces the color difference data Cb and Cr by utilizing the characteristics that the human eye is sensitive to luminance and insensitive to color difference. For example, by taking the average value of two adjacent color difference data and reducing the amount of color difference data to 1/2, the ratio of each data is Y: Cb: Cr = 1: 1:
Use 1,2: 1: 1 or 4: 1: 1.

Subsequently, the DSPa 104 executes step S2.
In step 4, the status signals P101 and P102 are compared, and when the states of both signals match, when the states of both signals match, in step S25, one-dimensional DCT processing in the horizontal direction is performed, and the calculation is performed. The results are sequentially stored in the RAM 106. Note that the DCT processing in the ADCT is two-dimensional, but in the present embodiment, one-dimensional DCT is performed twice in the horizontal direction and the vertical direction. The following equation is a transformation equation for one-dimensional DCT processing in the horizontal direction.

[0022] When the DCT process ends, the DSPa 104 executes step S
The status signal P101 is inverted at step 26, and thereafter, the processing relating to this data is performed by the DSPb1 according to the procedure shown in FIG.
05 executes.

In step S31, the DSPb 105 waits for the status signals P101 and P102 to become inconsistent, and if both signals do not match, RA is executed in step S32.
The operation data is read from M106 and stored in the internal RAM, and the status signal P102 is inverted in step S33. Subsequently, in step S34, the DSPb 105 adds one-dimensional DC in the vertical direction to the operation data stored in the internal RAM.
Perform T processing. The conversion formula is the same as that shown in formula (2).

Subsequently, the DSPb 105 has a step S3.
5, using the Y component quantization table and the C component quantization table, an example of which is shown in FIGS. 4A and 4B, respectively,
Quantization is performed by dividing each coefficient after DCT processing by the threshold value at the corresponding position in both quantization tables. Subsequently, in step S36, the DSPb 105 performs zigzag scanning in the order of 0 to 63, an example of which is shown in FIG.
The quantized data is rearranged into one dimension, and step S37 is performed.
Then, the Huffman coding is performed on the quantized data rearranged in one dimension, and the code data is stored in the code memory 107.

In the Huffman coding, the DC coefficient at the position of "0" and the AC coefficient at the position of "1" to "63" in FIG. 5 are differently coded. First, the DC coefficient is the D of the same component (Y, Cr or Cb) of the block encoded immediately before.
The difference from the C coefficient is obtained, and the group number SSSS and the number of additional bits are determined according to the relationship between the DC difference and the group number SSSS, an example of which is shown in FIG. The group number SSSS is Huffman-coded by referring to the Huffman table, and additional bits are added after that. On the other hand, the AC coefficient counts 0 until a coefficient other than 0 is sequentially found from "1" in a state where the AC coefficients are one-dimensionally arranged in the order of "1" to "63" shown in FIG. 0
If a coefficient other than is found, the group number SSSS and the number of additional bits are determined according to the relationship between the AC coefficient and the group number SSSS, an example of which is shown in FIG. The group number SSSS and the count value NNNN of coefficient 0 are Huffman-coded by referring to the Huffman table, and additional bits are added thereafter.

Although one block has been described above in the order of processing, the DSPa 104 and the DSP b10 are actually used.
5 operates in parallel by pipeline processing. For example, when the DSPb 105 is processing the Nth block, the DSPa 104 is processing the N + 1th block. FIG. 8 is a timing chart showing an example of parallel operation in encoding, where (a) is DSPa104.
, (B) shows the status of the status signal P101, (c) shows the processing details of the DSP b105, and (d) shows the status of the status signal P102.

In the figure, first, signals P101 and P1
02 is at L level. The DSPa 104 executes margin addition (S21), color space conversion (S22), and sub-sampling (S23), then confirms P101 = P102 in S24, executes DCT in the horizontal direction (S25), and outputs the signal in S26. Invert P101. Subsequently, the DSPa 104 shifts to the processing of the next block.

On the other hand, the DSPb 105 waits until the signal P101 is inverted (S31), and when the signal P101 is inverted, the DSPb 105 reads the RAM 106 (S32), and then S
At 33, the signal P102 is inverted. Then, the vertical DCT
(S34), quantization (S35), zigzag scan (S
36), Huffman coding (S37) is executed, and the processing for one block is completed. Subsequently, the DSPb 105 proceeds to the processing of the next block, but if P101 ≠ P102 in S31, the RAM 106 is immediately read out (S32).

Hereinafter, the above-mentioned processing is performed by the DSPa 104 and the DS.
Although it is repeated in Pb105, Huffman coding (S37) has the largest variation in processing time among the respective processing. Therefore, when the Huffman encoding (S37) of the DSPb 105 is prolonged and the sub-sampling (S23) of the DSPa104 is completed and the status signal P102 is not inverted, as shown by S24 in FIG. P101 =
DSPa104 will wait until P102. That is, the DSPa 104 and the DSP b 105 mutually monitor the status signals of the other party to synchronize with each other to realize parallel processing.

Next, the operation of decoding coded data will be described. FIG. 9 is a flowchart showing an example of the decoding processing procedure of the present embodiment, and shows decoding of one block of image data. Note that FIG. 9A is executed by the DSPa 104, and FIG. 9B is executed by the DSP b 105.
Further, in the following description, an example in which one block has 8 × 8 pixels is shown, but the present embodiment is not limited to this.

Code data received by the line control unit 108 via the line is stored in the code memory 107. The DSPb 105 has the code memory 1 in step S51.
The coded data is read from H.07, Huffman decoding is performed, the order of the data rearranged by the zigzag scan at the time of encoding is returned in step S52, and the quantum for the Y component shown in FIGS. 4A and 4B is returned in step S53. Table and C
Inverse quantization is performed using the component quantization table.

Subsequently, the DSP 105b carries out step S5.
In step 4, the status signals P101 and P102 are compared, and when the states of both signals match, when the states of both signals match, in step S55, one-dimensional horizontal IDCT processing is performed, and the calculation result Are sequentially stored in the RAM 106. The following expression is a conversion expression for horizontal one-dimensional IDCT processing. When the IDCT processing is completed, the DSPb 105 executes step S
At 56, the status signal P102 is inverted, and thereafter, the processing relating to this data is DSPa1 in the procedure shown in FIG.
04 executes.

In step S41, the DSPa 104 waits for the status signals P101 and P102 to become inconsistent, and when they do not match, RA is executed in step S42.
The operation data is read from M106 and stored in the internal RAM, and the status signal P101 is inverted in step S43. Subsequently, in step S44, the DSPa 104 adds a one-dimensional ID in the vertical direction to the operation data stored in the internal RAM.
Perform CT processing. The conversion formula is the same as that shown in formula (3).

Subsequently, the DSPa 104 carries out step S4.
Subsampling at the time of encoding is returned in step 5, and step S4
6, the color space of the image data is changed from the color space on the line, for example, the YCbCr color space, to a color space convenient for printing, for example, CM.
Convert to Y color space. Subsequently, in step S47, the DSPa 104 removes the blank space added at the time of encoding and stores the image data in the image memory 103. Image memory 1
The image data stored in 03 is sent to the image printing unit 102, and the received image is printed out.

Although one block has been described above in the order of processing, the DSPb105 and DSPa10 are actually used.
4 operates in parallel by pipeline processing. For example, when the DSPa 104 is processing the Nth block, the DSPb 105 is processing the (N + 1) th block. FIG. 10 is a timing chart showing an example of parallel operation in decoding, where (a) is DSPb105.
, (B) shows the status of the status signal P102, (c) shows the processing details of the DSPa104, and (d) shows the status of the status signal P101.

In the figure, first, signals P101 and P1
02 is at L level. The DSPb 105 returns the Huffman decoding (S51) and the zigzag scan (S5).
2), after inverse quantization (S53) is performed, P10 is performed in S54.
1 = P102 is confirmed, horizontal IDCT (S55) is executed, and the signal P102 is inverted in S56. Then, DSPb
105 moves to the processing of the next block.

On the other hand, the DSPa 104 waits until the signal P102 is inverted (S41). When the signal P102 is inverted, the DSP 106 reads the RAM 106 (S42) and then S
At 43, the signal P101 is inverted. Then the vertical IDCT
(S44), subsampling is returned (S45), color space conversion (S46) and blank removal (S47) are executed, and the processing for one block is completed. Subsequently, the DSPa 104 proceeds to the processing of the next block, but if P101 ≠ P102 in S41, the RAM 106 is immediately read (S42).

Hereinafter, the above processing is performed by the DSPb 105 and the DS.
Although it is repeated in Pa104, Huffman decoding (S51) is the one in which the processing time varies most among the processing. Therefore, when the Huffman decoding (S51) of the DSPb 105 is prolonged and the margin signal removal (S47) of the DSPa 104 is completed and the status signal P102 is not inverted, as shown in S41 in FIG. The DSPa 104 will wait until ≠ P102. That is, similar to the encoding process, DSPb105 and DSPa1
04 monitor each other's status signals to achieve parallel processing in synchronization with each other.

The interface between the CPU 109 and the DSPa 104 uses the interrupt signal lines I101 and I102 and part of the image memory 103. CPU109 is DS
When instructing Pa 104 to start the processing, whether the processing is encoding or decoding, necessary parameters such as the subsampling ratio and the image size are written in a predetermined area of the image memory 103, and the interrupt signal line I101 is set. Start the process via. In addition, DSPa104
When the processing is completed, the CP is sent via the interrupt signal line I102.
Notify U109 of the end.

The interface between the CPU 109 and the DSPb 105 is the interrupt signal lines I103, I104 and the code memory 10.
Using part of 7 to pass parameters and start processing. The same operation as in the case of DSPa104 is performed. As described above, according to the present embodiment, the pipeline processing is executed using the two DSPs to perform the image processing such as the encoding / decoding processing by the ADCT, the color space conversion, the subsampling, and the margin addition / removal. This has the effect of speeding up the overall processing.

[0041]

[Second Embodiment] A second embodiment of the present invention will be described below. In addition, in the second embodiment, the same reference numerals are given to the substantially same configurations as those of the first embodiment shown in FIG. 1, and the detailed description thereof will be omitted. FIG. 11 is a block diagram showing a configuration example of the color image communication device of the second embodiment.

In the first embodiment shown in FIG. 1, DSPa1
04, which mediates data between 04 and DSPb105
Although M106 was present, in this embodiment, DSPa104
And the DSPb 105 directly exchange data. First, the operation of encoding image data will be described. Each process described below is substantially the same as the process having the same name described in the first embodiment, and the detailed description thereof will be omitted.

FIG. 12 is a flow chart showing an example of the coding processing procedure of this embodiment, which shows coding of one block of image data. In addition, FIG.
Is executed by the DSP b 105 shown in FIG. Further, in the following description, one block is 8
An example of x8 pixels is shown, but the present embodiment is not limited to this.

The original image is scanned by the image reading unit 101,
The RGB image data output from the image reading unit 101 is
It is temporarily stored in the image memory 103. DSPa104
In step S121, a blank space is added as necessary to fit a predetermined size, and one block of image data is read from the image memory 103 in an image region other than the blank region.

Subsequently, the DSPa 104 executes step S1.
At 22, the color space of the image data is converted into the color space on the line, for example, the YCbCr color space. This conversion is performed by the equation (1). Then, DSPa104 is step S
Sub-sampling processing is performed at 123, and one-dimensional DCT processing in the horizontal direction is performed at step S124. The conversion formula is the same as that shown in formula (2).

When the DCT process is completed, DSPa104
Inverts the status signal P101 in step S125, and in step S126, status signals P101 and P102.
Wait until the state of both signals becomes inconsistent by comparing
When the states of both signals do not match, the operation data is transmitted to the DSPb 105 in step S127. After that, the processing related to this data is performed by the DSPb in the procedure shown in FIG.
105 executes.

The DSPb 105, in step S131,
Waiting for the status signals P101 and P102 to become inconsistent. When the status signals P101 and P102 do not match, the operation data is received from the DSPa 104 in step S132, and step S1
At 33, one-dimensional vertical DCT processing is performed. The conversion formula is the same as that shown in formula (2). Then, DS
In step S134, the Pb 105 uses the Y component quantization table and the C component quantization table shown in FIGS. 4A and 4B, respectively, to determine the respective coefficients after the DCT processing in both quantization tables. Quantize by dividing by the threshold of the corresponding position.

Subsequently, the DSPb 105 executes the step S1.
At 35, zigzag scanning is performed in the order of 0 to 63 shown in FIG. 5, and the quantized data is rearranged into one dimension,
In step S136, the Huffman coding is performed on the quantized data rearranged in one dimension, and the code data is stored in the code memory 10
Store in 7. The above description has been given for one block in the order of processing, but in reality, DSPa104 and DSPb1
05 is operated in parallel by pipeline processing,
For example, when DSPb 105 is processing the Nth block, DSPa 104 is processing the N + 1th block.

FIG. 13 is a timing chart showing an example of parallel operation in encoding. (A) shows the processing contents of DSPa104, (b) shows the state of status signal P101,
(C) shows the processing contents of the DSPb 105, and (d) shows the state of the status signal P102. In the figure, the signals P101 and P102 are initially at the L level. The DSPa 104 adds a margin (S121), color space conversion (S122), sub-sampling (S123),
After executing DCT in the horizontal direction (S124), the signal P101 is inverted in S126, P101 ≠ P102 is confirmed in S127, and data is transmitted (S127). Then, DSPa
104 moves to the processing of the next block.

On the other hand, the DSPb 105 waits until the signal P101 is inverted (S131), and when the signal P101 is inverted, receives the data (S132). Then, DSPb
Reference numeral 105 denotes vertical DCT (S133) and quantization (S1).
34), zigzag scanning (S135), and Huffman coding (S136) are performed, and then P102 is inverted in S137, and the process for one block is completed. Next, DSP
b105 moves to the processing of the next block, but in S131 P10
If 1 ≠ 102, the data reception (S132) is immediately executed.

Hereinafter, the above-mentioned processing is executed by the DSPa 104 and the DS.
Although it is repeated in Pb105, Huffman coding (S136) is the one in which the processing time varies most among the processing.
Therefore, Huffman coding of DSPb105 (S136)
Is prolonged and DSPa104 inverts the status signal P101 (S125), if the status signal P102 is not inverted, or the Huffman coding (S136) of the DSPb105 is completed in a short time, and the DCT of the DSPa104 is terminated.
If the processing (S124) is not completed, as in S126 or S131 indicated by * in FIG. 13, P101
DSPa104 or DSPb10 until ≠ P102
5 will wait. That is, the DSPa 104 and the DSP b 105 mutually monitor the status signals of the other party to synchronize with each other to realize parallel processing.

Next, the operation of decoding coded data will be described. Each process described below is substantially the same as the process having the same name described in the first embodiment, and the detailed description thereof will be omitted. FIG. 14 is a flowchart showing an example of the decoding processing procedure of the present embodiment, and shows decoding of one block of image data. Note that FIG. 9A is executed by the DSP b 105, and FIG. 9B is executed by the DSPa 104. Further, in the following description, an example in which one block has 8 × 8 pixels is shown, but the present embodiment is not limited to this.

Code data received by the line control unit 108 via the line is stored in the code memory 107. The DSPb 105 reads out the coded data from the code memory 107 in step S151 and performs Huffman decoding, returns the order of the data rearranged by the zigzag scan at the time of encoding in step S152, and step S153.
Then, dequantization is performed using the Y component quantization table and the C component quantization table shown in FIGS. 4A and 4B.

Subsequently, the DSP 105b carries out step S1.
At 54, one-dimensional horizontal IDCT processing is performed. The conversion formula is the same as that shown in formula (3). When the IDCT processing is completed, the DSPb 105 inverts the status signal P102 in step S155, compares the status signals P101 and P102 in step S156, waits for the status of both signals to become inconsistent, and then waits for the status of both signals. If the values do not match, the operation data is transmitted to the DSPb 105 in step S157. After that, the process related to this data will be described in FIG.
The DSPa 104 executes the procedure shown in (b).

In step S141, the DSPa 104
Waiting for the status signals P101 and P102 to become inconsistent. When the status signals P101 and P102 do not match, operation data is received from the DSPb 105 in step S142, and step S1
At 43, one-dimensional IDCT processing in the vertical direction is performed. The conversion formula is the same as that shown in formula (3). When the IDCT processing ends, the DSPa 104 returns the sub-sampling at the time of encoding in step S144, and in step S145,
The color space of the image data is the color space on the line, for example YCb.
A color space that is convenient for printing from the Cr color space, such as CMYK
Convert to color space.

Subsequently, the DSPa 104 executes step S1.
In 46, the blank space added at the time of encoding is removed, the image data is stored in the image memory 103, and the status signal P101 is inverted in step S147. The image data stored in the image memory 103 is sent to the image printing unit 102,
The received image is printed out. Although the above has been described for one block in the order of processing, in reality, the DSPb105
And DSPa104 operate in parallel by pipeline processing. For example, when DSPa104 is processing the Nth block, DSPb105 is
Processing the second block.

FIG. 15 is a timing chart showing an example of parallel operation in decoding. (A) shows the processing contents of the DSPb 105, (b) shows the status of the status signal P102,
(C) shows the processing contents of the DSPa 104, and (d) shows the state of the status signal P101. In the figure, the signals P101 and P102 are initially at the L level. The DSPb 105 uses Huffman decoding (S151),
The zigzag scan is returned (S152), the inverse quantization (S1)
53), the horizontal IDCT (S154) is executed, and S15
After inverting the signal P102 in step 5, P101 ≠ P102 in step S156.
Is confirmed and the data is transmitted (S157). continue,
The DSPb 105 moves to the processing of the next block.

On the other hand, the DSPa 104 waits until the signal P102 is inverted (S141), and when the signal P102 is inverted, receives the data (S142). Then, DSPa
104 performs IDCT (S143) in the vertical direction, returns subsampling (S144), performs color space conversion (S145), removes blanks (S146), and inverts the status signal P101 in step S147 to process one block. To finish. Subsequently, the DSPa 104 proceeds to the processing of the next block, but if P101 ≠ P102 in S141, the next data is immediately received (S142).

Hereinafter, the above processing is performed by the DSPb 105 and the DS.
Although it is repeated in Pa104, Huffman decoding (S151) is the one in which the processing time varies most among the processing. Therefore, when the Huffman decoding (S151) of the DSPb 105 is lengthened and the margin removal (S146) of the DSPa104 ends, if the status signal P102 is not inverted, as shown in S141 in FIG. ≠
DSPa104 will wait until P102. That is, similarly to the encoding process, the DSPb 105 and the DSPa 104 monitor the status signals of the other parties to achieve the parallel processing in synchronization with each other.

As described above, according to this embodiment,
Although it has substantially the same effect as the first embodiment, the cost can be reduced because the RAM 106 is not required. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device. Also,
It goes without saying that the present invention can also be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0061]

As described above, according to the present invention,
Two signal processing means that perform image processing monitor the status signals of the other party to determine whether to read / write the RAM that mediates the exchange of block-based processing target data, and perform image processing in parallel. You can Therefore, for example, by pipeline processing using two DSPs, image processing can be speeded up and processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a color image communication apparatus according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a code processing procedure of the present embodiment.

FIG. 3 is a diagram showing an example of a margin added by “add margin” in FIG.

FIG. 4 is a diagram showing an example of a quantization table according to the present embodiment.

FIG. 5 is a diagram showing an example of a zigzag scan sequence according to the present embodiment.

FIG. 6 is a diagram showing an example of a relationship between a DC difference, a group number, and an additional bit number according to the present embodiment.

FIG. 7 is a diagram showing an example of a relationship between an AC coefficient, a group number, and an additional bit number according to the present embodiment.

FIG. 8 is a timing chart showing an example of parallel operations in the encoding of this embodiment.

FIG. 9 is a flowchart showing an example of a decoding processing procedure according to the present embodiment.

FIG. 10 is a timing chart showing an example of parallel operations in decoding according to the present embodiment.

FIG. 11 is a block diagram showing a configuration example of a color image communication apparatus according to a second embodiment of the present invention.

FIG. 12 is a flowchart showing an example of the encoding processing procedure of the second embodiment.

FIG. 13 is a timing chart showing an example of parallel operations in the encoding of the second embodiment.

FIG. 14 is a flowchart illustrating an example of a decoding processing procedure according to the second embodiment.

FIG. 15 is a timing chart showing an example of parallel operations in the decoding of the second embodiment.

FIG. 16 is a diagram showing a configuration of a conventional color image communication device.

17 is a flowchart showing a code processing procedure of the DSP of FIG.

18 is a flowchart showing a decoding processing procedure of the DSP of FIG.

[Explanation of symbols]

101 image reading unit 102 image printing section 103 image memory 104 DSPa 105 DSPb 106 RAM 107 code memory 108 Line control unit 109 CPU

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 1/41-1/419 G06F 17/00-17/18

Claims (7)

(57) [Claims] 1. A first storage means for storing image data,
Second storage means for storing code data and the image data stored in said first storage means and <br/> processed into blocks and stored into said second storage means, said second An image processing apparatus comprising processing means for decoding coded data stored in a storage means in block units and storing the decoded data in the first storage means, wherein the processing means is the block unit in the processing or decoding. In succession
One of the first and second treatments to be performed
First signal processing means for processing and other processing
Between the second signal processing means and the two signal processing means, the processing in block units is performed.
And a RAM for mediating the exchange of management object data, the two signal processing means, two signal connecting both
The line indicates the status of processing related to the access to the RAM.
The status signals shown are transmitted to each other and the two signal lines
Depending on whether the status signal of the
From the block unit data write operation or from the RAM
An image processing apparatus , comprising: determining whether or not to perform the data read operation in the block unit . 2. Each block is piped by said processing means.
Line processing, the first signal processing means is
Access each time the first process for the
The status signal indicating the state is inverted and the second signal
The signal processing means completes the second processing for one block.
Status signal indicating the access status of each
2. The image processing apparatus according to claim 1, wherein the operation of inverting is repeated . 3. The processing means pipes each block.
Line processing, the second signal processing means is
Access each time the first process for the
The status signal indicating the state is inverted and the first signal is transmitted.
The signal processing means completes the second processing for one block.
Status signal indicating the access status of each
2. The image processing apparatus according to claim 1, wherein the operation of inverting is repeated . 4. The first processing is one-dimensional in a first direction.
DCT processing, the second processing is the first direction
3. The image processing apparatus according to claim 2, wherein the image processing apparatus is a one-dimensional DCT process in a second direction orthogonal to the . 5. The first processing is one-dimensional in the first direction.
Inverse DCT processing, the second processing is the first
The image processing apparatus according to claim 3, wherein the image processing apparatus is one-dimensional inverse DCT processing in a second direction orthogonal to the direction . 6. The first signal processing means performs margin processing, color space conversion , subsampling processing, and one-dimensional DCT processing in the first direction on the image data read from the first storage means. And write the result to the RAM
Seen, the second signal processing means, one-dimensional DCT processing in the second direction read out the data from the RAM, and facilities quantization, zigzag scanning and Huffman coding, the
5. The image processing apparatus according to claim 4 , wherein the result is written in the second storage unit . 7. The second signal processing means includes Huffman decoding, zigzag scan restoration , dequantization, and one-dimensional inverse DCT processing in the first direction on the code data read from the second storage means. And write the result to the RAM.
Inclusive can, said second signal processing means, the output data read from said RAM, said second inverse DCT processing of the one-dimensional direction, the sub-sampling process, and facilities the color space conversion and blank treatment,
6. The image processing apparatus according to claim 5 , wherein the result is written in the first storage unit .