JPH0946702A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor capable of eliminating the overhead of the time for loading a program in a general purpose type processor, coping with continuously inputted data streams and performing a processing at a high speed. SOLUTION: In a decoding device for processing the data streams of picture data or the like taking a hierarchial structure, plural sub statement parts 20a-20f are provided corresponding to respective layers and wired logic circuits 21 constituted corresponding to the processing procedure of the data of the respectively corresponding layers are provided. Since the wired logic circuits 21 of the sub statement parts 20a-20f can be specified so as to process the data groups of the corresponding layers, they can be simplified and this processor utilizing the merits of the wired logic circuit that are no overhead is present and a processing speed is fast is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing apparatus suitable for high-speed processing of a data stream including a plurality of types of data such as compression-coded image data having different processing procedures.

[0002]

2. Description of the Related Art A general-purpose high-speed processor (CPU) 1 as shown in FIG. 3 is used as a method for processing a bit stream (data stream) such as image information continuously input from a recording medium or a communication terminal. There is one used. In this method, the program stored in the ROM 2 is stored in the CPU
1 to process the data stream input to the buffer 7 via the input / output unit 6. Then, the data is output from the buffer 8 via the input / output unit 9. If the processing procedure differs depending on the data, R for each type of data
The corresponding program is loaded from the OM2 to the CPU1 and processed. Therefore, although this method is versatile and it is easy to change the processing procedure, etc., the time (overhead) spent for system control is increased because the fetch operation increases due to alternating program loading and data input / output. Is big. When decoding a data stream composed of image data compressed and sent by encoding, the time that can be spent for processing the data stream is limited. Therefore, when the overhead becomes large, problems occur in terms of processing speed and the amount of information that can be processed.

In the method using the microprogram shown in FIG. 4, a microinstruction is stored in advance in the microprogram memory 5, and when the address designated by the control logic 3 is set in the program counter 4, a designation is made. A group of micro-instructions are sequentially executed from the specified address. The processing device using such a microprogram system is versatile because the processing procedure can be changed by changing the contents of the microprogram memory 5, and since the time for loading the program is unnecessary, the overhead due to the fetch operation is small. . However, the microprogram memory 5 requires a certain amount of memory for each operation regardless of its contents, so that the area of the memory on the chip becomes large. Also, since a group of micro-instructions are executed in sequence from the specified address, it is necessary to incorporate all the expected processing in these micro-instructions.
In this respect as well, the area of the microprogram memory is increased and the chip size is also increased.

On the other hand, a wired logic circuit, that is, a processing device in which a logic circuit is composed of electronic circuit elements, is high in speed because it is composed of electronic circuit elements (gate elements), and has no overhead. The processing speed is faster than the method using the program. However, if the logic becomes complicated, the critical path becomes long and the operating frequency is limited. In addition, if error processing etc. are included, the number of wiring and gate elements accompanying branching will be very large, which will complicate the circuit and reduce the operating speed.
Further, there is a problem that the chip size also becomes large. In addition, since the circuit cannot be changed, it is not versatile, and if a change occurs in the processing procedure, the device itself will be remade. For this reason, the wired logic circuit is not used in a processing device unless a simple processing procedure is sufficient.

[0005]

The processing time is limited, such as the processing for decoding compressed image information,
Considering the processing in which high speed is important, a processing device using a wired logic circuit having no overhead and a high processing speed is suitable. However, if a circuit that processes different types of data such as decoding by complicated logic is configured by wired logic, the critical path becomes longer, and if exceptional processing such as error processing is added, the circuit becomes complicated. It is impossible to realize such a processing device by using a conventional wired logic circuit because it is too complicated.

In view of this, in the present invention, attention is paid to the structure of the data stream to be processed, and by combining several wired logic circuits, it is possible to prevent each wired logic circuit from becoming complicated and from extending a path. The purpose is to provide a processing device that can perform complex processing at high speed by taking advantage of the wired logic circuit. Furthermore, by separating exceptional processing such as error processing from each wired logic circuit, the processing procedure that should be realized by each wired logic circuit can be reduced, and many functions can be realized without a complicated circuit configuration. It is intended to provide a processing device. It is also an object of the present invention to provide a processing device that can be manufactured at low cost by simplifying the wired logic circuit to reduce the chip size.

[0007]

[Means for Solving the Problems] MPEG1 (Moving Pic
ture Experts Group 1) or MPEG2 (MovingPi
Most of the data streams that need to be processed continuously, such as image data according to standards such as cture Experts Group 2), are sent in sequence as a group. Further, these grouped data appearing in the data stream often have a plurality of groups sequentially repeated or have a hierarchical structure. For example, MPEG1 or M
In the PEG2 standard, a plurality of types of data groups form a layer from a layer indicating information such as an image size and an image rate, a layer indicating information on a screen basis, to a layer indicating a conversion coefficient itself. The inventor of the present application pays attention to the structure of such a data stream and the fact that a certain processing procedure can be applied to each grouped data, and is specialized for processing each grouped data. By using this wired logic circuit, we have realized a processing device that takes advantage of the high speed of the wired logic circuit without complicating the circuit.

That is, the processing device according to the present invention is a processing device for processing a data stream having grouped data, and a plurality of sub-devices having a wired logic circuit configured according to the processing procedure of these groups. It is characterized by having a statement part and a main statement part having a wired logic circuit for selecting a sub-statement part corresponding to a group appearing in a data stream. Since the processing device of the present invention is provided with the wired logic circuit corresponding to the processing procedure of the data of each group and the wired logic circuit having the function of selecting a specific sub-statement portion, it should be realized by each circuit. It is possible to provide a device capable of limiting processing and processing a data stream containing different types of data without using a complicated wired logic circuit. Therefore, the critical path of each wired logic circuit used in the processing device of the present invention is shortened, and the processing speed of the entire processing device can be improved. As described above, with the above configuration, it is possible to realize a processing device that takes advantage of the advantage of the wired logic circuit that overhead is unnecessary and processing speed is high.

In the processing apparatus of the present invention, the wired logic circuit in the main statement portion and any of the wired logic circuits in the sub statement portion perform processing alternately to complete data processing in each wired logic circuit. It prevents the critical path from extending. Provide a pointer to advance the operation of the wired logic circuit in the sub-statement part,
The main statement part can set a value to start the operation of one of the wired logic circuits in the sub statement part, and the processing of the wired logic circuit corresponding to the data group can be advanced. Further, the value of this pointer is also referred to in the main statement portion, and when the operation of the wired logic circuit of the sub statement portion is completed by this value, the wired logic circuit of the main statement portion starts the operation.

Further, a pointer for advancing the operation of the wired logic circuit and an exceptional process for the wired logic circuit, for example, an error process, a process common to a plurality of wired logic circuits, or an operation of the wired logic circuit is temporarily performed. It is desirable to provide an exception handling unit that detects a process to be interrupted and control the pointer by this exception handling unit. When performing error processing etc. collectively in the common part, the exception processing part holds the value of the pointer to interrupt the processing of each wired logic circuit, or the pointer value suitable for the processing situation is set to each wired logic circuit. To perform appropriate processing. As a result, it is not necessary to incorporate all exceptional processing into the wired logic circuit, and the configuration of the wired logic circuit can be further simplified. Therefore, it is possible to significantly reduce the number of gate elements and wirings configuring the wired logic circuit, and it is possible to improve the operation speed, reduce the chip size, and reduce the cost. Further, there is an effect that power consumption can be reduced.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail below by taking an apparatus for decoding encoded image information as an example. FIG. 1 shows a schematic configuration of a decoding device to which the present invention is applied. In addition, FIG. 2 shows MPEG1 or MPEG2.
The data structure of the image information according to the standard is shown. According to these standards, the compression-encoded image data includes a sequence layer, a group of picture (GOP) layer 52,
The picture layer 54, the slice layer 56, the microblock (MB) layer 58, and the block layer 60 are supplied as a bitstream (data stream) having a hierarchical structure of six layers. The sequence layer is a sequence data group 51 that is a data group that defines the attributes of the screen group, such as the image size and the image rate, and the GOP layer 5.
It consists of two. The GOP layer 52 is composed of a GOP data group 53 which is a minimum unit data group of a screen group and which defines the time from the beginning of the sequence of these image groups, and a picture layer 54.
Similarly, the picture layer 54 is composed of a picture data group 55 that defines attributes common to one screen and a slice layer 56. Further, the slice layer 56 is 1
It is composed of a slice data group 57 that defines information common to small screens obtained by dividing a single screen into arbitrary lengths, and a microblock layer 58. Further, the microblock layer 58 defines M that defines information common to the pixel blocks.
It consists of B data group 59 and block layer 60,
The block layer 60 is composed of a block data group 61 composed of transform coefficients.

The decoding apparatus of this example for decoding the image data grouped in this way is composed of the main statement section 1
0 and a plurality of sub-statement portions 20a to 20f. The sub-statement sections 20a to 20f are provided corresponding to each of the six layers (layers) that make up the image data described above. Furthermore, each of the sub-statement units 20a to 20f includes a wired logic circuit 21 that processes a data group that forms a corresponding layer. For example, the sub-statement portion 20a corresponds to the sequence layer, and the wired logic circuit 21 having a function as a decoder according to the processing procedure of the sequence data group 51.
It has. Similar sub-statement part 20b is G
GOP data group 5 configured corresponding to the OP layer 52
The wired logic circuit for processing 3 is provided, and the same applies to the other sub-statement units 20c to 20f. Further, a substate state register 23 for advancing an operation in the wired logic circuit 21 is provided, and the wired logic circuit 21 is controlled by using this register 23 as a pointer. Register 23
The value of is changed according to the output of the selector 22, and the signal from the main statement section 10 and the signal instructing the next operation from the selected sub statement section 20 are input to the selector 22.

The main statement portion 10 has a decoding function of judging the corresponding layer from the data group appearing in the data stream, and sets the layer information in the current layer register 15. Further, the main statement unit 10 includes a wired logic circuit 11, and the wired logic circuit 11 is arranged according to the layer appearing in the data stream.
Sub-statement part 20a corresponding to the layer
The value at which the wired logic circuit 21 of 20f starts operation is set in the sub-state state register 23. Wired logic circuit 11 of main statement section 10
The operation of (1) proceeds using the main state status register 12 as a pointer, and the operation of this register 12 is changed by a signal instructing the next operation of the main statement portion 10.

In addition to the main statement section 10 and the sub-statement sections 20a to 20f, the decoding apparatus of this embodiment is exceptional for error processing, processing common to the sub-statement section and the main statement section, and other wired logic circuits. A processing unit 30 for detecting the occurrence of various processes and the end of such processes is provided.

The output of the register 12 for operating the wired logic circuit 11 of the main statement section 10 is supplied to the wired logic circuit 11 via the selector 13, and the selector 13 is operated by the signal from the exception processing section 30. .

That is, when the exception processing unit 30 detects an exceptional process for the wired logic circuits 11 and 21, the value of the register 12 is held by the selector 13 based on the instruction of the exception processing unit 30, and the wired logic circuit 11 is processed. The operation of does not proceed. When the exception processing unit 30 detects that the exceptional processing has ended, the selector 13 is opened, and the processing of the wired logic circuit 11 is restarted according to the value of the register 12.

In addition, the selector 13 includes an exception handling unit 30.
The value of the pointer is also supplied from the exception processing unit 30 to the wired logic circuit 11 via the selector 13 depending on the state detected by the exception processing unit 30. It is designed so that processing or processing suitable for exceptional conditions can be performed.

The same applies to the wired logic circuit 21 of the sub-statement portions 20a to 20f. The output of the sub-state register 23 is supplied to the wired logic circuit 21 via the selector 24 controlled by the exception handling section 30. Therefore, the exception handling unit 3
When 0 detects that exceptional processing is necessary or that such processing is being performed, or when it is determined that the wired logic circuit 21 should be temporarily stopped, The value of 23 is held, and the operation of the wired logic circuit 21 does not proceed. When the operation of the wired logic circuit 21 is restarted, such as when the exception processing unit 30 detects the end of exceptional processing, the value of the register 23 is supplied to the wired logic circuit 21 via the selector 24, and the next operation is performed. Done. As with the selector 13, the exception processing unit 30 can supply the pointer value to the wired logic circuit 21 via the selector 24. Therefore, it is possible to selectively perform exceptional processing using the wired logic circuit 21 or perform processing suitable for the exceptional state. Of course, the exception processing unit 30 may perform error processing or other common processing.

The output of the selector 24 is returned to the main statement section 10, and the main statement section 1
0 monitors the progress of the wired logic circuit 21 in the sub-statement section based on this output.
Therefore, the end of the process in the wired logic circuit 21 of the sub-statement part can be determined by the value of the register 23, and the process of the main statement part 10 is restarted. In the processing device of this example, the state of the sub-statement part is referenced by using a register as a pointer, and the processing subject is dynamically switched from the main statement part to the sub-statement part and from the sub-statement part to the main statement part. , Continue processing the data stream.

As described above, in the decoding apparatus of this example,
Since the circuit that processes the input data stream is realized by the plurality of wired logic circuits 21, the processing speed is very high. In addition, these wired logic circuits 21 include a plurality of sub-statement units 20.
a to 20f, these sub-statement portions 20a to 20f are data groups having different processing procedures, and in the data stream for transmitting the image information of this example, the data groups 51, 53, 5 of each layer.
5, 57, 59 and 61 are provided.
Furthermore, these sub-statement parts 20a to 20f
Is selected by the main statement part 10 based on the data group appearing in the data stream, and the main statement part 10 selects the substate state register 23.
The process proceeds using the as a pointer.

Therefore, the processing contents to be realized by the wired logic circuit 21 in each sub-statement portion can be limited to only the processing of the data included in the corresponding data group. Since the wired logic circuit 21 provided in each sub-statement section only needs to perform a limited function, it is possible to prevent the circuit from becoming complicated,
It is possible to shorten the critical path. Therefore, the advantages of the wired logic circuit such as no overhead and high processing speed can be maximized.

The function of the main statement portion 10 is also limited to selecting the sub statement portion corresponding to the data group appearing in the data stream and proceeding with the processing. Therefore, it can be realized by using a wired logic circuit, and processing can be performed at high speed.
Further, by referring to the value of the sub-state state register 23, when the processing of the sub-statement section is completed, the control of the processing device is automatically transferred to the main statement section 10 side. Therefore, replacement control is performed between the main statement part 10 and the sub-statement part 20, such that the process is transferred from the main statement part 10 to any of the sub-statement parts 20a to 20f, and then the process is transferred to the main statement part 10. . As a result, the processing content realized by the wired logic circuit 11 of the main statement section 10 and the processing content realized by the wired logic circuit 21 of the sub statement section 20 are clearly separated, and the configurations of the wired logic circuits 11 and 21 are It keeps it from becoming complicated. Further, since the main statement part 10 and the sub-statement part 20 are dynamically controlled to be replaced, there is no overhead in migration and it is possible to prevent a decrease in processing speed.

In recent years, such a wired logic circuit has been designed by a hardware description language such as HDL or VHDL, so that the time required for the development of the circuit can be greatly shortened and the circuit can be easily changed. It has become. Therefore, even a device using a wired logic circuit such as the decoding device of this example can shorten the time required for design and development, and can flexibly deal with a change in specifications. Therefore, also in terms of versatility, it is possible to sufficiently oppose a processing device using a conventional program or a microprogram, and it is possible to provide a processing device having a higher processing speed. Further, unlike the micro program memory, it is only necessary to prepare the minimum necessary elements on the circuit, so that the chip size can be reduced.

Further, in the decoding apparatus of this example, the outputs of the registers 12 and 23 for advancing the operation of the wired logic circuits 11 and 21 are supplied via the selectors 13 and 24. Then, the selectors 13 and 24 are operated by the exception processing unit 30 to control the values of the pointers supplied to the wired logic circuits 11 and 21. Therefore, when processing in the exception handling unit 30, for example, error handling is required, the main statement unit 10 and each sub-statement unit 2
The values of the registers 12 and 23 supplied to 0a to 20f are held and the wired logic circuit 1 of each is held.
The error handling can be performed by interrupting the operations in 1 and 21. Similarly, the wired logic circuits 11 and 21
It is also possible to cause the processing appropriate for error processing to be performed. When the error processing is completed, the values of the registers 12 and 23 are supplied to the wired logic circuits 11 and 21 via the selectors 13 and 24, so that the continuous processing can be performed in the respective wired logic circuits.

In the conventional wired logic circuit, since exceptional processing such as error processing is also judged and processed at each stage of operation, the logic becomes complicated and many gate elements and long wiring are required. As a result, the throughput is reduced and the area occupied by the circuit is increased, resulting in a large chip size and a high price.

On the other hand, in the decoding device of this example,
Exceptional processing such as error processing can be separated from individual wired logic circuits for common use, or a predetermined operation can be performed by the wired logic circuits under the control of the exception processing unit. Therefore, the configuration of the wired logic circuit can be simplified, and the circuit can be configured with a small number of gate elements and short wiring. Furthermore, because it is not necessary to consider exceptional processing in each operation step of each wired logic circuit, it is possible to adopt the optimum circuit configuration corresponding to the data group to be processed and reduce the time spent for development and design. be able to. As a result, the area occupied by the wired logic circuit can be significantly reduced, and the size and cost of the processing device equipped with a decoding device such as an LSI can be reduced. Furthermore, since the number of gate elements is reduced and the circuit is shortened, it is effective not only in improving processing speed but also in reducing power consumption.

In this example, MPEG1 and M
Although the apparatus for decoding the compression-encoded data based on the structure of the image data standardized by PEG2 has been described as an example, the present invention is not limited to this. JPEG (Joint Photog
raphic Coding Experts Group) or H.P. 261 (I
The structure of image data in a standard such as TU-T Recommendation No. 261) also has almost the same hierarchical structure, and it is not possible to realize a processing device similar to the above by providing sub-statement parts corresponding to these data groups. Of course it is possible. Furthermore, standardization for encoding audio signals using a similar data structure is also in progress.

[0028]

As described above, the processing device of the present invention is provided with a plurality of sub-statement portions, and each sub-statement portion is provided with the wired logic circuit configured according to the processing procedure of the data group. . Then, the sub-statement portion corresponding to the data group appearing in the data stream is selected by the main statement portion and processed. Thus, each wired logic circuit is a simpler circuit dedicated to processing the corresponding data group.

Therefore, the overhead is eliminated, and
Since the device can be miniaturized, a complicated processing device that handles a plurality of types of data can be configured by taking advantage of the wired logic circuit, and a device with a high processing speed can be provided.

Further, a portion for performing exceptional processing such as error processing can be shared, and when exceptional processing is required, the operation of the wired logic circuit can be held. As a result, many gate elements and wirings required in the conventional wired logic circuit for performing exceptional processing can be omitted, and the wired logic circuit can be simplified. As a result, it is possible to provide a processing apparatus which has a higher processing speed, a reduced chip size, and can be manufactured at low cost.

As described above, the processing apparatus of the present invention is capable of processing a data stream of data grouped according to a predetermined standard at high speed, and compresses and encodes image information such as a video signal in real time or the compression code. It is suitable for a processing device that decodes image data that has been sent after being converted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a decoding device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of image data according to the MPEG standard.

FIG. 3 is a block diagram showing a schematic configuration of a processing device using a conventional programmable processor.

FIG. 4 is a block diagram showing a schematic configuration of a processing device using a conventional microprogram.

[Explanation of symbols]

1 ... CPU 2 ... ROM as program storage medium 3 ... Control logic 4 ... Program counter 5 ... Micro program memory 6, 9 ... Input / output unit 7, 8 ... Buffer 10 ... Main statement part 11 ... Wired logic circuit of main statement part 12 ... Main state status register 13, 22, 24 ... Selector 15 ... Current layer register 20 ... Sub statement part 21 ... Wired logic circuit of sub statement part 23 ... Substate status register

Claims (5)

[Claims] 1. A processing device for processing a data stream comprising a plurality of grouped data, comprising: a plurality of sub-statement units comprising a wired logic circuit configured according to a processing procedure of the group; And a main statement unit including a wired logic circuit that selects one of the sub-statement units corresponding to the group appearing in the stream. 2. The processing device according to claim 1, wherein the wired logic circuit in the main statement portion and any of the wired logic circuits in the sub statement portion perform processing alternately. 3. The pointer according to claim 1, further comprising a pointer for advancing an operation of the wired logic circuit of the sub-statement unit, the pointer starting an operation of any of the wired logic circuits of the sub-station unit by the main statement unit. The main statement part refers to the value of this pointer, and when the operation in the wired logic circuit of the sub statement part is completed, the operation in the wired logic circuit of the main statement part is started. Characterizing processing device. 4. The pointer according to claim 1, further comprising a pointer for advancing the operation of the wired logic circuit, and an exception processing unit for detecting an exceptional process for the wired logic circuit. A processing device having a controllable value. 5. The processing apparatus according to claim 1, wherein the data stream is image data according to MPEG1 or MPEG2, and the groups have a hierarchical structure.