JP2000037870A - Recording head and recording apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a current-driving efficiency of a power transistor. SOLUTION: When an image signal 620 is H, a first switch 615 is connected to a (b) terminal, a second switch 617 to a (c) terminal and a third switch 619 to a (d) terminal, whereby a capacitor 114 is charged. When the image signal 620 becomes L, the first switch 615 is connected to an (a) terminal (a source line 620), the second switch 617 is connected to the (d) terminal and the third switch 619 is opened, whereby charges stored in the capacitor 114 are divided to the capacitor 114 and a power transistor 502. A higher voltage than a voltage of the source line 620 is supplied to a gate of the power transistor 502.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording head and a recording apparatus, and more particularly, to a recording head for recording an image on a recording medium by controlling ink ejection based on an image signal, and a recording apparatus having the recording head. About.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a circuit configuration of a recording head mounted on a conventional ink jet recording apparatus. The electrothermal transducer (heater) of this type of recording head and its driving circuit can be formed on the same substrate by using a semiconductor process technology, as shown in, for example, Japanese Patent Application Laid-Open No. 5-185594.

In FIG. 8, reference numeral 401 denotes an electrothermal transducer (heater) for generating thermal energy; 402, a power transistor section for supplying a desired current to the heater 401; The shift register temporarily stores image data for controlling whether or not to eject ink from the nozzles of the print head, 407 denotes an input terminal of a transfer clock (CLK) provided in the shift register 404, and 406 denotes a heater. 401
403 is a latch circuit for latching image data corresponding to each heater, and 408 is a timing signal for latch operation to each latch circuit 403. L
T) is a latch signal input terminal for inputting T), 409 is a switch for controlling the timing of supplying a current to the heater 401, 405 is a power supply line for applying a predetermined voltage to the heater 401 and supplying a current, and 410 is a heater G into which the current flowing through the power transistor 401 and the power transistor 402 flows
ND line.

The number of bits of image data stored in the shift register 404, the number of power transistors 402, and the number of heaters 401 are the same. FIG. 9 is a diagram showing a signal waveform in the recording head shown in FIG. The transfer clock (CLK) for the number of bits of the image data stored in the shift register 404 is input to the transfer clock input terminal 407, and the image data is transferred by the transfer clock (CLK).
Is input and shifted at the rising edge of.

Image data (DATA) for controlling ON / OFF of each heater 401 is supplied to an image data input terminal 406.
Is entered from As described above, the shift register 404
And the number of heaters 401 and the number of current driving power transistors 402 are the same, so that the same number of transfer clocks (C
LK), and the image data (DATA) is shifted in the shift register 404. Then, the latch signal (LT) is supplied to the latch signal input terminal 408 to supply each heater 4
01 is latched in each latch circuit 403.

Thereafter, a heat signal (HEAT) for controlling the switch 409 is input to the heat signal input terminal 411. In this recording head, a heat signal (HEA
When T) is H, the switch 409 is turned ON. Set the heat signal (HEAT) 411 to H to turn on the switch 409
In the state, the power transistor 402 and the heater 4
01 to the power supply line 405 to the GND line 410
Current flows through As a result, the heater 401 generates heat necessary for discharging ink, and the ink is discharged from the corresponding nozzle.

FIG. 10 shows a recording head obtained by improving the recording head shown in FIG. In FIG. 10, reference numeral 502 denotes a power transistor for supplying a desired current to the heater. The printhead shown in FIG. 8 employs a Darlington-connected NPN transistor as a power transistor, whereas the printhead shown in FIG. 10 employs an nMOS transistor as a power transistor.

Generally, it is preferable to use a CMOS gate for a logic circuit such as a shift register or a latch. Therefore, if an NPN transistor is used as a power transistor, it is necessary to manufacture a recording head by a Bi-CMOS process. However, the Bi-CMOS process has
For example, there is a disadvantage that a large number of masks are required and the manufacturing cost is high. Therefore, in the recording head shown in FIG. 10, by employing an nMOS transistor instead of an NPN transistor, it is possible to produce the recording head by a CMOS process, thereby reducing the production cost.

The problem with the adoption of the CMOS process is that the current driving capability of the MOS transistor is inferior to that of the bipolar transistor. Therefore, in the recording head shown in FIG. 10, in order to increase the current driving capability of the nMOS power transistor 502, the voltage conversion unit 111 supplies a voltage higher than the power supply voltage to the gate of the power transistor 502. Is provided.

[0010]

However, FIG.
In the voltage conversion unit 111 shown in FIG. 19, the threshold value of the inverter including the resistor 531 and the nMOS transistor 532 is
1 and the ON resistance value of the nMOS transistor 532. Therefore, the threshold value is generally equal to the CMO used in the latch circuit 403 and the shift register 404.
There is a problem that it is lower than the S inverter and is weak against noise. In particular, in an ink jet printer, a large heater current needs to be supplied to the heater 401 in order to reliably discharge ink, and a large GND line noise is easily generated by the heater current flowing to the GND 410. Therefore, a circuit configuration that is resistant to noise is required.

In the voltage converter 111 shown in FIG. 10, when the output of the latch circuit 403 is H and the switch 409 is turned on in the inverter including the resistor 531 and the nMOS 532, the resistor 531 and the nMOS transistor 532 are connected. From power supply line 120 to GND
Current continues to flow through line 410. This current increases as the number of latch circuits 403 whose output is H increases.

In order to speed up the printing process and improve the image quality, it is desired to increase the number of bits for simultaneously ejecting ink, in addition to increasing the pitch of the heater and increasing the number of nozzles. Increasing the number of bits for simultaneously ejecting ink means increasing the number of latch circuits 403 that output H, that is, increasing the current flowing from the power supply line 120 to the GND line 410 of the voltage converter 111. means. When this current increases, the voltage drop due to the wiring resistance of the power supply line 120 increases. Therefore, when a large number of power transistors 502 are turned on at the same time, the voltage applied to the gates of the power transistors 502 decreases.

As described above, in the recording head shown in FIG. 10, since the voltage applied to the gate of the power transistor 502 depends on the number of bits for simultaneously ejecting ink, the power transistor 502 can be driven stably. Have difficulty. In the recording head shown in FIG. 10, the voltage of the power supply line 120 of the voltage conversion circuit 111 is increased in order to increase the current driving capability of the power transistor 502.
It is preferable to increase the voltage within a range not exceeding the breakdown voltage of the CMOS inverter including the pMOS transistor 533 and the nMOS transistor 534 and the gate breakdown voltage of the power transistor 502. Generally, the heater voltage is often set to a high voltage of 20 V or more.
However, the breakdown voltage of the CMOS inverter is 1
In many cases, the voltage is about 5 V, and in consideration of the durability of the gate insulating film of the power transistor 502, it is not preferable to increase the gate voltage of the power transistor 502 without limit.

In general, a gate voltage of a MOS is set to a predetermined value.
When the voltage is increased, the carrier mobility saturates and the electric field increases.
Even if it does, the current driving capability will not change dramatically. Characteristic
In general, to stabilize the
Pressure is applied to the gate. For example, if the resistance of the p-type substrate is 15
Ωcm, gate oxide thickness tox is 0.5 μm, channel
Length L is 3 μm, source / drain of nMOS transistor
Dose of 3 × 10 ^Fifteencm^-2, NMOS transistor
The dose of the drain electric field relaxation layer is 3 × 10¹²cm^-2of
In the case of the process, when the gate voltage is about 7V, the nMOS
The current drive capability of the transistor starts to saturate. This professional
If the margin is taken into account when adopting the
Apply gate voltage in the range of 2V to nMOS transistor
Is preferred.

After all, the power supply line 1 of the voltage conversion circuit 111
It is difficult to make the optimum voltage of the power supply 20 equal to the voltage of the power supply line 405 for the heater, and therefore, the power supply line 120 for voltage conversion, the heater power supply 405, the latch circuit 403, the shift register 404, etc. Power line. However, the provision of three power supplies complicates the system and increases the cost.

SUMMARY OF THE INVENTION It is an object of the present invention to increase the current driving capability for driving an ink ejection unit.

[0017]

SUMMARY OF THE INVENTION A recording head according to the present invention is a recording head that controls the ejection of ink based on an image signal to record an image on a recording medium, and a driving unit that drives an ink ejection unit. And a drive signal generation unit that generates a drive signal for controlling the drive unit based on the image signal, wherein the drive signal generation unit has a capacitor, and uses the capacitor to reduce a power supply voltage. And generating the drive signal having a high voltage.

In the above recording head, the capacitor has a first terminal and a second terminal, and the drive signal generating section includes:
For example, a charging circuit that applies a voltage between the first terminal and the second terminal to charge the capacitor,
An application circuit for setting a terminal to a predetermined potential and electrically connecting the second terminal to an input terminal of the driving unit to apply a drive signal to the input terminal is further provided.

In the recording head, for example, the charging circuit preferably includes a diode having an anode connected to a power supply and a cathode connected to a second terminal of the capacitor. In the above recording head, for example, the charging circuit grounds a first terminal of the capacitor when the image signal is at a first logical level, and supplies a power to the first terminal when the image signal is at a second logical level. A first switch circuit connected to the power supply, wherein the application circuit connects a second terminal of the capacitor to a power supply when the image signal is at the first logic level, and connects the power supply when the image signal is at the second logic level. Preferably, a second terminal is electrically connected to an input terminal of the driving section.

In the above recording head, for example, it is preferable that the drive signal generating circuit further includes a delay unit for delaying the image signal, and the first switch is controlled by an output of the delay unit. In the recording head, for example, it is preferable that the charging circuit includes a transistor between a power supply line and a second terminal of the capacitor, and the transistor is controlled based on a logical level of the image signal. .

In the recording head, for example, the charging circuit connects the first terminal of the capacitor to a ground when the image signal is at the first logical level, and connects the second terminal of the capacitor to a power supply. When the image signal is at the second logic level, the first terminal is connected to a power supply and the second terminal is electrically disconnected from the power supply. Preferably, a second terminal is grounded, and the second terminal is electrically connected to an input terminal of the driving unit when the image signal is at the second logic level.

In the above-mentioned recording head, for example, it is preferable that the driving section includes a transistor controlled by the driving signal. In the above-described recording head, for example, it is preferable that the transistor of the driving unit is a MOS transistor. In the above recording head,
For example, the capacitance of the capacitor is preferably larger than the gate capacitance of the MOS transistor.

In the above recording head, for example, the dielectric constituting the capacitor and the gate insulating film of the MOS transistor are made of the same material, and the thickness of the dielectric is larger than the thickness of the gate insulating film. Preferably, it is thin. In the above-mentioned recording head, for example, it is preferable that the dielectric constant of the dielectric constituting the capacitor is higher than the dielectric constant of the gate insulating film of the MOS transistor.

In the above-mentioned recording head, for example, it is preferable that the delay unit is formed of a CMOS circuit. In the above recording head, for example, it is preferable that the delay unit includes an RC integrating circuit. In the above recording head,
For example, the drive unit and the drive signal generation unit are CMOS
It is preferably manufactured in a process.

In the above recording head, for example, a plurality of sets of the driving section and the driving signal generating section are provided, and further, a shift register for converting an image signal supplied in series to a parallel image signal, A plurality of latch circuits each latching each image signal output from the, a transmission circuit that transmits the output of the plurality of latch circuits to the corresponding drive signal generation unit according to a control signal, the drive unit, It is preferable that the drive signal generator, the shift register, the latch circuit, and the transmission circuit are driven by the same power supply.

In the above-mentioned recording head, it is preferable that the ink discharge section includes, for example, a nozzle and a heater for heating ink filled in the nozzle. A recording apparatus according to the present invention includes any one of the recording heads described above.

[0027]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. <Schematic Description of Apparatus Main Body> FIG. 5 is an external perspective view showing an outline of a configuration of an ink jet printer (IJRA) which is a typical embodiment of the present invention. In FIG. 5, the driving force generated by the driving motor 5013 is
It is transmitted to the lead screw 5005 via 009-5011. The carriage HC has a lead screw 50
05 has a pin engaged with the spiral groove 5004, and reciprocates in the directions of arrows a and b while being supported by the guide rail 5003. On the carriage HC, an integrated type ink jet cartridge IJC containing a recording head IJH and an ink tank IT is mounted.

Reference numeral 5002 denotes a paper holding plate, which is a carriage H
The recording paper P is pressed against the platen 5000 over the moving direction of C. Reference numerals 5007 and 5008 denote photocouplers, which are home position detectors for confirming the presence of the carriage lever 5006 in this region and switching the rotation direction of the motor 5013. Reference numeral 5016 denotes a cap member 5022 for capping the front surface of the recording head IJH.
Reference numeral 5015 denotes a suction device that suctions the inside of the cap, and performs suction recovery of the recording head through the opening 5023 in the cap. Reference numeral 5017 denotes a cleaning blade. Reference numeral 5019 denotes a member which allows the blade to move in the front-rear direction. These members are supported by a main body support plate 5018. It goes without saying that the blade is not limited to this form and a known cleaning blade can be applied to this example.

Reference numeral 5021 denotes a lever for starting suction for suction recovery, and a cam 5020 which engages with the carriage.
The driving force from the driving motor is controlled by a known transmission mechanism such as clutch switching. The capping, cleaning, and suction recovery are configured so that desired operations can be performed at the corresponding positions by the action of the lead screw 5005 when the carriage comes to the area on the home position side. If the above operation is performed, any of the examples can be applied.

<Description of Control Structure> Next, a control structure for executing the recording control of the above-described apparatus will be described.
FIG. 6 is a block diagram showing a configuration of a control circuit of the inkjet printer IJRA. In the figure showing a control circuit, 1700 is an interface for inputting a recording signal, 1
Reference numeral 701 denotes an MPU, 1702 a ROM for storing a control program executed by the MPU 1701, and 1703 a DRAM for storing various data (such as the above-described recording signals and recording data supplied to the head). Reference numeral 1704 denotes a gate array that controls supply of print data to the print head 1708, and includes an interface 1700, an MPU 17
01, and also controls data transfer between the RAM 1703.

Reference numeral 1710 denotes a carrier motor for transporting the recording head 1708, and reference numeral 1709 denotes a transport motor for transporting the recording paper. Reference numeral 1705 denotes a head driver for driving the recording head, and reference numerals 1706 and 1707 denote motor drivers for driving the transport motor 1709 and the carrier motor 1710, respectively. The operation of the above-described control configuration will be described. When a print signal enters the interface 1700, the print signal is converted into print print data between the gate array 1704 and the MPU 1701. Then, the motor drivers 1706 and 1707 are driven, and the printhead is driven according to the print data sent to the head driver 1705 to perform printing.

As described above, the ink tank IT and the recording head IJH may be integrally formed to constitute a replaceable ink cartridge IJC. However, the ink tank IT and the recording head IJH are separated. It may be configured so that only the ink tank IT can be replaced when the ink runs out. FIG. 7 is an external perspective view showing a configuration of an ink cartridge IJC in which an ink tank and a head can be separated. Ink cartridge IJC
As shown in FIG. 7, the ink tank IT and the recording head IJH can be separated at the position of the boundary line K. When the ink cartridge IJC is mounted on the carriage HC, the ink cartridge IJC is provided with an electrode (not shown) for receiving an electric signal supplied from the carriage HC side. Is driven to eject ink.

In FIG. 7, reference numeral 500 denotes an ink ejection port array. The ink tank IT is provided with a fibrous or porous ink absorber for holding ink, and the ink is held by the ink absorber. In the above embodiment, the description has been made assuming that the liquid droplets ejected from the recording head are ink, and the liquid contained in the ink tank is ink, but the contained matter is limited to ink. Not something. For example, to improve the fixability and water resistance of the recorded image,
A liquid such as a processing liquid discharged to a recording medium to improve the image quality may be stored in the ink tank.

The above-described embodiment is particularly provided with a means (for example, an electrothermal converter or a laser beam) for generating thermal energy as energy used for performing ink ejection even in an ink jet recording system. By using a method in which a change in the state of the ink is caused by energy, it is possible to achieve higher density and higher definition of recording. For a representative configuration and principle, see, for example, US Pat.
It is preferable to use the basic principle disclosed in 723129 and 4740796.

This method can be applied to both on-demand type and continuous type.
In the case of the on-demand type, a rapid temperature rise exceeding the film boiling corresponding to the recorded information is performed on the electrothermal transducer disposed corresponding to the sheet or liquid path holding the liquid (ink). By applying at least one drive signal to the recording medium, heat energy is generated in the electrothermal transducer, causing film boiling on the heat-acting surface of the recording head. As a result, the drive signal corresponds one-to-one. This is effective because air bubbles in the formed liquid (ink) can be formed. The growth of this bubble,
The liquid (ink) is ejected through the ejection opening by the contraction to form at least one droplet. When the drive signal is formed into a pulse shape, the growth and shrinkage of the bubble are performed immediately and appropriately, so that the ejection of the liquid (ink) having particularly excellent responsiveness can be achieved, which is more preferable.

As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. Further, if the conditions described in US Pat. No. 4,313,124 relating to the temperature rise rate of the heat acting surface are adopted, more excellent recording can be performed. As a configuration of the recording head, in addition to the combination of the ejection port, the liquid path, and the electrothermal converter (a linear liquid flow path or a right-angled liquid flow path) as disclosed in the above-mentioned respective specifications, a heat acting surface A configuration using U.S. Pat. No. 4,558,333 and U.S. Pat. No. 4,459,600, which disclose a configuration in which a is bent, is also included in the present invention. In addition, Japanese Patent Laid-Open Publication No. Sho 5 discloses a configuration in which a common slot is used as a discharge portion of an electrothermal converter for a plurality of electrothermal converters.
Japanese Unexamined Patent Publication No. 9-123670 discloses a structure in which an opening for absorbing a pressure wave of thermal energy corresponds to a discharge portion.
A configuration based on JP-A-9-138461 may be adopted.

Further, as a full-line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, the length is determined by combining a plurality of recording heads as disclosed in the above-mentioned specification. This may be either a configuration satisfying the above requirements or a configuration as a single recording head formed integrally. In addition, not only the recording head of the cartridge type in which the ink tank is provided integrally with the recording head itself described in the above-described embodiment, but also the electrical connection with the main body of the apparatus by being attached to the main body of the apparatus. A replaceable chip-type recording head that can supply ink from the apparatus body may be used.

Further, it is preferable to add recovery means for the printhead, preliminary auxiliary means, and the like to the configuration of the printing apparatus described above, since the printing operation can be further stabilized. Specific examples thereof include capping means for the recording head, cleaning means, pressurizing or suction means, preheating means using an electrothermal transducer or another heating element or a combination thereof. It is also effective to provide a preliminary ejection mode for performing ejection that is different from printing, in order to perform stable printing.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, and may be a single recording head or a combination of plural recording heads. Alternatively, the apparatus may be provided with at least one of full colors by color mixture. In the embodiment described above, the description has been made on the assumption that the ink is a liquid.However, even if the ink is solidified at room temperature or below, it may be one that softens or liquefies at room temperature. Alternatively, in the ink jet system, the temperature of the ink itself is generally controlled within a range of 30 ° C. or more and 70 ° C. or less to control the temperature so that the viscosity of the ink is in a stable ejection range. It is sufficient if the ink is sometimes in a liquid state.

In addition, in order to positively prevent the temperature rise due to thermal energy as energy for changing the state of the ink from the solid state to the liquid state,
Alternatively, in order to prevent evaporation of the ink, an ink which solidifies in a standing state and liquefies by heating may be used. In any case, the application of heat energy causes the ink to be liquefied by application of the heat energy according to the recording signal and the liquid ink to be ejected, or to start to solidify when reaching the recording medium. The present invention is also applicable to a case where an ink having a property of liquefying for the first time is used. In such a case, as described in JP-A-54-56847 or JP-A-60-71260, the ink is held in a liquid state or a solid state in the concave portion or through hole of the porous sheet. It is good also as a form which opposes an electrothermal transducer. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

In addition to the above, the recording apparatus according to the present invention may be provided not only as an image output terminal of an information processing apparatus such as a computer but also integrally or separately, a copying apparatus combined with a reader or the like, and a transmission / reception apparatus. It may take the form of a facsimile machine having functions. <Circuit Configuration of Print Head IJH> The circuit configuration of the print head IJH of the above printing apparatus will be described below.

FIG. 1 shows a recording head IJ.
FIG. 3 is a diagram illustrating a first configuration example of H. 1 includes a shift register 404 and a plurality of latch circuits 4.
03, a plurality of switches 409, a plurality of voltage conversion units (drive signal generation units) 111, a plurality of MOS power transistors (drive units) 502, and a plurality of resistors (heaters) 401. Latch circuit 403, switch 40
9, voltage converter 111, MOS power transistor 50
Each number of 2 and the resistance 401 is the same as the number of nozzles.

Each of the voltage converters 111 includes a first switch 61
5, a second switch 617, a third switch 619,
And a drive signal 630 having a voltage higher than the voltage supplied from the power supply line 120, which is controlled by an input signal, that is, an image signal 620 supplied from the latch circuit 403 via the switch 409. .
The potential of the power supply line 120 is, for example,
And the potential of a power supply line of a circuit such as the shift register 404 or the like.

First, second and third switches 615, 61
7 and 619 are both controlled by the image signal 620. Specifically, when the image signal 620 is H, the first switch 615 is connected to the terminal b, the second switch 617 is connected to the terminal c, and the third switch 619 is connected to the terminal d. On the other hand, when the image signal 620 is L, the first switch 615 is connected to the terminal a, and the second switch 617 is connected to the terminal d.
Connected to the terminal, and the third switch 619 is opened.

In the following, description is made on the assumption that the potential of the power supply line 120 is 5 [V]. First, a case where the image signal 620 is H (ink ejection: OFF) will be described. In this case, since the first switch is connected to the terminal b, the potential at the point A of the capacitor 114 becomes 0V. Further, since the second switch 617 is connected to the terminal c, the capacitor 114 is charged by the charging current supplied from the power supply line 120. Here, the charging time is t,
Assuming that the charging current flowing through the second switch 617 is I, the charge Q stored in the capacitor 114 is Q = It. Also, assuming that the capacitance of the capacitor 114 is C,
The potential Vc of the terminal B of the capacitor 114 is as follows: Vc = Q / C = 1 / C · It For example, the capacitance C of the capacitor 114 is set to 100
Assuming that [pF], the output impedance of the power supply 120 and the combined impedance R of the wiring and the like are 100 [Ω], the potential Vc when the time t has elapsed from the start of charging is as follows: Vc = (1−e ^{−t / RC} ) 5 = (1−exp (−t / (10 × 10 ⁻⁹ ))) · 5

For example, in the thermal ink jet printer, after the heat signal (control signal) 411 becomes active (switch 409: ON), the ink is ejected from the nozzle, and then the ink is filled and the ink can be ejected again. Is dominant by the viscosity of the ink and the fluid resistance of the nozzle wall, and is usually about several tens [μs]. Here, for example, if the charging time t is 10 [μs], the capacitor 114 is charged to Vc = 4.995 [V] according to the above equation. This potential Vc can be regarded as a potential at which charging is almost completed. That is, it can be seen that the refilling time of the ink is sufficiently longer than the charging time of the capacitor 114. In the following, for simplicity of description, it is assumed that the capacitor 114 is charged up to 5 [V].

When the output of the latch circuit 403, that is, the image signal 620 is H (ink ejection: OFF),
Since the third switch 619 is connected to the d terminal and 0 [V] is supplied to the gate of the MOS power transistor 502, the MOS power transistor 502 is turned off and no current flows to the heater 401. Therefore, in this case, no ink is ejected.

Next, a case where the output of the latch circuit 403 is L (ink ejection: ON) will be described. In this case, the first switch 615 is connected to the terminal a, the second switch 617 is connected to the d terminal, and the third switch 619 is opened. The potential on the A terminal side of the capacitor 114 becomes 5 [V] which is the same voltage as the power supply 120. here,
For the sake of explanation, considering the case where the B terminal side of the capacitor 114 is open, that is, the case where the second switch 617 is open, the potential Vb at the B terminal side of the capacitor 114 is Vb = (potential at the A terminal side) + Vc = 5 + 5 = 10 [V] instantaneously.

However, actually, since the second switch 617 is connected to the d terminal, the B terminal of the capacitor 114 and the gate potential Vg of the MOS power transistor 502 are connected.
Are equal. That is, the charge Q stored in the capacitor 114 is divided according to the ratio of the capacitance C of the capacitor 114 and the gate capacitance Cg of the MOS power transistor 502. The gate potential Vg at this time is as follows: Vg = C / (C + Cg) × (5 + Vc) Here, if C >> Cg, then Vg = 5 + Vc ≒ 10 [V]. That is, if the capacitance C of the capacitor 114 is sufficiently larger than the gate capacitance Cg of the MOS power transistor 502, a voltage that is approximately twice the voltage of the power supply line 120 is supplied to the gate of the MOS power transistor 502.

When the output of the latch circuit 403 is L,
Capacitor 114 and MOS power transistor 502
The voltage Vg is held until the output data of the latch circuit 403 becomes H because there is no path for extracting the electric charge accumulated in the gate of. That is, when the output of the latch circuit 403 is L (ink ejection: ON), the voltage Vg boosted by the charge accumulated in the capacitor 114 is applied to the gate of the MOS power transistor 502,
As a result, the MOS power transistor 502 is turned on, a current flows to the corresponding heater 401, and ink discharge, that is, printing is performed.

This voltage Vg is equal to the power supply voltage supplied to the shift register 404, the latch circuit 403, and the like.
[V] is boosted.
Since a high voltage is supplied to the gate of the power transistor 502, the current driving capability is increased. Here, the capacitance C of the capacitor 114 with respect to the gate capacitance Cg
Is arbitrarily set, an arbitrary voltage higher than the voltage of the power supply line 120 can be obtained as the voltage Vg. This voltage Vg is, for example, the breakdown voltage of the elements constituting the second and third switches 617 and 619, the gate oxide film of the MOS power transistor 501,
It is desirable to set the voltage as high as possible within the range permitted by the dielectric strength of the capacitor 114.

By the way, usually, the capacitor of the heater board formed on the silicon substrate preferably has, for example, an MIS capacitor structure.
When the gate insulating film of No. 02 and the dielectric of the capacitor 114 are the same, it is necessary to make the capacitor area larger than the gate area in order to satisfy C >> Cg as described above. In order to reduce the chip size, it is necessary to increase the capacity per unit area. As a method,
For example, a method in which an insulating film thinner than the gate insulating film of the power transistor 502 is used as the dielectric of the capacitor 114, and a method in which a film having a higher dielectric constant than the gate insulating film of the power transistor 502 is used as the dielectric of the capacitor 114 Etc.

Further, according to this configuration example, by setting the threshold values of the first, second and third switches 615, 617 and 619 near the center of the amplitude of the image signal 620,
A noise margin can be secured. FIG.
In the conventional example shown in FIG. 1, when the heater 401 is driven, a steady current flows from the power supply line 120 to the GND line 410 via the resistor 531 and the nMOS transistor 532. By configuring the conversion unit 111 with a CMOS transistor, a structure in which only a transient through current flows through the voltage conversion unit 111 can be provided. In this case, current consumption can be reduced.

According to this configuration example, the latch circuit 4
03 and the shift register circuit 404 and the power supply 120 of the voltage conversion unit 111.
In this case, desired characteristics (current driving capability) can be obtained while reducing the number of power supply systems. Therefore, the circuit configuration can be simplified as compared with the conventional example. (Second Configuration Example) FIG. 2 is a diagram showing a second configuration example of the recording head IJH. This configuration example is a modification of the voltage conversion unit 111 according to the first configuration example, and the other configuration is the same as the first configuration example.

Each voltage converter 111 is a CMOS comprising a pMOS inverter 115 and an nMOS inverter 116.
Inverter, pMOS inverter 118, nMOS
It has an inverter 119, a capacitor 114, and a diode 117, and is controlled by an input signal, that is, an image signal 620 supplied from the latch circuit 402 via the switch 409, and is higher than a voltage supplied from the power supply line 120. A voltage drive signal 630 is generated. It is preferable that the potential of the power supply line 120 be the same as the potential of the power supply line of a circuit such as the latch circuit 403 or the shift register 404, for example.

The CMOS inverter including the pMOS transistor 115 and the nMOS transistor, the pMOS transistor 118 and the nMOS transistor 119 are controlled by the image signal 620 supplied from the latch circuit 403 via the switch 409. The pMOS transistor 118 is a switch element that connects the capacitor 114 and the gate of the MOS power transistor 502 according to the image signal 630, and the nMOS transistor 119 is
MOS power transistor 50 according to image signal 630
2 is a switch element for setting the gate of the second to the ground potential.

In the voltage converter 111 according to this configuration example, the switch 615 of the voltage converter 111 according to the first configuration example shown in FIG. 1 is replaced with a CMOS inverter including a pMOS transistor 115 and an nMOS transistor 116.
The switch 617 is replaced with a diode 117 and a pMOS transistor 118, and the switch 619 is replaced with an nMOS transistor 119.

First, the case where the output of the latch circuit 403, that is, the image signal 620 is H (ink ejection: OFF) will be described. In this case, the pMOS transistor 115
And the output of the CMOS inverter composed of the nMOS transistor 116, that is, the voltage on the point A side of the capacitor 114 becomes substantially 0V. In this case, the nMOS transistor 1
19 is ON, the pMOS transistor 118 is OFF,
The capacitor 114 is charged via the diode 117.

Here, the power supply line 1 of the voltage conversion unit 111
The voltage of 20 is 5 [V], the anode of the diode 117
Assuming that the voltage between the cathodes is VF, the current of the diode exponentially decreases as the VF becomes smaller. Therefore, the cathode potential Vk of the diode 117 (point B in FIG. 2) is several tens of points at which the nozzle is refilled with ink. [μs], Vk = 5V−VF ≒ 4.3V, and assuming that the capacitance of the capacitor 114 is C, the capacitor 114 is charged with the charge of Q = C · Vk.

At this time, the nMOS transistor 119 is
Since it is N, the gate voltage of the MOS power transistor 502 becomes 0 V, no current flows to the heater 401, and no ink is ejected. Next, a case where the output of the latch circuit 403, that is, the image signal 620 is L (ink ejection: ON) will be described. In this case, C is composed of a pMOS transistor 115 and an nMOS 116 transistor.
The output of the MOS inverter, that is, the voltage on the input side (point A) of the capacitor 114 is substantially equal to the voltage of the power supply line 120 and rises to about 5V. Then, the capacitor 114
Rises to about 5V on the input side (point A), the voltage on the output side (point B) of the capacitor 114 connected to the cathode of the diode 117 rises to a voltage of 5V or more. At this time, since the diode 117 is reverse-biased and cut off, the charge accumulated in the capacitor 114 does not move with respect to the power supply line 120.

When the image signal 620 becomes L, the nMOS transistor 119 is turned off and pMO
The S transistor 118 is turned on, and the capacitor 1
The electric charge Q accumulated in 14 is distributed between the gate capacitance Cg of the nMOS power transistor 502 and the capacitor 114, and the gate voltage of the MOS power transistor 502 increases.

Assuming that the charge that moves when the pMOS transistor 118 is turned on is q, the final gate voltage Vg of the MOS power transistor 502 is C >>
When Cg is used, it is obtained as follows. Vg = 5 + Vk ≒ 5 + 4.3 = 9.3 [V] By applying the gate voltage Vg higher than the voltage of the power supply line 120 to the MOS power transistor 502 as described above, the current driving capability of the MOS power transistor 502 is improved. be able to.

The ON / OFF threshold of the voltage converter 111 is determined by the voltage of the power supply line 120, the size ratio between the pMOS transistor 115 and the nMOS transistor 116 constituting the CMOS inverter, and the pMOS transistor 11
8 and the size ratio of the nMOS transistor 119. Therefore, by adjusting these size ratios, the ON / OFF threshold value of the voltage conversion unit 111 can be set to an arbitrary value. For example, if this threshold is 2.5V
By setting it near, it is possible to secure a higher noise margin than that of the voltage converter composed of the resistor and the MOS transistor as shown in FIG.

FIG. 3 shows a recording head IJ.
FIG. 14 is a diagram illustrating a third configuration example of H. In this configuration example, a delay unit 201 is added as a component of the voltage conversion unit 111 according to the second configuration example. Delay device 201
Delays the logic of the image signal 620 without changing it,
MOS transistor 115 and nMOS transistor 11
6 CMOS inverter. Delay device 20
1 is composed of, for example, two-stage inverters 202 and 203.

First, the case where the output of the latch circuit 403, that is, the image signal 620 is H (ink ejection: OFF) will be described. When the image signal 620 transits to H, the output of the delay unit 201 transits to H after a lapse of a predetermined time. At this time, the output of the CMOS inverter including the pMOS transistor 115 and the nMOS transistor 116, that is, the voltage on the point A side of the capacitor 114 becomes substantially 0V. Also,
In this case, the nMOS transistor 119 is ON and the pMO
The S transistor 118 is turned off, and the capacitor 114 is charged via the diode 117.

Here, the power supply line 1 of the voltage conversion unit 111
The voltage of 20 is 5 [V], the anode of the diode 117
Assuming that the voltage between the cathodes is VF, the cathode potential Vk (point B in FIG. 3) of the diode 117 is Vk = 5V-1VF ≒ 4.3V during several tens [μs] at which the ink is refilled into the nozzles. Assuming that the capacitance of the capacitor 114 is C, the charge of Q = C · Vk is charged in the capacitor 114.

At this time, the nMOS transistor 119 is
Since it is N, the gate voltage of the MOS power transistor 502 becomes 0 V, no current flows to the heater 401, and no ink is ejected. Next, a case where the output of the latch circuit 403, that is, the image signal 620 is L (ink ejection: ON) will be described. In this case, the image signal 620
Changes to L, the output of the delay unit 201 changes to L after a predetermined time has elapsed.

On the other hand, when the image signal 620 transitions to L,
In response, the pMOS transistor 118 turns on,
Thereby, the gate voltage of MOS power transistor 502 rises to Vk ′ = 5V−1VF ≒ 4.3V.

Assuming that the capacitance of the capacitor 114 is C and the gate capacitance of the MOS power transistor 502 is Cg, the charges Q and Qg respectively stored at this time are as follows: Q = C · Vk ′ Qg = Cg · Vk ′ When a predetermined time elapses after the image signal 620 changes to L and the output of the delay unit 201 changes to L, nMO
The output of the CMOS inverter including the S transistor 116 and the pMOS transistor 115, that is, the capacitor 11
The voltage on the input side (point A) of the power supply line 1 is approximately 0V.
20 (5 V), and the voltage of the gate of the MOS power transistor 502 increases with the gate capacitance Cg of the MOS power transistor 502.
And the capacitor 114 distribute the charge to change to a voltage determined. Subsequent operations are the same as in the first or second configuration example.

According to this configuration example, as compared with the second configuration example, the capacitor 114 and the nMOS
The total charge stored in the gate of the power transistor 502 is large. Therefore, in order to obtain the same gate voltage Vg as in the second configuration example, in this configuration example, a capacitor 114 having a smaller capacity than in the second configuration example can be used. That is, according to this configuration example, the capacitor 114
Occupied area can be reduced, and a reduction in chip size and cost can be realized.

The configuration of the delay unit 201 is not limited to this circuit configuration. If the diode 117 has a configuration having a time constant sufficient to charge the gate of the MOS power transistor 502, for example, an inverter may be further added. A multi-stage configuration can be adopted, or for example, an RC integration circuit can be used. (Fourth Configuration Example) FIG. 4 is a diagram showing a fourth configuration example of the recording head IJH. Note that, in this configuration example, the diode 117 of the voltage conversion unit 111 according to the second configuration example is pMO
In this embodiment, an S transistor 317 is substituted, and an inverter 312 for controlling the pMOS transistor 317 is added.

First, the case where the output of the latch circuit 403, that is, the image signal 620 is H (ink ejection: OFF) will be described. When the image signal 620 is H, the output of the inverter 312 is L and the pMOS transistor 31
Since 7 is turned on, the capacitor 114 is charged. Here, the voltage of the power supply line 120 of the voltage conversion unit 111 is set to 5
V, when the source-drain voltage of the pMOS transistor 317 is VDS, the drain potential VD of the pMOS transistor 317 rises to VD = 5V−VDS ≒ 5V. Assuming that the capacitance of the capacitor 114 is C,
Thereby, the charge of Q = C · VD is charged in the capacitor 114.

Next, the operation when the output of the latch circuit 403, that is, the image signal 620 is L (ink ejection: ON) will be described. When the image signal 620 is at L, the C signal comprising the pMOS transistor 115 and the nMOS transistor 116
The output of the MOS inverter becomes H, the pMOS transistor 317 turns off, and the electric charge accumulated in the capacitor 114 does not move to the power supply line 120.

When the image signal 620 changes to L,
nMOS transistor 116 and pMOS transistor 1
15, the voltage on the input side (point A) of the capacitor 114 rises from substantially 0 V to a voltage substantially equal to the voltage of the power supply line 120 (5 V).
Accordingly, the voltage of the gate of the MOS power transistor 502 changes to a voltage determined by distributing the electric charge between the gate capacitance Cg of the MOS power transistor 502 and the capacitor 114. Subsequent operations are the same as in the first to third configuration examples.

The pMOS transistor 317 is connected to the power supply line 12 similarly to the diode 117 according to the second configuration example.
From 0, a current is supplied to the capacitor 114 to charge the capacitor 114, but the capacitor 114 functions to prevent discharge from the capacitor 114 to the power supply line 120. Here, the potential at the point B when the capacitor 114 is charged is the second potential.
In this configuration example, the voltage rises to about 4.3 V, whereas in this configuration example, the voltage rises to about 5 V. Therefore, when the same capacitor 114 as that of the second configuration example is employed, in this configuration example, a larger charge can be stored. In other words, when trying to obtain substantially the same characteristics as the second configuration example,
The size (capacity) of the capacitor 114 can be reduced.

The pMOS transistor 317 and the inverter 312 are examples of a switch element, and can be replaced with another element (for example, a bipolar transistor). Further, the above embodiment relates to a recording apparatus of a type in which ink is heated by a heater and ejected from a nozzle. However, for example, the heater can be replaced with a piezoelectric element or the like.

Although the above embodiment is particularly effective when a MOS power transistor is used as the driving unit, this does not prevent adoption of a bipolar transistor as the driving unit. That is, when a bipolar transistor is adopted as the driving unit, it cannot be manufactured by a CMOS process, but the first to third objects can be achieved even in this case.

In the above embodiment, the power supply 120
Has been described as 5 [V], for example, another voltage is appropriately selected according to the withstand voltage of the power transistor, the gate voltage at which the ON resistance of the power transistor is stabilized, and the power supply voltage of the latch circuit, the shift register circuit, and the like. can do. In addition, the present invention is applicable to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but also to a device including one device (for example, a copying machine, a facsimile machine, etc. ) May be applied.

According to the above-described embodiment, for example, the current drive capability of the drive unit for driving the ink discharge unit is increased, and the noise margin in the drive signal generation unit for generating a drive signal for driving the drive unit is reduced. Can be secured. According to the above-described embodiment, for example, current consumption in the drive signal generation unit can be suppressed, and the influence of the number of bits for ejecting ink can be reduced.

Further, according to the above-described embodiment, for example, the current drive capability of the drive unit can be increased while reducing the number of power supply systems.

[0081]

According to the present invention, for example, it is possible to increase the current driving capability of the driving unit for driving the ink ejection unit.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first configuration example of a recording head IJH.

FIG. 2 is a diagram illustrating a second configuration example of a recording head IJH.

FIG. 3 is a diagram illustrating a third configuration example of the recording head IJH.

FIG. 4 is a diagram illustrating a fourth configuration example of the recording head IJH.

FIG. 5 is an external perspective view illustrating an outline of a configuration of an ink jet printer (IJRA) as a typical embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a control circuit of the inkjet printer IJRA.

FIG. 7 is an external perspective view illustrating a configuration of an ink cartridge IJC in which an ink tank and a head are separable.

FIG. 8 is a diagram showing a circuit configuration of a recording head mounted on a conventional inkjet recording apparatus.

9 is a diagram showing a signal waveform in the recording head shown in FIG.

FIG. 10 is a recording head obtained by improving the recording head shown in FIG.

[Explanation of symbols]

 111 Voltage conversion unit 114 Capacitor 117 Diode 120 Power line 201 Delay unit 317 Transistor 401 Resistance (heater) 402 Bipolar transistor (Drive unit) 403 Latch circuit 404 Shift register 409 Switch 502 nMOS transistor (Drive unit) 615 First switch 617 Second Switch 619 Third switch 620 Image signal 630 Drive signal

Claims (18)

[Claims] 1. A recording head that controls ejection of ink based on an image signal to record an image on a recording medium, comprising: a driving unit that drives an ink ejection unit; and a driving unit that drives the ink ejection unit based on an image signal. A drive signal generating unit for generating a drive signal for controlling, the drive signal generating unit having a capacitor, and generating the drive signal having a voltage higher than a power supply voltage using the capacitor. A recording head characterized by the above-mentioned. 2. The charging circuit according to claim 2, wherein the capacitor has first and second terminals, and the driving signal generator applies a voltage between the first terminal and the second terminal to charge the capacitor. And an application circuit for setting the first terminal to a predetermined potential and electrically connecting the second terminal to an input terminal of the driving unit to apply a drive signal to the input terminal. The recording head according to claim 1. 3. The recording head according to claim 2, wherein the charging circuit includes a diode having an anode connected to a power supply and a cathode connected to a second terminal of the capacitor. 4. The charging circuit according to claim 1, wherein the first terminal of the capacitor is grounded when the image signal is at a first logic level, and the first terminal is connected to a power supply when the image signal is at a second logic level. A switch circuit, wherein the application circuit connects a second terminal of the capacitor to a power supply when the image signal is at the first logic level, and connects the second terminal when the image signal is at the second logic level. The recording head according to any one of claims 2 to 4, wherein the recording head is electrically connected to an input terminal of the driving unit. 5. The driving signal generating circuit according to claim 4, wherein the driving signal generating circuit further includes a delay unit for delaying the image signal, and the first switch is controlled by an output of the delay unit. Recording head. 6. The charging circuit according to claim 1, further comprising a transistor between a power supply line and a second terminal of the capacitor, wherein the transistor is controlled based on a logic level of the image signal. Item 3. The recording head according to Item 2. 7. The charging circuit, when the image signal is at a first logical level, grounds a first terminal of the capacitor and connects a second terminal of the capacitor to a power supply, and the image signal is supplied to a second logical level. When the level is at the level, the first terminal is connected to a power source and the second terminal is electrically disconnected from the power source. The application circuit grounds the second terminal of the capacitor when the image signal is at the first logic level. 7. The recording head according to claim 6, wherein the second terminal is electrically connected to an input terminal of the driving unit when the image signal is at the second logical level. 8. The recording head according to claim 1, wherein the driving unit includes a transistor controlled by the driving signal. 9. The recording head according to claim 8, wherein the transistor of the driving unit is a MOS transistor. 10. The capacity of the capacitor is equal to the MOS
10. The recording head according to claim 9, wherein the recording head is larger than a gate capacitance of the transistor. 11. A dielectric material constituting the capacitor and a gate insulating film of the MOS transistor are made of the same material, and a thickness of the dielectric is smaller than a thickness of the gate insulating film. The recording head according to claim 9. 12. The recording head according to claim 9, wherein a dielectric constant of a dielectric constituting the capacitor is higher than a dielectric constant of a gate insulating film of the MOS transistor. 13. The recording head according to claim 5, wherein said delay unit is formed of a CMOS circuit. 14. The recording head according to claim 5, wherein said delay unit includes an RC integrating circuit. 15. The recording head according to claim 1, wherein the driving unit and the driving signal generating unit are manufactured by a CMOS process. 16. A shift register having a plurality of sets of the driving unit and the driving signal generating unit, further converting a serially supplied image signal into a parallel image signal, and each image output from the shift register. A plurality of latch circuits each latching a signal, and a transmission circuit transmitting an output of each of the plurality of latch circuits to a corresponding one of the drive signal generation units in accordance with a control signal, wherein the drive unit, the drive signal generation unit 2. The shift register, the latch circuit and the transmission circuit are driven by the same power supply.
6. The recording head according to any one of 5. 17. The recording apparatus according to claim 1, wherein the ink ejection unit includes a nozzle and a heater that heats ink filled in the nozzle. head. 18. The method according to claim 1, wherein:
A recording apparatus, comprising the recording head according to item 13.