JP2000036742A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically correct a PLL unbalance current so as to always obtain optimum characteristics irrelevantly to the value of a PLL unbalance current quantity. SOLUTION: An EFM signal 2 generated by digitizing an analog signal read out of a disk and a PCK signal 3 as the output clock from a voltage-controlled oscillator 1 are inputted to a phase comparator 4, the difference between the Pch charge pump drive signal width and Nch charge pump drive signal width outputted from the phase comparator 4 is detected, and a control current source 7 consisting of a Pch charge pump and an Nch charge pump is brought under feedback control for controlling the phase difference between the EFM signal 2 and PCK signal 3 to an optimum value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a phase-locked loop (PLL) applied to a disk device such as a CD-ROM.
It is related to the circuit.

[0002]

2. Description of the Related Art The configuration of a conventional PLL circuit will be described with reference to FIG.

In FIG. 9, reference numeral 1 denotes a voltage controlled oscillator;
Is an EFM signal obtained by digitizing an analog signal read from a disk, 3 is a PCK signal which is an output clock of the voltage controlled oscillator 1, 4 is a phase comparator, 7 is a constant current source, 9
Is a filter circuit, 12 is a current correction circuit, and 13 is a switch. In this example, an example in which a charge pump is used as the constant current source 7 will be described.

[0004] The EFM signal 2 and the PCK signal 3 are input to a phase comparator 4 where the phases of the signals are compared. The phase comparator 4 outputs two signals, a signal for driving the Pch charge pump in the constant current source 7 and a signal for driving the Nch charge pump.
(Low), the Pch charge pump is driven and Nc
If the h drive signal is H (High), the Nch charge pump is driven. When the phase comparison is not being performed, the Pch drive signal becomes H, the Nch drive signal becomes L, and the drive of the charge pump is stopped. The output current of the constant current source 7 driven by the phase comparison signal is converted into a voltage using the filter circuit 9, and the voltage is input to the voltage-controlled oscillator 1, whereby the PCK signal 3 synchronized with the EFM signal 2 is obtained.
Has been generated.

[0005] The difference between the Pch charge pump current and the Nch charge pump current in the constant current source 7 is called an unbalanced current.
Of the wire is deteriorated. Therefore, a current correction circuit 12 is provided to correct the imbalance current, and a correction amount is externally set, and the switch 1 is set according to the set value.
3 is turned on to perform correction.

[0006]

The PLL charge pump unbalance current amount is not always the same, but differs for each LSI chip, for example. Also, it changes depending on the reproduction speed.

However, in the conventional configuration, only the current correction of a fixed amount set in advance can be corrected, so that the current cannot be completely corrected unless the amount of unbalanced current is within a certain range. Therefore, outside the correction range, the pull-in characteristic of the PLL deteriorates, causing a problem such as a deterioration in an error rate or a problem in access.

The present invention has been made to solve the above-mentioned conventional problem. In order to always obtain an optimum characteristic irrespective of the value of the PLL unbalance current amount, a PLL capable of automatically correcting the PLL unbalance current is provided. It is intended to provide a circuit.

[0009]

In order to achieve the above object, the present invention has the following arrangement. That is, a voltage controlled oscillator that generates an oscillation clock according to an input voltage, a phase comparator that compares a phase difference between an input signal and the oscillation clock and outputs a phase comparison signal, and is driven by the phase comparison signal. A constant current source, a filter circuit that converts a current output from the constant current source into a voltage and supplies the voltage as an input voltage of the voltage controlled oscillator, a counter that measures a signal width of the phase comparison signal, A current value control circuit for controlling the output current value of the constant current source according to the count value of the counter, and further comprising an offset addition circuit for adding an offset width to the signal width of the phase comparison signal to the configuration. ing.

The present invention also provides a voltage-controlled oscillator for generating an oscillation clock corresponding to an input voltage, a phase comparator for comparing a phase difference between an input signal and the oscillation clock and outputting a phase comparison signal, A constant current source driven by the phase comparison signal, a filter circuit that converts a current output from the constant current source into a voltage and supplies the voltage as an input voltage of the voltage-controlled oscillator, and measures a signal width of the phase comparison signal , A PWM circuit that outputs a PWM signal corresponding to the count value of the counter, and an adjustment circuit that adjusts the input voltage of the voltage-controlled oscillator by the PWM signal. And an offset adding circuit for adding an offset width to the signal width of the signal.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a PLL circuit for explaining a first embodiment of the present invention. 1 is a voltage-controlled oscillator, 2 is an EFM signal obtained by digitizing an analog signal read from a disk, and 3 is PCK signal, which is an output clock of the voltage controlled oscillator 1, 4 is a phase comparator that compares the phase of the EFM signal and the PCK signal and outputs a phase comparison signal, and 5 is an offset addition that adds an offset width to the phase comparison signal width. A circuit, 6 is a counter for measuring the output signal width of the offset addition circuit 5, 7 is a constant current source driven by the phase comparison signal, and 8 is a control of the output current of the constant current source 7 according to the count value of the counter 6. The current value control circuit 9 is a filter circuit for converting the current output from the constant current source 7 into a voltage.

The operation of the first embodiment having the above configuration will be described with respect to an example in which a plurality of charge pumps (CP) are used as the constant current source 7 and an up / down counter is used as the counter 6.

The EFM signal 2 and the PCK signal 3 are input to a phase comparator 4 where the phases of the signals are compared. The phase comparator 4 outputs a Pch charge pump drive signal and an Nch charge pump drive signal as shown in FIG.
The Pch charge pump drive signal is a signal which becomes L during the period from the detection of the edge of the EFM signal 2 to the rising edge of the second pulse of the PCK signal 3, and the Nch charge pump drive signal causes the edge of the EFM signal 2 to P after detection
From the rising edge of the CK signal 3 to the rising edge of the next PCK signal 3, the signal is always at H for a period of 1 PCK.

The charge pump current amount is N
The ch charge pump current is set to 1.5 times the Pch charge pump current. Therefore, when there is no imbalance current as shown in FIG. 2, the charge pump drive signal width is Pch: Nch = 1.5PCK: 1P
In the case of CK, that is, in a state where the phase of the EFM signal 2 and the phase of the PCK signal 3 are matched, the area A = the area B, the current amount is balanced, and the PLL is locked.

Next, the Pch output from the phase comparator 4
The charge pump drive signal and the Nch charge pump drive signal are input to the offset adding circuit 5 and the constant current source 7. The offset addition circuit 5 adds a set value as an offset width to the Pch charge pump drive signal and the Nch charge pump drive signal in order to finely adjust the optimum position of the phase difference between the EFM signal and the PCK signal. Is output to the counter 6. When the offset width is not added, the same signal as the charge pump drive signal output from the phase comparator 4 is input to the counter 6.

The counter 6 detects the difference between the width of the Pch charge pump drive signal and the width of the Nch charge pump drive signal.
The width when both the h charge pump drive signal is L is up-counted, and the width when the Nch charge pump drive signal is H is down-counted by 1/2 clock of the up-count.

As shown in FIG. 2, when Pch charge pump current: Nch charge pump current = 1: 1.5, that is, when there is no imbalance current,
Since the ratio of the width when the Pch charge pump drive signal and the Nch charge pump drive signal are both L to the width when the Nch charge pump drive signal is H is 1: 2, the value of the counter 6 becomes zero. .

As shown in FIG. 3, when the Pch charge pump current is larger than a desired value, assuming that the unbalance current is b, Pch charge pump current: Nch charge pump current = (1 + b): 1.5. , PCK
When the phase of signal 3 is advanced, area A = area B and P
LL locks. Assuming that the phase shift width at this time is a, the charge pump drive signal width is Pch: Nch =
(1.5PCK-a): 1PCK, and the counter 6 takes a negative value.

Conversely, as shown in FIG. 4, the Pch charge pump current is smaller than a desired value, and the Pch charge pump current: Nch charge pump current = (1-b): 1.
When it is 5, area A = area B with the phase of the PCK signal 3 delayed, and the PLL is locked. The charge pump drive signal width at this time is Pch: Nch =
1.5 (PCK + a): 1PCK, and the counter 6 takes a positive value.

The respective values of the counter 6 are input to the current value control circuit 8, and are output to the constant current source 7 at the timing when the phase comparison output is not output. The Pch side of the constant current source 7 is composed of a reference 100% charge pump and 1% and 2% charge pumps for current correction, and a combination of 1% and 2% enables a 1% to 3% current correction. It is. On the Nch side, a reference 150% charge pump and 1%, 2%, 4%, 8%, 16%
% And 32% of charge pumps, and a combination thereof allows a current correction of 1 to 64%.

On both the Pch side and the Nch side, the reference charge pump is controlled only by the phase comparison signal. If the Pch drive signal is L, the Pch charge pump is driven. If there is, the Nch charge pump is driven. When phase comparison is not performed,
The Pch drive signal becomes H, the Nch drive signal becomes L, and the drive of the charge pump is stopped. Other charge pumps for current correction are turned on by the current value control circuit 8.
The charge pump is turned off. The current correction charge pump has a current amount of 2n units, and a current correction value can be obtained by decoding the value of the counter 6 by the current value control circuit 8.

As described above, the output current amount of the constant current source 7 is determined by the value of the counter 6, and this current is converted into a voltage by the filter circuit 9 and is used as the input voltage of the voltage-controlled oscillator 1 to obtain the PCK signal. 3 has been generated. For example, when the counter 6 takes a negative value, since the phase of the PCK signal 3 is advanced, the Nch correction charge pump in the constant current source 7 is turned on, the Nch charge pump current is increased, and the voltage control is performed. By lowering the input voltage of the oscillator 1, the phase of the PCK signal 3 is delayed, and the EFM-PCK phase difference is controlled to the optimum position as shown in FIG. When the counter 6 takes a positive value, the PCK signal 3
Is delayed, the Pch correction charge pump in the constant current source 7 is turned on, the Pch charge pump current is increased, and the input voltage of the voltage controlled oscillator 1 is increased, so that the phase of the PCK signal 3 is changed. Then, as shown in FIG. 2, the phase difference between the EFM signal and the PCK signal is controlled to the optimum position.

When the PLL comes off due to access or the like, a normal EFM signal is not input, so that the phase comparison is not performed normally. In such a case, the counter 6
The counter clock is stopped, and the counter value before the PLL comes off is output, or the data of the counter 6 is set in advance and the value is output to prevent abnormal operation.

FIG. 5 is a block diagram of a PLL circuit for explaining a second embodiment of the present invention. Members corresponding to those described in the first embodiment are denoted by the same reference numerals and are described in detail. Is omitted.

In FIG. 5, reference numeral 1 denotes a voltage-controlled oscillator;
Is an EFM signal, 3 is a PCK signal, 4 is a phase comparator, 5 is an offset addition circuit, 6 is a counter, 7 is a constant current source, 9
Is a filter circuit, and 10 is a PWM corresponding to the value of the counter 6.
(Pulse width modulation) PWM circuit for outputting a signal,
This is an adjustment circuit that adjusts the input voltage of the voltage controlled oscillator 1 using the WM signal.

The operation of the second embodiment having the above configuration will be described with respect to an example in which a charge pump is used as a constant current source and an up / down counter is used as a counter.

The phase comparison method and the operations of the offset addition circuit 5 and the counter 6 are the same as in the first embodiment. Further, the constant current source 7 is constituted only by the reference charge pump used in the first embodiment, and its operation is the same as that of the first embodiment.
The difference from the first embodiment is that the output of the counter 6 is controlled by the PWM circuit 10.

Hereinafter, the PWM circuit 1 according to the second embodiment will be described.
0 will be described. That is, the value of the counter 6 is PW
The PWM signal is input to the M circuit 10 and is output from the PWM circuit 10 as shown in FIG. The PWM signal is converted into a current by the adjustment circuit 11, further converted into a voltage by the filter circuit 9, and input to the voltage controlled oscillator 1.
When the value of the counter 6 is zero, as shown in FIG.
And L are output in the same period.

When the value of the counter 6 is negative, as shown in FIG. 7, a waveform having a short H period is output and discharged from the filter circuit 9 to the PWM circuit 10, so that the voltage-controlled oscillator 1 , The phase of the PCK signal 3 is delayed, and the phase difference between the EFM signal and the PCK signal is controlled to the optimum position as shown in FIG.

When the value of the counter 6 is positive, a waveform having a long H period is output as shown in FIG. 8 and the PWM circuit 10 charges the filter circuit 9.
, The phase of the PCK signal 3 is advanced, and the phase difference between the EFM signal and the PCK signal is controlled to the optimum position as shown in FIG.

As described above, in the second embodiment, it is not necessary to provide many charge pumps for correction, and a simpler configuration can be achieved.

In the first and second embodiments, the PLL
Is described, the counter value before the PLL comes off or a preset value is output from the counter 6. However, the value is set in the current value control circuit 8 or the PWM circuit 10 instead of the counter 6. Even if output, the same effect can be obtained.

The first and second phase comparison methods are also described.
It is not limited to the method used in the embodiment.

[0035]

As described above, according to the present invention, it is not necessary to externally set a correction current value by automatically correcting a PLL charge pump unbalance current which is not always the same, and the EFM signal-PCK Since the phase difference of the signal can be controlled to the optimum position, problems such as deterioration of an error rate or access failure can be improved.

[Brief description of the drawings]

FIG. 1 is a PLL for explaining a first embodiment of the present invention;
Circuit configuration diagram

FIG. 2 is a diagram showing a charge pump drive signal when a phase difference between an EFM signal and a PCK signal is at an optimum position in the first embodiment;

FIG. 3 is a diagram showing a charge pump drive signal when a phase difference between an EFM signal and a PCK signal is advanced in the first embodiment;

FIG. 4 is a diagram showing a charge pump drive signal when a phase difference between an EFM signal and a PCK signal is delayed in the first embodiment;

FIG. 5 is a PLL for explaining a second embodiment of the present invention.
Circuit configuration diagram

FIG. 6 is a diagram illustrating an output signal of a PWM circuit when a value of an up / down counter is zero in the second embodiment.

FIG. 7 is a diagram showing an output signal of a PWM circuit when a value of an up / down counter is negative in the second embodiment.

FIG. 8 is a diagram showing an output signal of a PWM circuit when a value of an up-down counter is positive in the second embodiment.

FIG. 9 is a configuration diagram of a conventional PLL circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 voltage controlled oscillator 2 EFM signal 3 PCK signal 4 phase comparator 5 offset addition circuit 6 counter 7 constant current source 8 current value control circuit 9 filter circuit 10 PWM circuit 11 adjustment circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuhiko Kubo 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5J060 AA04 BB03 BB04 CC01 CC21 CC41 DD13 DD17 DD32 GG07 GG15 HH03 JJ08 KK12

Claims (6)

[Claims] A voltage-controlled oscillator that generates an oscillation clock corresponding to an input voltage; a phase comparator that compares a phase difference between an input signal and the oscillation clock to output a phase comparison signal; And a filter circuit that converts a current output from the constant current source into a voltage and supplies the voltage as an input voltage of the voltage-controlled oscillator, the PLL circuit comprising: A PLL circuit comprising: a counter for measuring a signal width of a signal; and a current value control circuit for controlling an output current value of the constant current source according to a count value of the counter. 2. The PLL circuit according to claim 1, wherein the current value control circuit changes an output current value of the constant current source when the phase comparison signal is not output. 3. A voltage-controlled oscillator for generating an oscillation clock according to an input voltage, a phase comparator for comparing a phase difference between an input signal and the oscillation clock and outputting a phase comparison signal, and the phase comparison signal. And a filter circuit that converts a current output from the constant current source into a voltage and supplies the voltage as an input voltage of the voltage-controlled oscillator, the PLL circuit comprising: A counter for measuring the signal width of the signal, a PWM circuit for outputting a PWM (pulse width modulation) signal according to the count value of the counter, and an adjustment circuit for adjusting the input voltage of the voltage controlled oscillator by the PWM signal. A PLL circuit, comprising: 4. The PL according to claim 1, wherein the counter stops measuring when the PLL is asynchronous.
L circuit. 5. A counter or current control circuit or PW
When the M circuit is out of PLL, regardless of the count value,
4. The PLL circuit according to claim 1, wherein a preset value output in advance is output. 6. An apparatus according to claim 1, further comprising an offset adding circuit for adding an offset width to a signal width of the phase comparison signal, wherein the counter measures a signal width of the phase comparison signal to which the offset width is added. 3. The PLL circuit according to 3.