JP2000036544A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the memory-cell structure which can achieve high integration, and the surrounding circuit which can perform stable operation. SOLUTION: The region, which faces the opening end of a first element isolation groove 106 at the surface of a P-type silicon substrate that becomes the active region of an MOS transistor constituting a memory cell 143 of a given memory-cell region 105, is made to be the shape so that the electric-field concentration is easy to be generated in gate-voltage application. Thus, the memory part 143 has two MOS transistor parts having the different threshold voltages. The content of information is made to correspond to the respective threshold voltage. Thus, two kinds of the information can be stored. The region in correspondence with the opening ends of second element isolation grooves 114 and 115 at the surface of the P-type silicon substrate 101 that become the active regions of surrounding circuit regions 112 and 113 are made to have the shape, wherein electric-field concentration is hard to occur in gate-voltage application. P-type impurity layers 120 are provided at least at the side walls of the second element isolation grooves 114 and 115. Thus, the MOS transistor having the single threshold voltage is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for storing multilevel information and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been highly integrated, and each element constituting the semiconductor memory device has become extremely fine. One of the semiconductor storage devices has a read-only memory for storing nonvolatile information, that is, a ROM (Rea).
d Only Memory). Among them, a ROM for performing a program in a wafer processing step, a so-called mask ROM, has a simpler memory cell structure than a DRAM or the like, so that high integration and large capacity can be easily performed.

As a typical programming method of a conventional mask ROM, a threshold voltage is increased by increasing a gate insulating film thickness of a MOS transistor of a specific memory cell among MOS transistors constituting a memory cell. There is a method in which a difference in threshold voltage is used as a storage state. Hereinafter, a conventional semiconductor memory device will be described with reference to FIG. FIG. 20 is a schematic sectional view showing two types of memory cells of a conventional semiconductor memory device (mask ROM).

In the memory cell A shown in FIG.
A gate electrode 504 is formed on a mold silicon substrate 501 with a gate oxide film 502 interposed therebetween. Gate electrode 504
Are formed on both sides thereof. On the silicon substrate 501, an N-type low-concentration impurity diffusion layer 505 and an N-type high-concentration impurity diffusion layer 507 are formed on both sides of the gate electrode 504, respectively, so that an LDD (Lightly Doped Drain) is formed.
This is a MOS transistor having an n) structure. And
An aluminum wiring 510 is connected to each high-concentration impurity diffusion layer 507 via a contact hole 509 provided in an interlayer insulating film 508.

On the other hand, memory cell B shown in FIG.
Is substantially the same as the memory cell A except that a gate oxide film 503 which is considerably thicker than the gate oxide film 502 of the memory cell A is formed. The MO of memory cell B is formed by this thick gate oxide film 503.
The threshold voltage of the S transistor is equal to the MO of the memory cell A.
The threshold voltage is considerably higher than the threshold voltage of the S transistor.
The OS transistor is not turned on. That is, when the same gate voltage is applied to the memory cell A and the memory cell B, the MOS transistor of the memory cell A is turned on and the MOS transistor of the memory cell B is not turned on. Is obtained.

[0006]

However, in the above-mentioned conventional semiconductor memory device, the thicknesses of the gate oxide films 502 and 503 are changed for each memory cell according to the storage state. Has a problem that two memory cells are required, and it is difficult to achieve high integration.

Furthermore, in a miniaturized semiconductor memory device, the operation of a MOS transistor in a peripheral circuit region which controls the operation of a memory cell may become unstable due to a change in threshold voltage due to a short channel effect or a narrow channel effect. There is. A first object of the present invention is to provide a semiconductor memory device capable of realizing a memory cell structure capable of achieving high integration and a method of manufacturing the same.

[0008] Further, a second object of the present invention is to provide the above first object.
It is another object of the present invention to provide a semiconductor memory device having a peripheral circuit capable of performing a stable operation and a method of manufacturing the same.

[0009]

Means taken by the present invention to achieve the above object are to provide, for each memory cell, a MOS transistor portion having a high threshold voltage and a MOS transistor portion having a low threshold voltage. And a transistor section. Specifically, the measures described in the following claims are taken.

According to a first aspect of the present invention, there is provided a semiconductor memory device including a memory cell array region in which a plurality of memory cells are arranged and a peripheral circuit region thereof, wherein at least one of the plurality of memory cells is provided. In a cell region, a source region and a drain region formed of an impurity layer of another conductivity type formed on the surface of a semiconductor substrate of one conductivity type, a channel region formed between the source region and the drain region, and a gate insulating film. MOS transistor having a gate electrode formed on a channel region by
A plurality of device isolation trenches arranged with openings in the semiconductor substrate on both sides in the channel width direction of the transistor, and a buried insulating film embedded in the device isolation trenches, and a MOS facing the opening end of the device isolation trench It is characterized in that the channel region, the source region and the drain region of the transistor are shaped so that electric field concentration easily occurs when a bias is applied to the gate electrode.

According to this structure, in at least one memory cell region of the plurality of memory cells, the active region (channel region, source region and drain region) of the MOS transistor facing the opening end of the isolation trench is gated. By adopting a shape in which electric field concentration is likely to occur when a bias is applied to the electrodes, the MOS transistors share the gate electrode and have a high threshold voltage at the center of the active region.
MOS transistor portion and a second MOS transistor having a low threshold voltage formed at an end of an active region having a shape facing an opening end of an element isolation groove and easily causing electric field concentration when a bias is applied to a gate electrode. Part. By associating different threshold voltages of the first and second MOS transistor portions with different storage states, two types of information can be stored in one memory cell. In addition, since one memory cell includes two types of MOS transistor portions, high integration can be achieved without increasing the memory cell area.

According to a second aspect of the present invention, in the semiconductor memory device of the first aspect, the position of the surface of the buried insulating film is lower than the positions of the surface of the channel region, the source region, and the drain region of the MOS transistor. Features. As a result, the channel width of the second MOS transistor portion formed at the end of the active region increases,
The operation of the MOS transistor section is stabilized.

According to a third aspect of the present invention, there is provided a semiconductor memory device according to the first aspect, wherein a source region comprising an impurity layer of another conductivity type formed on a surface of the semiconductor substrate of one conductivity type is provided in the peripheral circuit region. A peripheral MOS transistor having a drain region, a channel region formed between the source region and the drain region, a gate electrode formed on the channel region via a gate insulating film, and both sides of the peripheral MOS transistor in the channel width direction A plurality of peripheral element isolation grooves arranged with an opening in the semiconductor substrate, an impurity layer of one conductivity type formed on sidewalls of the peripheral element isolation grooves, and a peripheral buried insulation embedded in the peripheral element isolation grooves A channel region, a source region, and a drain region of the peripheral MOS transistor facing the opening end of the peripheral element isolation groove are connected to the gate electrode. Characterized in that the electric field concentration was less susceptible shape upon application of.

According to this configuration, in the peripheral circuit region, when a bias is applied to the active region (channel region, source region and drain region) of the peripheral MOS transistor facing the opening end of the peripheral element isolation groove, the gate electrode is applied. By making the shape less likely to cause electric field concentration, the electric field concentration at the edge of the active region when the gate voltage is applied is reduced, and a one conductivity type impurity layer is formed on the side wall of the peripheral device isolation groove. The MOS transistor in the peripheral circuit region becomes a MOS transistor having a single threshold voltage at the edge of the active region and the central portion of the active region, so that a stable circuit operation is performed.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the position of the surface of the buried insulating film is lower than the positions of the surface of the channel region, the source region, and the drain region of the MOS transistor. The position of the surface of the buried insulating film is lower than the position of the surface of the channel region, source region and drain region of the peripheral MOS transistor.

According to this structure, in the memory cell region, the position of the surface of the buried insulating film is lower than the position of the surface of the active region of the MOS transistor, so that the second region formed at the end of the active region is formed. The channel width of the MOS transistor portion is increased, the operation of the second MOS transistor portion is stabilized, and the position of the peripheral buried insulating film surface in the peripheral circuit region is lower than the surface position of the active region of the peripheral MOS transistor. The surrounding M
The operation of the OS transistor is more stable.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the first, second, third or fourth aspect, the MOS transistor of the memory cell includes a first MOS transistor portion having a high threshold voltage. And a second MOS transistor portion having a low threshold voltage. As described above, the MOS transistor of the memory cell includes the first MOS transistor portion having a high threshold voltage and the second MOS transistor having a low threshold voltage.
Since each of the first and second MOS transistor units has a different threshold voltage corresponding to a different storage state, two memory transistors can be used in one memory cell.
Various types of information can be stored, and high integration can be achieved without increasing the memory cell area.

According to a sixth aspect of the present invention, in the semiconductor memory device of the fifth aspect, the difference in threshold voltage between the first MOS transistor section and the second MOS transistor section is stored in a memory cell. It is characterized in that it is used as a state difference. 8. A semiconductor memory device according to claim 7, comprising a memory cell array region in which a plurality of memory cells are arranged and a peripheral circuit region thereof, wherein the plurality of memory cells are a first memory cell and a second memory cell.
A source region and a drain region formed of an impurity layer of another conductivity type formed on a surface of a semiconductor substrate of one conductivity type, and a source region and a drain in a region of the first memory cell. A MOS transistor having a channel region formed between the regions and a gate electrode formed on the channel region via a gate insulating film, and a semiconductor substrate is arranged on both sides of the MOS transistor in the channel width direction with openings. A plurality of first element isolation trenches, and a first buried insulating film embedded in the first element isolation trenches, and M faces the opening end of the first element isolation trench.
The channel region, the source region, and the drain region of the OS transistor are shaped so that electric field concentration easily occurs when a bias is applied to the gate electrode.
A source region and a drain region formed of an impurity layer of another conductivity type formed on a surface of a semiconductor substrate of one conductivity type, a channel region formed between the source and drain regions, and a gate insulating film on the channel region. A MOS transistor having a gate electrode formed thereon; an impurity layer of one conductivity type formed in a channel region of the MOS transistor; and a plurality of transistors arranged on both sides of the MOS transistor in a channel width direction by opening a semiconductor substrate. A second trench for element isolation and a second buried insulating film embedded in the second trench for element isolation are provided, and M faces the opening end of the second trench for element isolation.
The channel region, the source region, and the drain region of the OS transistor are shaped so that electric field concentration hardly occurs when a bias is applied to the gate electrode.

According to this configuration, the plurality of memory cells have at least one first memory cell and at least one second memory cell, and the first memory cell region has a first element isolation trench. The active region (channel region, source region, and drain region) of the MOS transistor facing the opening end is shaped so that electric field concentration easily occurs when a bias is applied to the gate electrode.
The OS transistor shares the gate electrode, and the first MOS transistor portion having a high threshold voltage at the center of the active region and the first MOS transistor portion facing the opening end of the element isolation trench cause electric field concentration when a bias is applied to the gate electrode. The second MOS transistor portion having a low threshold voltage is formed at the end of the active region having a shape which is likely to occur. By associating different threshold voltages of the first and second MOS transistor portions with different storage states, two types of information can be stored in one memory cell.

Further, in the area of the second memory cell,
The active region (channel region, source region and drain region) of the MOS transistor facing the opening end of the second isolation trench is shaped so that electric field concentration hardly occurs when a bias is applied to the gate electrode. Although the electric field concentration at the end of the active region at the time of application is alleviated, since the impurity layer is not provided on the side wall of the second isolation trench, the MOS transistor in the second memory cell region has a gate electrode. Third M having a high threshold voltage in the middle of the active region
An OS transistor portion and a fourth MOS transistor portion having a low threshold voltage at an end of an active region, which has a shape which faces the opening end of the isolation groove and has a shape in which electric field concentration is unlikely to occur when a bias is applied to the gate electrode. Thus, two types of information can be stored in one memory cell by associating different threshold voltages of the third and fourth MOS transistor units with different storage states. Second
Forming the impurity layer of one conductivity type in the channel region of the MOS transistor in the region of the memory cell, the threshold voltage of the third MOS transistor portion and the
It becomes higher than the threshold voltage of the transistor section.

As described above, in the first memory cell region and the second memory cell region, each of the memory cells has two types of MOS transistor portions, and the first and second memory cells are provided. In this area, four-valued information can be stored, and high integration can be achieved without increasing the memory cell area. The semiconductor memory device according to claim 8 is the semiconductor memory device according to claim 7, wherein the position of the surface of the first buried insulating film in the region of the first memory cell is the position of the channel region, the source region, and the drain region of the MOS transistor. The position of the surface of the second buried insulating film in the region of the second memory cell is lower than the position of the surface of the channel region, the source region and the drain region of the MOS transistor.

According to this structure, in the region of the first memory cell, the position of the surface of the first buried insulating film is MOS.
Since it is lower than the position of the surface of the active region of the transistor, the channel width of the second MOS transistor formed at the end of the active region is increased, and the operation of the second MOS transistor is stabilized. Similarly, in the region of the second memory cell, the position of the surface of the second buried insulating film is lower than the position of the surface of the active region of the MOS transistor. M
The channel width of the OS transistor section is increased, and the operation of the fourth MOS transistor section is stabilized.

A semiconductor memory device according to a ninth aspect of the present invention is the semiconductor memory device according to the seventh aspect, wherein the peripheral circuit region includes a source region comprising an impurity layer of another conductivity type formed on the surface of the semiconductor substrate of one conductivity type; A peripheral MOS transistor having a drain region, a channel region between the source region and the drain region, a gate electrode formed on the channel region via a gate insulating film, and a semiconductor substrate on both sides of the peripheral MOS transistor in the channel width direction. A plurality of peripheral device isolation trenches having openings formed therein, an impurity layer of one conductivity type formed on sidewalls of the peripheral device isolation trenches, and a peripheral buried insulating film embedded in the peripheral device isolation trenches. A bias is applied to the gate electrode of the channel region, the source region and the drain region of the peripheral MOS transistor facing the opening end of the peripheral element isolation groove. Wherein the electric field concentration was less susceptible shape when.

According to this structure, in the peripheral circuit region, when a bias is applied to the active region (channel region, source region and drain region) of the peripheral MOS transistor facing the opening end of the peripheral element isolation groove, the gate electrode is applied. By making the shape less likely to cause electric field concentration, the electric field concentration at the edge of the active region when the gate voltage is applied is reduced, and a one conductivity type impurity layer is formed on the side wall of the peripheral device isolation groove. The MOS transistor in the peripheral circuit region becomes a MOS transistor having a single threshold voltage at the edge of the active region and the central portion of the active region, so that a stable circuit operation is performed.

According to a tenth aspect of the present invention, in the semiconductor memory device of the ninth aspect, the position of the surface of the first buried insulating film in the region of the first memory cell is MO.
The position of the surface of the second buried insulating film in the region of the second memory cell is lower than the position of the surface of the channel region, the source region and the drain region of the S transistor, and the surface of the channel region, the source region and the drain region of the MOS transistor And the position of the surface of the peripheral buried insulating film in the peripheral circuit region is lower than the position of the surface of the channel region, source region and drain region of the peripheral MOS transistor.

According to this structure, in the region of the first memory cell, the position of the surface of the first buried insulating film is MOS.
Since it is lower than the position of the surface of the active region of the transistor, the channel width of the second MOS transistor formed at the end of the active region is increased, and the operation of the second MOS transistor is stabilized. Similarly, in the region of the second memory cell, the position of the surface of the second buried insulating film is lower than the position of the surface of the active region of the MOS transistor. M
The channel width of the OS transistor section is increased, and the operation of the fourth MOS transistor section is stabilized. In the peripheral circuit region, the position of the surface of the peripheral buried insulating film is lower than the position of the surface of the active region of the peripheral MOS transistor, so that the operation of the peripheral MOS transistor is more stable.

In the semiconductor memory device according to the eleventh aspect, in the semiconductor memory device according to the seventh, eighth, ninth, or tenth aspect, the MOS transistor in the region of the first memory cell may be:
It comprises a first MOS transistor portion having a high threshold voltage and a second MOS transistor portion having a low threshold voltage, and the MOS transistor in the second memory cell region has a high threshold voltage. And a fourth MO transistor having a low threshold voltage.
The third MOS transistor section has a higher threshold voltage than the first MOS transistor section, and the fourth MOS transistor section has a second MOS transistor section.
It has a higher threshold voltage than the S transistor portion.

As described above, in the region of the first memory cell and the region of the second memory cell, each memory cell is provided with two types of MOS transistor sections having different threshold voltages, so that the first and second memory cells are provided. Four-level information can be stored in the area of two memory cells, and high integration can be achieved without increasing the memory cell area. Claim 1
The semiconductor memory device according to claim 2, wherein the threshold values of the first MOS transistor portion, the second MOS transistor portion, the third MOS transistor portion, and the fourth MOS transistor portion are different from the threshold values of the first MOS transistor portion, the second MOS transistor portion, and the fourth MOS transistor portion. It is characterized in that a difference in voltage is used as a difference in storage state in a memory cell.

According to a thirteenth aspect of the present invention, in a method of manufacturing a semiconductor memory device, a first step of forming a first insulating film on a surface of a semiconductor substrate of one conductivity type, and a second insulating film on the first insulating film A second step of forming a plurality of first element isolation trenches in a predetermined memory cell region in a memory cell array region of a semiconductor substrate by a photolithography method; and The third insulating film is formed on the inner wall of the first isolation trench, so that a region of the one conductivity type semiconductor substrate facing the opening end of the first isolation trench via the third insulating film is gated. A fourth step of forming a shape in which electric field concentration easily occurs when a bias is applied to the electrode; a fifth step of depositing a first buried insulating film to bury the plurality of first element isolation trenches; 1
A sixth step of polishing and planarizing a part of the buried insulating film and a part of the second insulating film, and a plurality of second element isolation trenches in a peripheral circuit region of the semiconductor substrate by photolithography. A seventh step of forming the second insulating film, an eighth step of etching and retreating the portion of the first insulating film exposed in the second element separating groove, and forming an inner wall of the plurality of second element separating grooves. A ninth step of forming a fourth insulating film; and implanting a first impurity ion of one conductivity type into the semiconductor substrate on sidewall portions of the plurality of second isolation trenches to form an impurity layer of one conductivity type. A tenth step of forming, an eleventh step of depositing a second buried insulating film to bury a plurality of second element isolation trenches, a part of the second buried insulating film, and a second insulating film A twelfth step of polishing and planarizing a portion of the first, a thirteenth step of removing the second insulating film, and a first insulating film A fourteenth step of removing a part of the third insulating film, a part of the fourth insulating film, a part of the first buried insulating film, and a part of the second buried insulating film by etching; A fifteenth step of forming a gate insulating film, a sixteenth step of depositing a conductive film over the entire surface, and a step of forming a gate electrode made of a conductive film in the memory cell array region and the peripheral circuit region by photolithography. 17 steps,
An eighteenth step of forming source / drain regions in predetermined memory cell regions and peripheral circuit regions by implanting second impurity ions of another conductivity type.

According to this manufacturing method, a MOS transistor can be formed in a predetermined memory cell region and a peripheral circuit region of the semiconductor memory device according to the first aspect, and the first and second MOS transistors are formed in the memory cell region. By associating different threshold voltages of the two MOS transistor portions with different storage states, two types of information can be stored in one memory cell, and high integration can be achieved without increasing the memory cell area. The device can be realized.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor memory device according to the thirteenth aspect, the fourth step is performed by thermal oxidation. Thus, the fourth step can be easily performed by thermal oxidation. According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor memory device according to the thirteenth aspect, the opening end of the second element isolation trench is formed through the fourth insulating film by the ninth step. Is characterized in that the region of the one conductivity type semiconductor substrate facing the above is shaped so that electric field concentration hardly occurs when a bias is applied to the gate electrode.

According to this manufacturing method, the semiconductor memory device according to claim 3 can be manufactured, and the MO of the peripheral circuit region can be manufactured.
The S transistor becomes a MOS transistor having a single threshold voltage at the end of the active region and at the center of the active region, and a stable circuit operation is performed. According to a sixteenth aspect of the present invention, in the method of the fifteenth aspect, the ninth step is performed by thermal oxidation.

As described above, the ninth step can be easily performed by thermal oxidation. According to a seventeenth aspect of the present invention, in the method of the thirteenth aspect, the position of the surface of the first buried insulating film is lower than the position of the surface of the semiconductor substrate by the fourteenth step. And the position of the surface of the second buried insulating film is lower than the position of the surface of the semiconductor substrate.

According to this manufacturing method, the position of the surface of the first buried insulating film is MO in a predetermined memory cell region.
Since it is lower than the position of the surface of the active region of the S transistor, the channel width of the second MOS transistor formed at the end of the active region is increased, and the operation of the second MOS transistor is stabilized. In the peripheral circuit region, the position of the surface of the second buried insulating film is lower than the position of the surface of the active region of the MOS transistor.
The operation of the S transistor becomes more stable. In the method of manufacturing a semiconductor memory device according to the present invention, a first step of forming a first insulating film on a surface of a semiconductor substrate of one conductivity type, and forming a second insulating film on the first insulating film. A second step, and a first step in the memory cell array region of the semiconductor substrate performed by photolithography.
A third step of forming a plurality of first isolation trenches in the memory cell region, and forming a third insulating film on the inner wall of the plurality of first isolation trenches. A fourth step of forming a region of the one conductivity type semiconductor substrate facing the opening end of the first isolation trench through the insulating film into a shape in which electric field concentration is likely to occur when a bias is applied to the gate electrode; A fifth step of depositing one buried insulating film and filling a plurality of first element isolation trenches, and polishing and planarizing a part of the first buried insulating film and a part of the second insulating film; A sixth step of forming a plurality of second element isolation trenches in a second memory cell region in a memory cell array region of the semiconductor substrate by photolithography, and a plurality of second device isolation grooves in a peripheral circuit region of the semiconductor substrate. A seventh step of forming a third element isolation groove, and the second and third element isolation grooves. An eighth step of etching back the portion of the first insulating film exposed in the isolation groove, and forming a fourth insulation film on inner walls of the plurality of second and third element isolation grooves, A ninth step of forming a region of the one-conductivity-type semiconductor substrate facing the opening end of the second isolation trench through the insulating film into a shape in which electric field concentration is unlikely to occur when a bias is applied to the gate electrode; A tenth step of implanting a first impurity ion of one conductivity type into the semiconductor substrate on a side wall portion of the plurality of third isolation trenches to form an impurity layer of one conductivity type, and a second buried insulating film An eleventh step of depositing a plurality of second and third element isolation trenches and depositing a part of the second buried insulating film and a part of the second insulating film by flattening. Step 12, a thirteenth step of removing the second insulating film, and a part of the first insulating film and the third insulating film A fourteenth step of removing a part of the fourth insulating film, a part of the first buried insulating film and a part of the second buried insulating film by etching, and a part of a region of the second memory cell. A fifteenth step of implanting a second impurity ion of one conductivity type, a sixteenth step of forming a gate insulating film on the entire surface, a seventeenth step of depositing a conductive film on the entire surface, and photolithography. An eighteenth step of forming a gate electrode made of a conductive film in the memory cell array region and the peripheral circuit region by a method, and implanting third impurity ions of another conductivity type to form the first and second memory cell regions and A nineteenth step of forming source / drain regions in the peripheral circuit region.

According to this manufacturing method, a MOS transistor can be formed in the first and second memory cell regions and the peripheral circuit region of the semiconductor memory device according to claim 7,
In the first memory cell area and the second memory cell area, the memory cells in each area are provided with two types of MOS transistor sections. A semiconductor memory device capable of storing information and achieving high integration without increasing the memory cell area can be realized.

According to a nineteenth aspect of the present invention, in the method of manufacturing a semiconductor memory device according to the eighteenth aspect, the fourth step is performed by thermal oxidation. Thus, the fourth step can be easily performed by thermal oxidation. According to a twentieth aspect of the present invention, in the method of manufacturing a semiconductor memory device according to the twelfth aspect, the opening end of the third element isolation groove is formed through the fourth insulating film by the ninth step. Is characterized in that the region of the one conductivity type semiconductor substrate facing the above is shaped so that electric field concentration hardly occurs when a bias is applied to the gate electrode.

According to this manufacturing method, the semiconductor memory device according to the ninth aspect can be formed, and the MO of the peripheral circuit region can be formed.
The S transistor becomes a MOS transistor having a single threshold voltage at the end of the active region and at the center of the active region, and a stable circuit operation is performed. According to a twenty-first aspect of the present invention, in the method of manufacturing a semiconductor memory device according to the eighteenth or twentieth aspect, the ninth step is performed by thermal oxidation.

As described above, the ninth step can be easily performed by thermal oxidation. According to a twenty-second aspect of the present invention, in the method for manufacturing a semiconductor memory device according to the eighteenth aspect, the position of the first buried insulating film surface is lower than the position of the semiconductor substrate surface by the fourteenth step. And the position of the surface of the second buried insulating film is lower than the position of the surface of the semiconductor substrate.

According to this manufacturing method, in the region of the first memory cell, the position of the surface of the first buried insulating film is MO.
Since it is lower than the position of the surface of the active region of the S transistor, the channel width of the second MOS transistor formed at the end of the active region is increased, and the operation of the second MOS transistor is stabilized. In the region of the second memory cell, the position of the surface of the second buried insulating film is MO
Since it is lower than the position of the surface of the active region of the S transistor, the channel width of the fourth MOS transistor formed at the end of the active region is increased, and the operation of the fourth MOS transistor is stabilized. In the peripheral circuit region, the position of the surface of the second buried insulating film is lower than the position of the surface of the active region of the MOS transistor.
The operation of the S transistor becomes more stable.

According to a twenty-third aspect of the present invention, in the method for manufacturing a semiconductor memory device according to the thirteenth or eighteenth aspect, the first insulating film formed in the first step is formed by heating the semiconductor substrate. It is an oxide film formed by oxidation, and the second insulating film formed in the second step is an insulating film having oxidation resistance. As described above, the first insulating film formed in the first step is an oxide film generated by thermally oxidizing a semiconductor substrate, and the second insulating film formed in the second step has an oxidation resistance. When the third insulating film is formed by thermal oxidation, a compressive stress is generated on the surface of the active region of the first memory cell region due to the influence of the second insulating film. Since the oxidation rate is higher in the first element isolation trench than in the active region surface of the cell region, the end of the active region in the first memory cell region has a smaller radius of curvature or has an acute cross-sectional shape. Thus, when a bias is applied to the gate electrode, the electric field concentration tends to occur.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment)
The semiconductor memory device and the method of manufacturing the same according to the embodiment will be described with reference to FIGS. FIG.
1A is a cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention, FIG. 1B is a plan view of a memory cell array region of the semiconductor memory device, and FIG. FIG. 1A is a circuit diagram of a memory cell array region, and FIG.
4B shows a cross section corresponding to the position of the line AA ′. In FIG. 1, 101 is a P-type silicon substrate (semiconductor substrate), 1
05 is a predetermined memory cell area, 106 is a first element isolation groove, 108 is a silicon oxide film embedded in the first element isolation groove 106, 112 and 113 are peripheral circuit areas, 1
14 and 115 are second element isolation trenches, 120 is a P-type impurity layer, 121 is a silicon oxide film buried in the second element isolation trenches 114 and 115, 129 is a gate oxide film made of a silicon oxide film, 135 and 136 are N-type impurity layers,
137 is an interlayer insulating film made of a silicon oxide film, 138 is a contact hole, 139 is a wiring, 143 is a memory cell, 144 is an element isolation region in which the silicon oxide film 108 is embedded in the first element isolation groove 106, and 145 is a predetermined. The word line 146 serving as the gate electrode 132 of the memory cell region 105 is a source region made of an N-type impurity layer 135,
147 is a drain region composed of an N-type impurity layer 135, 1
Reference numeral 48 denotes a bit line serving as a wiring 139 of a predetermined memory cell area 105.

FIG. 2A is a sectional view of a memory cell of the semiconductor memory device (memory cell 143 shown in FIG. 1A).
FIG. 2B is a circuit diagram of the same memory cell, and FIG.
(C) is a voltage-current characteristic diagram of the memory cell (transistor). The cross-sectional views of FIG. 1A and FIG. 2A are shown as perspective views without considering perspective.
In FIG. 2A, reference numeral 156 denotes a first MOS transistor region, 157 and 158 denote second MOS transistor regions, and in FIG. 2B, 159 denotes a first MOS transistor region.
The first MOS transistor formed in the transistor region 156 and the second MOS transistor
7 and 158. In FIG. 2C, reference numeral 161 denotes a voltage-current characteristic of the first MOS transistor 159, and 162 denotes a second MOS transistor.
4 shows voltage-current characteristics of a transistor 160.

The semiconductor memory device of the present embodiment is similar to that of FIG.
As shown in (a), a memory cell array region including a predetermined memory cell region 105 in which a memory cell 143 is formed, another memory cell region (not shown), and a peripheral circuit region that controls the operation of the memory cell 112 and 113. As shown in FIG. 1B, in a predetermined memory cell region 105, the memory cell 143 is
44 are individually separated. Memory cell 143
Is composed of a word line 145, a source region 146, a drain region 147, and a bit line 148 connected to the drain region 147 via a contact hole 138. FIG. 1C is a circuit diagram of the predetermined memory cell region 105 shown in FIG.

The main feature of this embodiment is that, in a predetermined memory cell region 105, an active region of a MOS transistor constituting the memory cell 143, that is, a source region 146, a drain region 147, and a channel region formed therebetween. Of the surface of the P-type silicon substrate 101
The region facing the opening end of the element isolation groove 106 has a small radius of curvature or an acute cross-sectional shape, and the gate electrode 132
Is formed so that electric field concentration easily occurs when a bias is applied. With this configuration, the MOS transistor of the memory cell 143 has two MOS transistor portions that share the gate electrode 132 and have different threshold voltages.

That is, as shown in FIG. 2A, the MOS transistor of the memory cell 143 includes a first MOS transistor region 156 and second MOS transistor regions 157 and 158. As shown by a first MOS transistor 159 and a second MOS transistor
It is represented by a parallel equivalent circuit of the transistor 160. As shown in FIG. 2A, the end of the active region facing the opening end of the first isolation trench 106 has a small radius of curvature or an acute angle in cross section, and an electric field is generated when a bias is applied to the gate electrode 132. The second MOS transistor regions 157 and 158 at the ends of the active region have a shape in which concentration is likely to occur.
Then, the first MOS transistor region 1 in the center of the active region
When a gate voltage is applied to the gate electrode 132 as compared with 56, the electric field concentration is more likely to occur. Here, FIG.
The first MOS transistor 159 and the second M
The common gate electrode 132 of the OS transistor 160
When a certain gate voltage is applied, electric field concentration easily occurs in the second MOS transistor 160, so that a larger drain current is generated than in the first MOS transistor 159, and as shown in FIG. the threshold voltage Vt ₂ of the MOS transistor 160, a first MO
It becomes lower than threshold voltage Vt ₁ of S transistor 159.

The memory cell 143 having such a configuration is arranged at an appropriate position in the memory cell array region according to the contents of the intended program. The structure of a memory cell (not shown) other than the structure of the memory cell 143 arranged in the memory cell array region is, for example,
In the structure of the memory cell 143, the first isolation trench 1
The memory cell 143 may have a structure that is partially different from the memory cell 143 in which the cross section of the edge of the active region facing the opening end of the memory cell 06 is substantially perpendicular, or may have any other memory cell structure. Absent.

Further, this embodiment is characterized in that, in the peripheral circuit regions 112 and 113, the active region of the MOS transistor, that is, the P-type silicon substrate 1 serving as a source region, a drain region and a channel region formed therebetween.
01 second isolation grooves 114 and 115 on the surface
The region facing the opening end (the end of the active region) has a large radius of curvature, for example, an arc-shaped cross section, and a shape in which electric field concentration is unlikely to occur when a bias is applied to the gate electrode 132. The same P-type impurity layer 12 as the silicon substrate 101 is formed at least on the side walls of the trenches 114 and 115.
0 is provided. In this configuration, the end of the active region facing the opening end of the second isolation trenches 114 and 115 is shaped so that electric field concentration is unlikely to occur when a bias is applied to the gate electrode 132, so that the end of the active region is formed. Of the electric field when the gate voltage is applied is alleviated. Further, since the P-type impurity layer 120 is provided on the side walls of the second isolation trenches 114 and 115, the MOS transistor formed at the end of the active region and the central portion of the active region has a threshold voltage and a negative voltage. The current characteristics are also the same and may be regarded as a single MOS transistor.

The method of manufacturing the semiconductor memory device according to the present embodiment configured as described above will be described with reference to process sectional views shown in FIGS. In addition, FIG.
The process cross-sectional view of FIG. 9 also shows a cross-section corresponding to the position of the line AA ′ in FIG. 1B, as in FIG. 1A, and is shown as a perspective view that does not consider perspective. First, in the step shown in FIG. 3, a silicon oxide film 102 is formed on a P-type silicon substrate 101 by thermal oxidation, and then a silicon nitride film 103 is deposited by CVD (FIG. 3A). afterwards,
Using a photoresist 104, a plurality of first element isolation trenches 106 are opened in a predetermined memory cell region 105 of the silicon substrate 101 by photolithography (FIG. 3B), and the photoresist 104 is removed. Then, a silicon oxide film 107 is formed on the inner wall of the isolation trench 106 by thermal oxidation (FIG. 3C). At this time, a region facing the opening end of the first isolation trench 106 on the surface of the P-type silicon substrate 101 which is to be an active region of the MOS transistor in the predetermined memory cell region 105 is a gate electrode 132 (see FIG. 1A). The silicon oxide film 107 is formed so as to have a shape in which electric field concentration easily occurs when a bias is applied in (1).

In the step shown in FIG. 4, a silicon oxide film 108 is deposited on the entire surface by CVD to bury the element isolation trench 106 (FIG. 4A), and then the CMP (Chemi) is performed.
cal Mechanical Polishing)
Then, a part of the silicon oxide film 108 and a part of the silicon nitride film 103 are polished to flatten the surfaces of the silicon oxide film 108 and the silicon nitride film 103 (FIG. 4B).

In the step shown in FIG.
Then, a plurality of second element isolation trenches 114 and 115 are opened in the peripheral circuit regions 112 and 113 by photolithography (FIG. 5A), and the photoresist 111 is removed. The portion of the silicon oxide film 102 exposed to the second element isolation trenches 114 and 115 is etched back (FIG. 5B), and then the silicon oxide film 117 is thermally oxidized to remove the element isolation trenches 114 and 115. 1
15 (FIG. 5C). At this time, the region facing the opening end of the second isolation trenches 114, 115 on the surface of the P-type silicon substrate 101 which becomes the active region of the MOS transistor in the peripheral circuit regions 112, 113 is the gate electrode 132 (FIG. The silicon oxide film 117 is formed so as to have a shape in which electric field concentration hardly occurs when a bias is applied in (2). Further, a P-type impurity ion implantation 119 is performed using a photoresist 118 to form a P-type impurity layer 120 in the silicon substrate 101 on the inner wall of the isolation trenches 114 and 115 (FIG. 5D).

In the step shown in FIG.
8 is removed, and a silicon oxide film 121 is formed on the entire surface by CVD.
Is deposited to bury the element isolation trenches 114 and 115 (FIG. 6A), and then a part of the silicon oxide films 121 and 108 and a part of the silicon nitride film 103 are polished by CMP to form a silicon oxide film. The surfaces of 121 and 108 and the silicon nitride film 103 are flattened (FIG. 6B). Furthermore,
The silicon nitride film 103, then a part of the silicon oxide films 121, 108, 107, and 117 and the silicon oxide film 102 are sequentially removed by wet etching, and the first memory cell region 105, which is the surface of the active region of the MOS transistor, is removed. Active region surface 125 and peripheral circuit region 11
The second active region surface 127 which is the surface of the active regions of the MOS transistors 2 and 113 is exposed, and the position of the surface 126 of the silicon oxide film 108 is lower than the position of the first active region surface 125. The position of the surface 128 of the silicon oxide film 121 corresponds to the second active region surface 12.
7 (FIG. 6 (c)).

In the step shown in FIG. 7, a gate oxide film 129 of a silicon oxide film is formed by thermal oxidation.
(A)) Subsequently, a polysilicon film 130 containing impurities is deposited by CVD (FIG. 7B). Further, a gate electrode 132 is formed by photolithography using the photoresist 131 (FIG. 7C). In the step shown in FIG. 8, after removing the photoresist 131, the photoresist 1 is removed.
33, N-type impurity layers 135 and 136 to be source / drain regions by N-type impurity ion implantation 134.
To form Here, since the gate electrode 132 also serves as a mask for the N-type impurity ion implantation 134, in actuality, FIG.
The gate electrode 132 in the cross section on the line AA ′ of FIG.
There are no N-type impurity layers 135 and 136 immediately below the area, but they are shown as a perspective view as described above.

In the step shown in FIG.
After removing 3, a silicon oxide film is deposited by CVD, and after heat treatment, planarized by CMP to form an interlayer insulating film 137 (FIG. 9A). Then, the N-type impurity layers 135 and 1
After opening a contact hole 138 on the substrate 36, a wiring 139 made of an aluminum film is formed (FIG. 9B). The wiring 139 in the predetermined memory cell region 105 is connected to the bit line 14
It becomes 8.

As described above, the semiconductor memory device of the present embodiment manufactured as described above has the active state of the MOS transistor of the memory cell 143 as shown in FIGS. 1 (a) and 2 (a). The region facing the opening end of the first isolation trench 106 on the surface of the P-type silicon substrate 101 serving as the region is shaped so that electric field concentration is likely to occur when a bias is applied to the gate electrode 132. As shown in b), the first MOS transistor 159 and the second
As shown in FIG. 2C, a voltage-current characteristic 161 of the first MOS transistor and a voltage-current characteristic 162 of the second MOS transistor are represented by a parallel equivalent circuit of the MOS transistor 160. The threshold voltage and the information correspond to each other, that is, the first MOS transistor 159 and the second MOS transistor
When the same gate voltage is applied to the transistor 160,
By turning on one side and not turning on the other side, the storage states "1" and "0" are obtained, so that two types of information can be stored in a single memory cell, and the memory cell area is reduced. High integration can be easily performed without enlargement.

Further, as shown in FIG. 1A, the opening ends of the second isolation trenches 114 and 115 on the surface of the P-type silicon substrate 101 which become active regions of the MOS transistors in the peripheral circuit regions 112 and 113. Is formed so that electric field concentration is unlikely to occur when a bias is applied to the gate electrode 132, and at least the side walls of the second element isolation trenches 114 and 115 have the same shape as the silicon substrate 101. By providing the P-type impurity layer 120, in the peripheral circuit regions 112 and 113, a stable circuit operation by the MOS transistor having a single threshold voltage is performed.

Further, as shown in FIG. 6C, in the predetermined memory cell region 105, the first isolation trench 10 is formed.
Since the position of the surface 126 of the silicon oxide film 108 embedded in the second MOS transistor 6 is lower than the position of the first active region surface 125, the second MOS shown in FIG.
The channel width of the transistor regions 157 and 158 increases, and the second MOS transistor 1 shown in FIG.
The operation of 60 is stabilized.

Further, as shown in FIG. 6C, in the peripheral circuit regions 112 and 113, the second isolation trenches 11 are formed.
Since the position of surface 128 of silicon oxide film 121 buried in 4, 115 is lower than the position of second active region surface 127, MOS transistors provided in peripheral circuit regions 112 and 113 are provided. Operation becomes stable.

Further, as shown in FIG.
Since the silicon oxide film 102 and the silicon nitride film 103 having oxidation resistance are sequentially formed on the silicon nitride film 01, when the silicon oxide film 107 is formed by thermal oxidation, the predetermined memory cell region 105 is affected by the silicon nitride film 103. Compressive stress is generated on the surface of the active region of
Since the oxidation rate is higher in the first element isolation trench 106 than in the active region surface of the first element isolation region 05, the first element isolation trench 106 on the surface of the P-type silicon substrate 101 to be the active region is formed.
Has a small radius of curvature or an acute angle in cross-section, and tends to cause electric field concentration when a bias is applied to the gate electrode 132. In the peripheral circuit regions 112 and 113, as shown in FIG.
After the silicon oxide film 102 facing the second element isolation grooves 114 and 115 is receded by etching, and the silicon oxide film 117 is formed by thermal oxidation, the silicon oxide film 117 on the surface of the P-type silicon substrate 101 serving as an active region is formed. Regions facing the opening ends of the second element isolation grooves 114 and 115 have a large radius of curvature, and have a shape in which electric field concentration hardly occurs when a bias is applied to the gate electrode 132.

In the first embodiment, the gate electrode 132 is formed of the polysilicon film 130 containing impurities. However, a tungsten film, a molybdenum film, a titanium film, a platinum film, a copper film, a tungsten silicide film, a molybdenum film, It may be formed of a single layer film such as a silicide film, a titanium silicide film, a platinum silicide film, or a stacked film of a tungsten silicide film, a molybdenum silicide film, a titanium silicide film or a platinum silicide film and a polysilicon film containing impurities.

The wiring 139 (bit line 148)
Polysilicon film made of aluminum film but containing impurities,
Tungsten film, molybdenum film, titanium film, platinum film, copper film, tungsten silicide film, molybdenum silicide film, titanium silicide film, single layer film such as platinum silicide film, tungsten silicide film, molybdenum silicide film, titanium silicide film or platinum It may be formed of a stacked film of a silicide film and a polysilicon film containing impurities.

In the first embodiment, the P-type silicon substrate 101, the P-type impurity ion implantation 119, the P-type impurity layer 120, the N-type impurity ion implantation 134, and the N-type impurity layers 135 and 136 are used. Reverse each conductivity type to N
Silicon substrate 101, N-type impurity ion implantation 119,
N-type impurity layer 120, P-type impurity ion implantation 134, P
The impurity layers 135 and 136 may be used.

(Second Embodiment) Hereinafter, a semiconductor memory device and a method of manufacturing the same according to a second embodiment will be described with reference to FIGS. FIG.
FIG. 10A is a sectional view of a semiconductor memory device according to a second embodiment of the present invention, FIG. 10B is a plan view of a memory cell array region of the semiconductor memory device, and FIG. FIG. 10A is a circuit diagram of a memory cell array region, and FIG.
Shows a cross section corresponding to the position of line BB 'in FIG. 10B. In FIG. 10, 201 is a P-type silicon substrate (semiconductor substrate), 205 is a first memory cell region, 206 is a first element isolation groove, and 208 is a first element isolation groove 206
, A peripheral region, 213 and 214, a second element isolation groove, 216 and 217 a third element isolation groove, and 222 a P The type impurity layer 223 is a silicon oxide film buried in the second and third element isolation trenches 215 and 216, 217. The reference numeral 235 is a P-type impurity layer formed between source / drain regions serving as channel regions. A gate oxide film 242, 243, 24 made of a silicon oxide film
4 is an N-type impurity layer serving as a source / drain region;
Is an interlayer insulating film made of a silicon oxide film, 246 is a contact hole, 247 is a wiring, 252 is a first memory cell, 253 is a second memory cell, 254 is first and second element isolation trenches 206 and 215. A silicon oxide film 208,
223 is embedded in the element isolation region, and 255 is the first and second element isolation regions.
Word lines 256 formed by the gate electrodes 239 of the memory cell regions 205 and 212
The source regions 257 and 257 of the first and second memory cells 252 and 253 are drain regions of the first memory cell 252 formed of the N-type impurity layer 242, and 258 is a wiring 247 of the first memory cell region 205. A bit line 261 is a drain region of the second memory cell 253 formed of the N-type impurity layer 243, and a bit line 262 is a wiring 247 of the second memory cell region 212.

FIG. 11A is a sectional view of a memory cell of the semiconductor memory device (memory cell 2 shown in FIG. 10A).
52B), FIG. 11B is a circuit diagram of the memory cell 252, and FIG. 11C is a cross-sectional view of the memory cell of the semiconductor memory device (an enlarged view of the memory cell 253 shown in FIG. 10A). 11 (d) is a circuit diagram of the memory cell 253, and FIG. 11 (e) is a voltage-current characteristic diagram of transistors of the memory cells 252 and 253. The cross-sectional views of FIG. 10A and FIGS. 11A and 11C are shown as perspective views without considering perspective. In FIG. 11A, 2
73 is a first MOS transistor region, 274, 275
Is a second MOS transistor region, and FIG.
276 is the first MOS transistor region 27
The first MOS transistor 277 configured in 3 is a second MOS transistor configured in the second MOS transistor regions 274 and 275. In FIG. 11C, reference numeral 278 denotes a third MOS transistor region;
Reference numerals 9 and 280 denote a fourth MOS transistor region. In FIG. 11D, reference numeral 281 denotes a third MOS transistor formed in the third MOS transistor region 278;
282 is a fourth MOS transistor region 279, 280
Is a fourth MOS transistor. FIG.
In (e), 283 is the first MOS transistor 2
76, 284 is the voltage-current characteristic of the second MOS transistor 277, 285 is the voltage-current characteristic of the third MOS transistor 281 and 286 is the fourth M transistor.
14 shows voltage-current characteristics of an OS transistor 282.

The semiconductor memory device of the present embodiment is similar to that of FIG.
As shown in (a), a first memory cell region 205 in which a first memory cell 252 is arranged and a second memory cell 2
It comprises a memory cell array area including a second memory cell area 212 in which 53 is arranged, another memory cell area (not shown), and peripheral circuit areas 213 and 214 that control the operation of the memory cell. As shown in FIG. 10B, in the first memory cell region 205, the first memory cells 252 are individually separated by element isolation regions 254. The first memory cell 252 includes a word line 255,
It comprises a source region 256, a drain region 257, and a bit line 258 connected to the drain region 257 via a contact hole 246. In the second memory cell region 212, the second memory cell 25
3 are individually isolated by element isolation regions 254.
The second memory cell 253 includes a word line 255, a source region 256, a drain region 261, and a drain region 2.
61 and a bit line 262 connected via a contact hole 246. FIG. 10C shows FIG.
The first and second memory cell regions 205 shown in FIG.
FIG. 212 is a circuit diagram of 212.

The first memory cell 252 formed in the first memory cell region 205 has the same structure as the memory cell 143 in the first embodiment, and has the same structure as that of the MOS transistor forming the first memory cell 252. The active region, that is, the region facing the opening end of the first isolation trench 206 on the surface of the P-type silicon substrate 201 which becomes the source region 256, the drain region 257, and the channel region between them has a small radius of curvature or an acute cross section. And the gate electrode 2
39 is shaped so that electric field concentration easily occurs when a bias is applied. With this configuration, the first memory cell 25
The two MOS transistors share the gate electrode 239 and have two MOS transistor portions having different threshold voltages.

That is, the MO of the first memory cell 252
The S transistor includes a first MOS transistor region 273 and second MOS transistor regions 274 and 275 as shown in FIG.
As shown by, the first MOS transistor 276 and the second MOS transistor 277 are represented by a parallel equivalent circuit. As shown in FIG. 11A, the second MOS at the edge of the active region, which has a shape that tends to generate electric field concentration when a bias is applied to the gate electrode 239 facing the opening end of the first isolation trench 206. In the transistor regions 274 and 275, when a gate voltage is applied to the gate electrode 239, electric field concentration is more likely to occur than in the first MOS transistor region 273 in the center of the active region. Here, FIG.
1 (b), common gate electrode 2 of first MOS transistor 276 and second MOS transistor 277
When a certain gate voltage is applied to the transistor 39, the second MOS transistor 277 is liable to cause electric field concentration, so that a drain current larger than that of the first MOS transistor 276 is generated. As shown in FIG. , Second
The threshold voltage Vt ₂ of the MOS transistor 277 is
The threshold voltage Vt _{1 of} the first MOS transistor 276
Lower than.

The second memory cell 253 formed in the second memory cell region 212 is different from the first memory cell 252 in that the active region of the MOS transistor constituting the second memory cell 253, that is, the source region 256, a second element isolation groove 215 on the surface of the P-type silicon substrate 201 to be a drain region 261 and a channel region therebetween.
The region facing the opening end (the end of the active region) has a large radius of curvature, for example, an arc-shaped cross section, and has a shape in which electric field concentration is unlikely to occur when a bias is applied to the gate electrode 239. A P-type impurity layer 235 is formed in a channel region between the region 261.
As described above, the MOS transistor of the second memory cell 253 has such a shape that the electric field concentration hardly occurs when the bias of the active region end is applied to the gate electrode 239, and is smaller than that of the MOS transistor of the first memory cell 252. No,
Since no P-type impurity layer is provided on the side wall of the second isolation trench 215, two MOS transistor portions having different threshold voltages are provided. The MOS transistor of the second memory cell 253 forms a P-type impurity layer 235 in the channel region, and the MOS transistor of the first memory cell 252
The threshold voltage is higher than that of the OS transistor.

That is, the MO of the second memory cell 253 is
The S transistor is composed of a third MOS transistor region 278 and fourth MOS transistor regions 279 and 280 as shown in FIG.
As shown by, it is represented by a parallel equivalent circuit of the third MOS transistor 281 and the fourth MOS transistor 282. The third MOS transistor 281 and the fourth MOS transistor 282 have voltage-current characteristics 285 and 286 shown in FIG.
The threshold voltage Vt ₄ of the transistor 282 is equal to the third M
It becomes lower than the threshold voltage Vt ₃ of the OS transistor 281.

The first and second memory cells 252 and 253 having such a configuration are arranged at appropriate positions in the memory cell array region according to the contents of the intended program. Note that, as described in the first embodiment, the structure of other memory cells (not shown) other than the first and second memory cells 252 and 253 arranged in the memory cell array region is not limited. Such a memory cell structure may be used, and there is no particular limitation.

The MOS transistors formed in the peripheral circuit regions 213 and 214 have the same structure as the MOS transistors in the peripheral circuit regions 213 and 214 in the first embodiment. , The drain region and the channel region therebetween, the region (active region end) facing the opening end of the third element isolation trenches 216 and 217 on the surface of the P-type silicon substrate 201, for example, is formed by increasing the radius of curvature. It is formed in an arc shape so that electric field concentration is unlikely to occur when a bias is applied to the gate electrode 239.
6, 217, at least on the side walls, the same P-type impurity layer 222 as that of the silicon substrate 201 is provided, so that it can be regarded as a MOS transistor having a single threshold voltage.

The method of manufacturing the semiconductor memory device of the present embodiment configured as described above will be further described with reference to FIGS.
This will be described with reference to the process sectional view shown in FIG. The process sectional views of FIGS. 12 to 19 also show cross sections corresponding to the position of the line BB ′ of FIG. 10B, as in FIG. Is shown. First,
In the step shown in FIG. 12, on the P-type silicon substrate 201,
A silicon oxide film 202 is formed by thermal oxidation.
A silicon nitride film 203 is deposited by VD (FIG. 12).
(A)). Thereafter, a plurality of first element isolation trenches 206 are opened in the first memory cell region 205 of the silicon substrate 201 by photolithography using the photoresist 204 (FIG. 12B). After the silicon oxide film 207 is removed by thermal oxidation,
(FIG. 12 (c)).

In the step shown in FIG. 13, a silicon oxide film 208 is deposited on the entire surface by CVD,
(FIG. 13A), and subsequently, a part of the silicon oxide film 208 and a part of the silicon nitride film 203 are polished by CMP to flatten the surfaces of the silicon oxide film 208 and the silicon nitride film 203 (FIG. 13 (b)). In the step shown in FIG. 14, a plurality of second element isolation trenches 215 are opened in the second memory cell region 212 of the silicon substrate 201 by photolithography using a photoresist 211, and the silicon substrate 201 Are formed in the peripheral circuit regions 213 and 214 of FIG.
(FIG. 14A), and after removing the photoresist 211, the silicon oxide film 2 exposed to the second and third isolation trenches 215, 216 and 217 by wet etching.
02 is etched back (FIG. 14B), and then a silicon oxide film 219 is formed on the inner walls of the isolation trenches 215, 216 and 217 by thermal oxidation (FIG. 14).
(C)). Further, a P-type impurity ion implantation 221 is performed using the photoresist 220 to form a P-type impurity layer 222 in the element isolation grooves 216 and 217 (FIG. 14).
(D)).

In the step shown in FIG.
After removing 20, a silicon oxide film 22 is formed on the entire surface by CVD.
Then, the trenches 215, 216 and 217 for device isolation are buried (FIG. 15A), and then a part of the silicon oxide films 208 and 223 and the silicon nitride film 2 are formed by CMP.
03 is polished to flatten the surfaces of the silicon oxide films 208 and 223 and the silicon nitride film 203 (FIG. 15).
(B)). Further, the silicon nitride film 203 and the silicon oxide films 208, 223, and 219 are formed by wet etching.
And the silicon oxide film 202 are sequentially removed, and the first active region surface 227 which is the surface of the active region of the MOS transistor in the first memory cell region 205 and the MOS transistor in the second memory cell region 212 are removed. A second active region surface 229 which is a surface of the active region;
The third active region surface 231 which is the surface of the active regions of the MOS transistors 13 and 214 is exposed,
Silicon oxide film 2 in first memory cell region 205
08 is lower than the position of the first active region surface 227, and the position of the surface 230 of the silicon oxide film 223 is lower than the position of the second active region surface 229 in the second memory cell region 212. In the peripheral circuit regions 213 and 214, the position of the surface 232 of the silicon oxide film 223 is lower than the position of the third active region surface 231 (FIG. 15C).

In the step shown in FIG.
P-type impurity ion implantation 234 is performed using 33 to form a P-type impurity layer 235 in a part of the second memory cell region 212 of the silicon substrate 201. This P-type impurity layer 23
5 is a source / a MOS transistor channel region.
It is formed between the drain regions. In the process shown in FIG.
After removing the photoresist 233, a silicon oxide film 236 to be a gate oxide film is formed by thermal oxidation (FIG. 17).
(A)) Subsequently, a polysilicon film 237 containing impurities is deposited by CVD (FIG. 17B). Further, a gate electrode 239 is formed by photolithography using the photoresist 238 (FIG. 17C).

In the step shown in FIG.
After removing 38, using the photoresist 240, N-type impurity layers 242, 243, and 244 to be source / drain regions are formed by N-type impurity ion implantation 241.
Here, the gate electrode 239 is also used for the N-type impurity ion implantation 24.
In fact, since the mask of FIG.
In the section on the line B ′, N
Type impurity layers 242, 243 and 244 do not exist,
As shown above, it is shown as a perspective view. The P-type impurity layer 235 formed between the source / drain regions
Exist immediately below the gate electrode 239.

In the step shown in FIG.
After removing 40, a silicon oxide film is deposited by CVD,
After the heat treatment, the interlayer insulating film 245 is flattened by CMP (FIG. 19A). Then, the N-type impurity layer 242,
After opening contact holes 246 on 243 and 244, wiring 247 made of an aluminum film is formed.
(B)). First and second memory cell areas 205 and 212
Are the bit lines 258 and 262.
As described above, the semiconductor memory device according to the present embodiment manufactured as described above has the structure shown in FIGS.
As shown in (a), the MOS of the first memory cell 252
P-type silicon substrate 201 serving as an active region of a transistor
The region (active region end) facing the opening end of the first element isolation groove 206 on the surface of FIG. 11), the first MOS transistor 276 and the second MOS transistor 277 are represented by a parallel equivalent circuit, and as shown in FIG. 11E, the voltage-current characteristic 283 of the first MOS transistor 283
And the voltage-current characteristic 284 of the second MOS transistor
Since the threshold voltage and the information correspond to each other, that is, when the same gate voltage is applied to the first MOS transistor 276 and the second MOS transistor 277, one of them is turned on. By not turning on the other, the storage states "11" and "10" are obtained, so that two types of information can be stored in a single memory cell.

Further, as shown in FIGS. 10A and 11C, a second element isolation groove on the surface of the P-type silicon substrate 201 which becomes the active region of the MOS transistor of the second memory cell 253. The region facing the opening end of the gate region 215 is shaped so that electric field concentration is unlikely to occur when a bias is applied to the gate electrode 239, and the source region 256
Since the P-type impurity layer 235 is formed in the channel region between the drain region 261 and the third MOS transistor 281 and the fourth MOS transistor 281 as shown in FIG.
It is represented by a parallel equivalent circuit of the OS transistor 282,
Further, it has a higher threshold voltage than the MOS transistor of the first memory cell 252, and as shown in FIG.
And the voltage-current characteristic 284 of the fourth MOS transistor
Since the threshold voltage and the information correspond to each other, that is, when the same gate voltage is applied to the third MOS transistor 281 and the fourth MOS transistor 282, one of them is turned on. By not turning on the other, the storage states "01" and "00" are obtained, so that two types of information can be stored in a single memory cell.

Therefore, in the present embodiment having the first memory cell region 205 in which the first memory cell 252 is formed and the second memory cell region 212 in which the second memory cell 253 is formed, Can be stored, and high integration can be easily performed without increasing the memory cell area. Further, as shown in FIG. 10A, regions facing the opening ends of the third element isolation trenches 216 and 217 on the surface of the P-type silicon substrate 201 to be the active regions of the MOS transistors in the peripheral circuit regions 213 and 214. Is formed so that electric field concentration hardly occurs when a bias is applied to the gate electrode 239, and the same P-type impurity layer 222 as the silicon substrate 201 is provided on at least the side walls of the third isolation trenches 216 and 217. By doing
In the peripheral circuit regions 213 and 214, a stable circuit operation by the MOS transistor having a single threshold voltage is performed.

Further, as shown in FIG. 15C, in the first memory cell region 205, the first trench 2 for element isolation is formed.
Surface 228 of silicon oxide film 208 embedded in 06
Is made lower than the position of the first active region surface 227, the second MO shown in FIG.
The channel width of the S transistor regions 274 and 275 increases, and the operation of the second MOS transistor 277 shown in FIG.

As shown in FIG. 15C, in the second memory cell region 212, the second isolation trench 2 is formed.
Surface 230 of silicon oxide film 223 embedded in 15
Is lower than the position of the second active region surface 229, the fourth MO shown in FIG.
The channel width of the S transistor regions 279 and 280 increases, and the operation of the fourth MOS transistor 282 shown in FIG.

As shown in FIG. 15C, in the peripheral circuit regions 213 and 214, the third isolation trench 2
Since the position of surface 232 of silicon oxide film 223 buried in 16, 217 is set lower than the position of third active region surface 231, peripheral circuit region 213 is formed.
, And the operation of the MOS transistor disposed at 214 is stabilized.

Since a silicon oxide film 202 and an oxidation-resistant silicon nitride film 203 are sequentially formed on a silicon substrate 201 as shown in FIG. 12, the silicon oxide film 207 is formed by thermal oxidation. Then, a compressive stress is generated on the surface of the active region of the first memory cell region 205 due to the influence of the silicon nitride film 203, and the first element isolation trench 206 is formed more than the surface of the active region of the first memory cell region 205.
Since the inside has a higher oxidation rate, the active region P
First element isolation groove 20 on the surface of mold silicon substrate 201
6 has a small radius of curvature or an acute angle in cross section, so that when a bias is applied to the gate electrode 239, the electric field concentration is likely to occur. The second
Memory cell region 212 and peripheral circuit regions 112 and 11
In FIG. 3, as shown in FIG. 14, after the silicon oxide film 202 facing the second and third element isolation trenches 215, 216, and 217 is receded by etching, a silicon oxide film 219 is formed by thermal oxidation. Therefore, the region facing the opening ends of the second and third isolation trenches 215, 216, and 217 on the surface of the P-type silicon substrate 201 serving as an active region concentrates electric fields when a bias is applied to the gate electrode 239. The shape becomes difficult to occur.

Although the gate electrode 239 is formed of the polysilicon film 237 containing impurities in the second embodiment, a tungsten film, a molybdenum film, a titanium film, a platinum film, a copper film, a tungsten silicide film, a molybdenum film, It may be formed of a single layer film such as a silicide film, a titanium silicide film, a platinum silicide film, or a stacked film of a tungsten silicide film, a molybdenum silicide film, a titanium silicide film or a platinum silicide film and a polysilicon film containing impurities.

The wiring 247 (bit lines 258 and 26)
2) was formed of an aluminum film, but a polysilicon film containing impurities, a tungsten film, a molybdenum film, a titanium film, a platinum film, a copper film, a tungsten silicide film, a molybdenum silicide film, a titanium silicide film, a platinum silicide film, etc. A single-layer film or a stacked film of a tungsten silicide film, a molybdenum silicide film, a titanium silicide film, or a platinum silicide film and a polysilicon film containing impurities may be used.

In the second embodiment, the P-type silicon substrate 201, the P-type impurity ion implantation 221, the P-type impurity layer 222, the P-type impurity ion implantation 234, the P-type impurity layer 235, the N-type impurity ion implantation 241, the N-type impurity layers 242, 243 and 244, but the N-type silicon substrate 201, the N-type impurity ion implantation 221, the N-type impurity layer 222, the N-type impurity ion implantation 234, the N-type impurity layer 235, the P-type impurity Ion implantation 241, P-type impurity layer 2
42, 243 and 244.

[0086]

As described above, according to the present invention, in at least one memory cell region of a plurality of memory cells, the active region (channel region, source region) of the MOS transistor facing the opening end of the isolation trench. Region and the drain region) are shaped so that electric field concentration is likely to occur when a bias is applied to the gate electrode, so that the MOS transistor shares the gate electrode and has a high threshold voltage at the center of the active region. MOS transistor portion and a second MOS transistor having a low threshold voltage formed at an end of an active region having a shape facing an opening end of an element isolation groove and easily causing electric field concentration when a bias is applied to a gate electrode. Section. By associating different threshold voltages of the first and second MOS transistor portions with different storage states, two types of information can be stored in one memory cell. In addition, since one memory cell includes two types of MOS transistor portions, high integration can be achieved without increasing the memory cell area.

In the peripheral circuit region, when a bias is applied to the gate electrode of the active region (channel region, source region and drain region) of the peripheral MOS transistor facing the opening end of the peripheral element isolation groove, electric field concentration occurs. By making the shape difficult, the electric field concentration at the time of applying the gate voltage at the edge of the active region is reduced, and the MOS transistor in the peripheral circuit region is formed by forming an impurity layer of one conductivity type on the side wall of the peripheral device isolation groove. Is a MOS transistor having a single threshold voltage at the end of the active region and at the center of the active region, and a stable circuit operation is performed.

Further, in the memory cell region, the position of the surface of the buried insulating film is made lower than the position of the surface of the active region of the MOS transistor, so that the channel of the second MOS transistor portion formed at the end of the active region is formed. The width is increased, the operation of the second MOS transistor section is stabilized, and the peripheral buried insulating film surface is positioned lower in the peripheral circuit region than the active region surface of the peripheral MOS transistor. The operation of the MOS transistor becomes more stable.

According to the present invention, the plurality of memory cells have at least one first memory cell and at least one second memory cell, and the first memory cell has a first memory cell and a second memory cell.
Active region (channel region, source region and drain region) of the MOS transistor facing the opening end of the device isolation groove of FIG.
Is shaped so that electric field concentration easily occurs when a bias is applied to the gate electrode, so that the MOS transistors in the region of the first memory cell share the gate electrode, and the threshold voltage of the central portion of the active region is reduced. A first MOS transistor portion having a high threshold voltage and a low threshold voltage formed at an edge portion of an active region which is formed at an end portion of an active region which faces an opening end of a trench for element isolation and which is apt to cause electric field concentration when a bias is applied to a gate electrode. MO of 2
And an S transistor section. By associating different threshold voltages of the first and second MOS transistor portions with different storage states, two types of information can be stored in one memory cell.

In the area of the second memory cell,
The active region (channel region, source region, and drain region) of the MOS transistor facing the opening end of the second element isolation trench is shaped so that electric field concentration hardly occurs when a bias is applied to the gate electrode. The concentration of the electric field at the end of the active region at the time of voltage application is reduced, but since the impurity layer is not provided on the side wall of the second isolation trench, the second
MOS transistors in the memory cell region share the gate electrode, and apply a bias to the gate electrode facing the opening end of the isolation trench and the third MOS transistor portion having a high threshold voltage in the center of the active region. And a fourth MOS transistor portion having a low threshold voltage formed at the end of the active region, which has a shape in which electric field concentration is unlikely to occur when the third and fourth MOS transistor portions are formed. By associating different threshold voltages with different storage states, one memory cell can store two types of information. Since the one conductivity type impurity layer is formed in the channel region of the MOS transistor in the region of the second memory cell, the threshold voltage of the third MOS transistor portion and the threshold voltage of the fourth MOS transistor portion are reduced. Will also be higher.

As described above, in the region of the first memory cell and the region of the second memory cell, the memory cell in each region is provided with two types of MOS transistor sections, and the first and second memory cells are provided. Four-level information can be stored in the memory cell region, and high integration can be achieved without increasing the memory cell area. Further, in the peripheral circuit region, the active regions (channel region, source region, and drain region) of the peripheral MOS transistor facing the opening end of the peripheral element isolation groove are formed into a shape in which electric field concentration hardly occurs when a bias is applied to the gate electrode. In this way, the concentration of the electric field at the end of the active region when the gate voltage is applied is reduced, and the one-conductivity-type impurity layer is formed on the side wall of the trench for separating the peripheral element. A MOS transistor having a single threshold voltage is formed at the end of the region and at the center of the active region, so that a stable circuit operation is performed.

Further, in the region of the first memory cell, the position of the surface of the first buried insulating film is made lower than the position of the surface of the active region of the MOS transistor, so that the second region formed at the end of the active region is formed. , The channel width of the MOS transistor section is increased, and the operation of the second MOS transistor section is stabilized. Similarly, in the region of the second memory cell, the position of the surface of the second buried insulating film is
The channel width of the fourth MOS transistor portion formed at the end of the active region is increased by lowering the position of the active region of the S transistor below the surface of the active region.
The operation of the transistor section is stabilized. In the peripheral circuit region, the position of the peripheral buried insulating film surface is changed to the peripheral MOS.
By making the position lower than the position of the surface of the active region of the transistor, the operation of the peripheral MOS transistor becomes more stable.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention, FIG. 1B is a plan view of a memory cell array region of the semiconductor memory device, and FIG. FIG. 3 is a circuit diagram of a memory cell array region.

2A is a sectional view of a memory cell of the semiconductor memory device according to the first embodiment of the present invention, FIG. 2B is a circuit diagram of the memory cell, and FIG. FIG. 4 is a voltage-current characteristic diagram.

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the first embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the first embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the first embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the first embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the first embodiment of the present invention.

FIG. 9 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the first embodiment of the present invention.

10A is a cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention, FIG. 10B is a plan view of a memory cell array region of the semiconductor memory device, and FIG. FIG. 3 is a circuit diagram of a memory cell array region.

11A is a cross-sectional view of a first memory cell of a semiconductor memory device according to a second embodiment of the present invention, FIG. 11B is a circuit diagram of the memory cell, and FIG. Sectional view of a second memory cell of the semiconductor memory device of the second embodiment, (d) is a circuit diagram of the memory cell, and (e) is a voltage-current of the first and second memory cells (transistors). Characteristic diagram.

FIG. 12 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the second embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the second embodiment of the present invention.

FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the second embodiment of the present invention.

FIG. 15 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the second embodiment of the present invention.

FIG. 16 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the second embodiment of the present invention.

FIG. 17 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the second embodiment of the present invention.

FIG. 18 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the second embodiment of the present invention.

FIG. 19 is a process sectional view illustrating the method for manufacturing the semiconductor storage device of the second embodiment of the present invention.

FIG. 20 is a schematic cross-sectional view showing two types of memory cells of a conventional semiconductor memory device.

[Explanation of symbols]

Reference Signs List 101 P-type silicon substrate (one conductivity type semiconductor substrate) 102 Silicon oxide film (first insulating film) 103 Silicon nitride film (second insulating film) 104 Photoresist 105 Predetermined memory cell region 106 First element isolation Groove 107 silicon oxide film (third insulating film) 108 silicon oxide film (first buried insulating film) 111 photoresist 112 peripheral circuit region 113 peripheral circuit region 114 second element isolation groove (peripheral element isolation groove) 115 second element isolation groove (peripheral element isolation groove) 117 silicon oxide film (fourth insulating film) 118 photoresist 119 p-type impurity ion implantation 120 p-type impurity layer (one conductivity type impurity layer) 121 Silicon oxide film (second buried insulating film) 125 First active region surface 126 Surface of silicon oxide film 108 Surface of second active region 128 Surface of silicon oxide film 121 129 Gate oxide film 130 Polysilicon film containing impurities 131 Photoresist 132 Gate electrode 133 Photoresist 134 N-type impurity ion implantation 135 N-type impurity layer (source / Drain region 136 N-type impurity layer (source / drain region of peripheral circuit) 137 Interlayer insulating film 138 Contact hole 139 Wiring 143 Memory cell 144 Element isolation region 145 Word line 146 Source region 147 Drain region 148 Bit line 156 First MOS Transistor area 157 Second MOS transistor area 158 Second MOS transistor area 159 First MOS transistor 160 Second MOS transistor 161 Voltage-voltage of first MOS transistor Flow characteristics 162 Voltage-current characteristics of second MOS transistor 201 P-type silicon substrate (one conductivity type semiconductor substrate) 202 Silicon oxide film (first insulating film) 203 Silicon nitride film (second insulating film) 204 Photo Resist 205 First memory cell region 206 First trench for element isolation 207 Silicon oxide film (third insulating film) 208 Silicon oxide film (first buried insulating film) 211 Photoresist 212 Second memory cell region 213 Peripheral circuit area 214 Peripheral circuit area 215 Second element isolation groove 216 Third element isolation groove (Peripheral element isolation groove) 217 Third element isolation groove (Peripheral element isolation groove) 219 Silicon oxide film ( (Fourth insulating film) 220 Photoresist 221 P-type impurity ion (first impurity ion of one conductivity type) implantation 222 P-type impurity Pure layer (one conductivity type impurity layer) 223 Silicon oxide film (second buried insulating film) 227 Surface of first active region 228 Surface of silicon oxide film 208 229 Surface of second active region 230 Silicon oxide film 223 Surface 231 Third active region surface 232 Surface of silicon oxide film 223 233 Photoresist 234 P-type impurity ions (second impurity ions of one conductivity type) implantation 235 P-type impurity layer 236 Gate oxide film 237 Polysilicon containing impurities Film 238 Photoresist 239 Gate electrode 240 Photoresist 241 N-type impurity ion implantation 242 N-type impurity layer (source / drain region of first memory cell) 243 N-type impurity layer (source / drain region of second memory cell) 244 N-type impurity layer (source / drain region of peripheral circuit) 45 interlayer insulating film 246 contact hole 247 wiring 252 first memory cell 253 second memory cell 254 element isolation region 255 word line 256 source region 257 drain region 258 bit line 261 drain region 262 bit line 273 first MOS transistor region 274 second MOS transistor region 275 second MOS transistor region 276 first MOS transistor 277 second MOS transistor 278 third MOS transistor region 279 fourth MOS transistor region 280 fourth MOS transistor region 281 third MOS transistor 282 Fourth MOS transistor 283 Voltage-current characteristic of first MOS transistor 284 Voltage-current characteristic of second MOS transistor 285 Third M Voltage of the S transistor - current characteristics 286 voltage of the fourth MOS transistor - current characteristic

Claims (23)

[Claims] 1. A semiconductor memory device comprising: a memory cell array region in which a plurality of memory cells are arranged; and a peripheral circuit region, wherein one region of at least one of the plurality of memory cells has one conductive layer. And drain regions formed of an impurity layer of another conductivity type formed on the surface of a semiconductor substrate of a die type, a channel region formed between the source region and the drain region, and a gate insulating film on the channel region. A MOS transistor having a gate electrode formed thereon, a plurality of device isolation trenches arranged by opening the semiconductor substrate on both sides in the channel width direction of the MOS transistor, and an embedding embedded in the device isolation trench An insulating film, and the MOS facing an opening end of the element isolation groove.
A semiconductor memory device wherein a channel region, a source region, and a drain region of a transistor are shaped so that electric field concentration easily occurs when a bias is applied to the gate electrode. 2. The semiconductor memory device according to claim 1, wherein the position of the surface of the buried insulating film is lower than the position of the surface of the channel region, the source region and the drain region of the MOS transistor. 3. A source and drain region comprising an impurity layer of another conductivity type formed on a surface of a semiconductor substrate of one conductivity type and a channel region formed between said source and drain regions in a peripheral circuit region. A peripheral MOS transistor having a gate electrode formed on the channel region with a gate insulating film interposed therebetween, and a plurality of peripheral elements arranged with openings in the semiconductor substrate on both sides of the peripheral MOS transistor in the channel width direction. An isolation layer, an impurity layer of one conductivity type formed on a side wall of the peripheral element isolation groove, and a peripheral buried insulating film embedded in the peripheral element isolation groove. Electric field concentration occurs when a bias is applied to the gate electrode in the channel region, source region, and drain region of the peripheral MOS transistor facing the opening end. The semiconductor memory device according to claim 1, characterized in that the pile shape. 4. The position of the surface of the buried insulating film is lower than the position of the surface of the channel region, source region and drain region of the MOS transistor, and the position of the surface of the peripheral buried insulating film is the position of the channel region, source region and drain of the peripheral MOS transistor. 4. The semiconductor memory device according to claim 3, wherein the position is lower than the position of the surface of the region. 5. The MOS transistor of a memory cell comprises a first MOS transistor having a high threshold voltage and a second MOS transistor having a low threshold voltage. 5. The semiconductor memory device according to 1, 2, 3 or 4. 6. A first MOS transistor section and a second M transistor section.
6. The semiconductor memory device according to claim 5, wherein a difference in threshold voltage from the OS transistor portion is used as a difference in storage state in the memory cell. 7. A semiconductor memory device comprising: a memory cell array region in which a plurality of memory cells are arranged; and a peripheral circuit region, wherein the plurality of memory cells include a first memory cell and a second memory cell. A source region and a drain region each having at least one impurity layer of another conductivity type formed on a surface of a semiconductor substrate of one conductivity type in a region of the first memory cell; MOS transistor having a channel region formed on the channel region and a gate electrode formed on the channel region via a gate insulating film, and the semiconductor substrate is arranged on both sides of the MOS transistor in the channel width direction with openings. A plurality of first element isolation grooves, and a first buried insulating film embedded in the first element isolation grooves. The channel region, the source region, and the drain region of the MOS transistor facing the opening end are shaped so that electric field concentration is likely to occur when a bias is applied to the gate electrode. A source region and a drain region formed of an impurity layer of another conductivity type formed on the surface of the semiconductor substrate; a channel region formed between the source region and the drain region; and a gate insulating film formed on the channel region. A MOS transistor having a gate electrode, a one-conductivity-type impurity layer formed in a channel region of the MOS transistor, and a plurality of semiconductor layers disposed on both sides of the MOS transistor in a channel width direction with openings in the semiconductor substrate. A second trench for element isolation and a second buried insulating film embedded in the second trench for element isolation are provided. A semiconductor device, wherein a channel region, a source region, and a drain region of the MOS transistor facing an opening end of the second isolation trench are shaped so that electric field concentration hardly occurs when a bias is applied to the gate electrode. Storage device. 8. The position of the surface of the first buried insulating film in the region of the first memory cell is lower than the position of the surface of the channel region, source region and drain region of the MOS transistor. 8. The semiconductor memory device according to claim 7, wherein the position of the surface of the second buried insulating film is lower than the position of the surface of the channel region, the source region and the drain region of the MOS transistor. 9. A source region and a drain region formed of an impurity layer of another conductivity type formed on a surface of a semiconductor substrate of one conductivity type, a channel region between the source region and the drain region, and a gate insulating layer. A peripheral MOS transistor having a gate electrode formed on the channel region with a film interposed therebetween, and a plurality of peripheral element isolation trenches arranged with the semiconductor substrate opened on both sides of the peripheral MOS transistor in the channel width direction. An impurity layer of one conductivity type formed on a side wall of the peripheral element isolation groove; and a peripheral buried insulating film embedded in the peripheral element isolation groove. The channel region, the source region and the drain region of the peripheral MOS transistor facing the shape in which electric field concentration hardly occurs when a bias is applied to the gate electrode. The semiconductor memory device according to claim 7, wherein the the. 10. The method according to claim 1, further comprising the steps of:
The position of the surface of the buried insulating film is lower than the position of the surface of the channel region, source region and drain region of the MOS transistor, and the position of the surface of the second buried insulating film in the region of the second memory cell is the channel region of the MOS transistor. , The position of the peripheral buried insulating film surface in the peripheral circuit region is lower than the surface position of the channel region, the source region and the drain region of the peripheral MOS transistor. The semiconductor memory device according to claim 9. 11. A MOS transistor in a region of a first memory cell includes a first MOS transistor portion having a high threshold voltage and a second MOS transistor portion having a low threshold voltage.
The MOS transistor in the second memory cell region includes an S transistor portion, and a third MOS transistor portion having a high threshold voltage and a fourth MOS transistor portion having a low threshold voltage. The third MOS transistor section has a higher threshold voltage than the first MOS transistor section, and the fourth MOS transistor section has a higher threshold voltage than the second MOS transistor section. 9. The method according to claim 7,
11. The semiconductor memory device according to 8, 9, or 10. 12. A difference in threshold voltage between the first MOS transistor unit, the second MOS transistor unit, the third MOS transistor unit, and the fourth MOS transistor unit is defined as a difference in storage state in a memory cell. The semiconductor memory device according to claim 11, wherein the semiconductor memory device is used. 13. A first step of forming a first insulating film on a surface of a semiconductor substrate of one conductivity type; a second step of forming a second insulating film on the first insulating film; A third step of forming a plurality of first isolation trenches in a predetermined memory cell region in a memory cell array region of the semiconductor substrate by etching, and an inner wall of the plurality of first isolation trenches; Forming a third insulating film on the substrate, thereby applying a bias to the gate electrode in the region of the one conductivity type semiconductor substrate facing the opening end of the first isolation trench through the third insulating film. A fourth step of forming a shape in which electric field concentration is likely to occur when the first step is performed; a fifth step of depositing a first buried insulating film to bury the plurality of first element isolation trenches; A sixth step of polishing and planarizing a part of the insulating film and a part of the second insulating film; A seventh step of forming a plurality of second element isolation grooves in a peripheral circuit region of the semiconductor substrate by a photolithography method; and a first step of exposing a portion exposed to the second element isolation grooves. An eighth step of etching and retreating the insulating film, a ninth step of forming a fourth insulating film on the inner wall of the plurality of second element isolation trenches, and the second element isolation A tenth step of implanting a first impurity ion of one conductivity type into the semiconductor substrate in the side wall portion of the trench for forming a one conductivity type impurity layer; An eleventh step of burying the second element isolation trench, a twelfth step of polishing and planarizing a part of the second buried insulating film and a part of the second insulating film, A thirteenth step of removing the second insulating film; and a step of removing the first insulating film and the third insulating film. Partially, the fourth
A fourteenth step of removing a part of the insulating film, a part of the first buried insulating film, and a part of the second buried insulating film by etching; and a fifteenth step of forming a gate insulating film on the entire surface. A sixteenth step of depositing a conductive film on the entire surface, a seventeenth step of forming a gate electrode made of the conductive film in the memory cell array region and the peripheral circuit region by photolithography, and the like. Forming a source / drain region in the predetermined memory cell region and the peripheral circuit region by implanting conductive second impurity ions. 14. The method according to claim 13, wherein the fourth step is performed by thermal oxidation. 15. A ninth step, in which a region of a semiconductor substrate of one conductivity type facing an opening end of a second isolation trench through a fourth insulating film is applied when a bias is applied to a gate electrode. 14. The method for manufacturing a semiconductor memory device according to claim 13, wherein the shape is such that electric field concentration does not easily occur. 16. The method according to claim 15, wherein the ninth step is performed by thermal oxidation. 17. A fourteenth step in which the position of the first buried insulating film surface is lower than the position of the semiconductor substrate surface and the position of the second buried insulating film surface is lower than the position of the semiconductor substrate surface. 14. The method of manufacturing a semiconductor memory device according to claim 13, wherein: 18. A first step of forming a first insulating film on a surface of a semiconductor substrate of one conductivity type; a second step of forming a second insulating film on the first insulating film; A third step of forming a plurality of first isolation trenches in a first memory cell region in a memory cell array region of the semiconductor substrate by etching, and forming a plurality of first isolation trenches; By forming the third insulating film on the inner wall, a bias is applied to the gate electrode from the region of the one conductivity type semiconductor substrate facing the opening end of the first element isolation groove via the third insulating film. A fourth step of forming a shape in which electric field concentration is likely to occur when the voltage is applied; a fifth step of depositing a first buried insulating film to bury the plurality of first isolation trenches; A sixth step of polishing and planarizing a part of the buried insulating film and a part of the second insulating film; Forming a plurality of second isolation trenches in a second memory cell region in a memory cell array region of the semiconductor substrate by photolithography, and forming a plurality of second trenches in a peripheral circuit region of the semiconductor substrate. A seventh step of forming an element isolation groove of No. 3, an eighth step of etching and retreating a portion of the first insulating film exposed to the second and third element isolation grooves, Forming a fourth insulating film on inner walls of the plurality of second and third isolation trenches, and the one conductivity type facing an opening end of the second isolation trench via the fourth insulating film; A ninth step of forming a region of the semiconductor substrate in which the electric field concentration is unlikely to occur when a bias is applied to the gate electrode; Implanting the first impurity ion to form an impurity layer of one conductivity type A tenth step of forming, an eleventh step of depositing a second buried insulating film to bury the plurality of second and third element isolation trenches, and a part of the second buried insulating film. A twelfth step of polishing and planarizing a part of the second insulating film, a thirteenth step of removing the second insulating film, the first insulating film, and the third insulating film Part of the fourth
A fourteenth step of removing a part of the insulating film, a part of the first buried insulating film, and a part of the second buried insulating film by etching, and a part of a region of the second memory cell The second of one conductivity type
A fifteenth step of implanting impurity ions of the following, a sixteenth step of forming a gate insulating film over the entire surface, a seventeenth step of depositing a conductive film over the entire surface, An eighteenth step of forming a gate electrode made of the conductive film in the peripheral circuit region; and implanting a third impurity ion of another conductivity type into the first and second memory cell regions and the peripheral circuit. A nineteenth step of forming a source / drain region in the region. 19. The method according to claim 18, wherein the fourth step is performed by thermal oxidation. In a ninth step, when a bias is applied to a gate electrode of a region of a semiconductor substrate of one conductivity type facing an opening end of a third isolation trench through a fourth insulating film, 19. The method for manufacturing a semiconductor memory device according to claim 18, wherein the shape is such that electric field concentration hardly occurs. 21. The method according to claim 18, wherein the ninth step is performed by thermal oxidation. 22. A fourteenth step in which the position of the first buried insulating film surface is lower than the position of the semiconductor substrate surface and the position of the second buried insulating film surface is lower than the position of the semiconductor substrate surface. 20. The method of manufacturing a semiconductor memory device according to claim 18, wherein: 23. The first insulating film formed in the first step is an oxide film generated by thermally oxidizing a semiconductor substrate, and the second insulating film formed in the second step is 14. An insulating film having oxidation resistance.
19. A method for manufacturing a semiconductor memory device according to item 18.