JP2000077543A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a multilevel-mask ROM which stores information of three or more levels in a memory cell by changing the contact resistances of source/ drain. SOLUTION: A field oxide film 2, isolating the active region of a MOSFET is formed in a region on the surface of a p-type silicon substrate 1, a gate electrode is formed via a gate oxide film, ions are implanted into an arsenic ion implantation layer 5, and the substrate 1 is subjected to heat treatment to form a n-type diffused layer 6. Also, an interlayer insulating film is formed on the surface of the p-type silicon substrate 1, a contact hole is made, ions are implanted, and the substrate 1 is subjected to heat treatment to form a heavily-doped n-type diffused layer. The n-type diffused layer 6 has an impurity concentration higher than that of a heavily-doped n-type diffused layer used in a normal MOSFET. Accordingly, this increases the contact resistance of the bottom portion of a contact hoe into which ions are not implanted after the contact hole is made. Changes in contact resistance or/and contact plug resistance constitutes a multilevel MOSFET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of multi-value storage and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device realizing a multi-value mask ROM and a method of manufacturing the semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device and a method of manufacturing the semiconductor device have been steadily evolving. For example, the storage capacity (the number of bits) of a semiconductor memory has increased fourfold in about three years. Such an improvement in storage capacity has been achieved by reducing the area of a memory cell for storing information. The reason for reducing the memory cell area is that the dimensions of the elements constituting the memory cell have been reduced by a factor of 0.7 in about three years due to advances in microfabrication technology. At present, the minimum design dimension of the device is 0.2 μm or less, and it is about to reach the limit of the photolithography which has been continuously used as a lithography technique for forming such a fine pattern.

Conventionally, binary information is stored in one memory cell. However, as a method other than miniaturization to increase the storage capacity of a semiconductor memory, a so-called multi-value storage memory is used to store information of three or more values. There is. Several memory cells for performing multi-value storage in a mask ROM have been proposed. The most common method is D.A. A. Ri
ch etc. are IEEE Journal of Soli
d-State Circuits, vol. SC-
19, No. 2, pp-174-179, (198
As reported in 4), it is to set three or more threshold voltages in the insulated gate field effect transistor of the memory cell.

To set the threshold voltage of an insulated gate field effect transistor to a different value, see Japanese Patent Application Laid-Open No. 9-2324.
As disclosed in JP-A-49-49, a method of setting the impurity concentration of the channel region to a different value by changing the dose amount of the ion implantation is generally used.

[0005] By the way, as described above, the setting of the threshold voltage based on the dose amount of the ion implantation is performed after the program data is passed from the customer. If the ion implantation process is located as far as possible after the mask ROM manufacturing process, the time from the supply of the program data from the customer to the shipment can be shortened. The ion implantation step for setting the threshold voltage of the insulated gate field effect transistor in a general integrated circuit other than the mask ROM is before the formation of the gate electrode. But mask ROM
In this case, the short-time shipment is performed immediately before forming the metal wiring.

FIGS. 9 and 10 show cross-sectional structures of a semiconductor device in an ion implantation step of a mask ROM. That is, the n-type diffusion layer 8 is formed in the region on the surface of the p-type silicon substrate.
6 and a 200 nm-thickness gate electrode made of polycrystalline silicon is formed on the surface with a gate oxide film 83 interposed therebetween. Further, a 300 nm-thick interlayer insulating film made of a silicon oxide film, PSG or PBPSG is formed on the surface.

In this state, the program waits for program data. When the program data is supplied, ion implantation for setting the threshold voltage of the insulated gate field effect transistor is performed correspondingly. In the case of programming the state 0, after forming a mask made of the first resist, for example, first ion implantation of boron is performed at an energy of 170 keV and a dose of 1 × 10 (e13) cm ⁻² . The threshold voltage of the first insulated gate field effect transistor subjected to the first ion implantation is about 0.8 V.

When the state 1 is programmed similarly after the removal of the first resist, a mask made of the second resist is formed, and then, for example, boron energy 17 is applied.
Second ion implantation is performed at 0 keV and at a dose of 3 × 10 (e13) cm ⁻² . The threshold voltage of the second insulated gate field effect transistor subjected to the second ion implantation is about 1.6 V. When the state 2 is similarly programmed after removing the second resist, after forming a mask made of the third resist, for example, boron is applied at an energy of 170 keV and a dose of 5 × 10 (e13) cm ^−2. Is performed. Third ion implantation is performed.
The threshold voltage of the insulated gate field effect transistor is
It becomes about 2.4V.

When the state 3 is similarly programmed after removing the third resist, a mask made of the third resist is formed and then, for example, boron energy 17 is applied.
Third ion implantation is performed at 0 keV and at a dose of 7 × 10 (e13) cm ⁻² . The threshold voltage of the fourth insulated gate field effect transistor subjected to the fourth ion implantation is about 3.2 V. In this way, insulated gate field effect transistors having four different threshold voltages are formed. FIG. 11 shows an actual threshold voltage distribution of the insulated gate field effect transistor set to four kinds of values. The reason why the center value of the threshold voltage deviates from the set value or has a distribution depends on actual manufacturing variations.

[0010]

However, the above conventional example has two problems. First, four lithography steps are required to form an insulated gate field effect transistor having four different threshold voltages. Therefore, the manufacturing process is long. Second, when the element is miniaturized, the power supply voltage also decreases. When the voltage decreases, it is necessary to narrow the set width of the conventional four threshold voltages from the set width of 0.8V. On the other hand, when the element is miniaturized, the manufacturing variation of the threshold voltage often increases. As a result, the distributions of the four types of thresholds are conventionally completely separated, but the distributions of the thresholds may overlap.

The cause of the process variation is that the impurity distribution of boron introduced into the channel region by ion implantation varies. For example, the distribution of the ion-implanted impurity varies in the depth direction due to the variation in the thickness of the interlayer insulating film and the thickness of the gate electrode. In addition, when the element is miniaturized, the distance between the channel regions of adjacent transistors becomes narrower, and a variation in the impurity distribution in the lateral direction due to the positional deviation of the resist pattern also poses a problem.

According to the present invention, three memory cells can be stored in one memory cell by changing the source / drain contact resistance.
Realizing a multi-value mask ROM that stores information equal to or more than a value;
It is an object to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0013]

In order to solve the above-mentioned problems, the invention according to claim 1 is to change a contact contact resistance value and / or a contact plug resistance value, and to change a drive voltage at the time of ON by a change in the resistance value. It is characterized in that it is configured to include a MOSFET that allows multi-value storage by giving a difference between values.

According to a second aspect of the present invention, there is provided a channel having a constant channel resistance, a source and / or a drain having a changed contact resistance, and a channel for reliably performing multi-value storage. Each configuration of the source diffusion layer resistance value (Rs), the drain diffusion layer resistance value (Rd), the source wiring resistance value (Rws), and the drain wiring resistance value (Rwd), which are smaller than the resistance value and the contact resistance value. And a unit.

According to a third aspect of the present invention, in the second aspect of the present invention, the change in the contact resistance value includes a state 0 when the contact resistance is sufficiently smaller than the channel resistance.
State 1 when the contact resistance is the same as the channel resistance only on the drain terminal D side, State 2 when the contact resistance is the same as the channel resistance only on the source terminal S side, and the state 2 on the drain terminal D side and the source terminal S side In both cases, the difference in the value of the current flowing through each MOSFET is utilized for each of the four types of elements, the state 3 where the contact resistance is substantially equal to the channel resistance.

According to a fourth aspect of the present invention, there is provided a step of forming a field oxide film for separating an active region of a MOSFET in a surface region on a p-type silicon substrate, and forming a field oxide film on a surface of an element region defined by the field oxide film. Forming a gate electrode through the formed gate oxide film, and ion-implanting phosphorus or arsenic into the ion-implanted layer on the surface of the p-type silicon substrate defined by the field oxide film and the gate electrode, and performing heat treatment to perform n-type diffusion. Forming a layer and forming a silicon oxide film, PSG or PBPS on the surface of the p-type silicon substrate.
A step of forming an interlayer insulating film made of G, a step of opening a contact hole so that the surfaces of the n-type diffusion layer and the gate electrode are exposed, and a surface of the p-type silicon substrate where the bottom of the opened contact hole is exposed Ion implantation of phosphorus or arsenic, which is an n-type impurity,
Forming a diffusion layer, and depositing a titanium film as a contact metal layer and a titanium nitride film as a barrier metal layer,
Performing a heat treatment and reacting the titanium film deposited on the surface of the n-type diffusion layer at the bottom of the contact hole with silicon to form a titanium silicide layer.

According to a fifth aspect of the present invention, in the fourth aspect, the ion implantation of phosphorus or arsenic is performed at an energy of 10 keV to 100 keV, preferably 20 keV.
And a dose of 1 × 10 (15) cm ⁻² to 1 × 10 (16) cm ⁻² , preferably 3 × 10 (1
5) The method is characterized by using a condition of cm ⁻² to 5 × 10 (15) cm ⁻² .

The invention according to claim 6 is the invention according to claim 4 or 5.
In the described invention, the heat treatment for forming the n-type diffusion layer and the heat treatment for forming the high impurity concentration n-type diffusion layer are:
It is characterized by a heat treatment for activating impurities by performing a heat treatment at 0 ° C. to 950 ° C.

According to a seventh aspect of the present invention, in the first aspect of the present invention, the heat treatment for forming the titanium silicide layer is a heat treatment at 650 ° C. to 700 ° C. .

[0020] The invention according to claim 8 is the invention according to any one of claims 4 to 7, wherein PSG or P
The interlayer insulating film made of BPSG is a 300 nm-thick interlayer insulating film.

According to a ninth aspect of the present invention, there is provided a step of forming a field oxide film for separating an active region of a MOSFET in a surface region on a p-type silicon substrate, and forming a field oxide film on an element region surface defined by the field oxide film. Forming a gate electrode through the gate oxide film formed, and implanting arsenic ions into the ion implantation layer on the surface of the p-type silicon substrate defined by the field oxide film and the gate electrode, and performing heat treatment to form an n-type diffusion layer. Forming, forming a silicon oxide film, an interlayer insulating film made of PSG or PBPSG on the surface of the p-type silicon substrate, and opening a contact hole so that the surfaces of the n-type diffusion layer and the gate electrode are exposed. After opening contact holes, an amorphous or polycrystalline silicon film containing phosphorus is deposited on a p-type silicon substrate and etched back. To form an n-type silicon plug layer by embedding a silicon film in the contact hole, and ion-implanting phosphorus which is an n-type impurity into the n-type silicon plug layer, and performing heat treatment to form an n-type diffusion layer having a high impurity concentration And depositing a titanium film as a contact metal layer and a titanium nitride film as a barrier metal layer, and then performing a heat treatment to react the titanium film deposited on the surface of the n-type diffusion layer at the bottom of the contact hole with silicon. Forming a titanium silicide layer.

According to a tenth aspect, in the ninth aspect, the ion implantation of phosphorus or arsenic is performed at an energy of 20 keV to 100 keV, preferably 20 keV.
V to 40 keV, dose amount 1 × 10 (15) cm ⁻²
To 1 × 10 (16) cm ⁻² , preferably 2 × 10 (1
5) The method is characterized by using a condition of cm ⁻² to 5 × 10 (15) cm ⁻² .

According to an eleventh aspect of the present invention, in the ninth or tenth aspect, the heat treatment for forming the n-type diffusion layer and the heat treatment for forming the high impurity concentration n-type diffusion layer are performed at 800 ° C. to 1100 ° C. Preferably, the heat treatment is performed at a temperature of 950 ° C. to 1050 ° C. to activate the impurities.

The twelfth aspect of the present invention provides a ninth aspect of the present invention.
In the invention described in any one of the above items 1, the interlayer insulating film made of PSG or PBPSG is an interlayer insulating film having a thickness of 0.2 μm to 1 μm, preferably 0.3 μm to 0.5 μm. .

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention; 1 to 8 show one embodiment of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention.

(First Embodiment) FIGS. 1 and 2 are cross-sectional views of a semiconductor device according to a first embodiment of the present invention. The structure and manufacturing method of the semiconductor device will be described with reference to FIGS. Referring to FIG. 1, a field oxide film 2 for isolating an active region of a MOSFET is formed in a surface region on a p-type silicon substrate 1, and a gate oxide formed on a surface of an element region defined by field oxide film 2 is formed. A gate electrode 4 is formed via the film 3. In an exposed region (or arsenic ion implanted layer 5) of the surface of the p-type silicon substrate 1 defined by the gate oxide film 3 and the gate electrode 4,
Ion implantation of phosphorus or arsenic as an n-type impurity
The n-type diffusion layer 6 is formed by activating impurities by performing a heat treatment at 0 ° C. to 950 ° C.

The ion implantation of phosphorus or arsenic is performed at an energy of 10 keV to 100 keV, preferably 20 keV.
And a dose of 3 × 10 (13) cm ⁻² to 1 × 10 (15) cm ⁻² , preferably 1 × 10 (1
4) Use the condition of cm ⁻² to 5 × 10 (14) cm ⁻² . Next, a silicon oxide film, PSG or PB
A 300 nm-thick interlayer insulating film 7 made of PSG is formed.

Next, a contact hole 8 is opened so that the surfaces of the n-type diffusion layer 6 and the gate electrode 4 are exposed (however, a contact opened on the gate electrode surface is not shown).

Next, phosphorus or arsenic, which is an n-type impurity, is ion-implanted into the surface of the p-type silicon substrate 1 exposed at the bottom of the contact opened by ion implantation using the resist 9 as a mask. By activating the impurities by performing the heat treatment, the high impurity concentration n-type diffusion layer 16 is formed.

The ion implantation of phosphorus or arsenic is performed at an energy of 10 keV to 100 keV, preferably 20 keV.
And a dose of 1 × 10 (15) cm ⁻² to 1 × 10 (16) cm ⁻² , preferably 3 × 10 (1
5) The condition of cm ⁻² to 5 × 10 (15) cm ⁻² is used. This ion implantation differs from the conventional example in that the ion implantation is performed on the surface of the p-type silicon substrate through the thick interlayer insulating film and the gate electrode. And an impurity layer having a desired concentration and distribution can be formed.

Next, referring to FIG. 2, after depositing a titanium film as contact metal layer 21 and a titanium nitride film as barrier metal layer 22, a heat treatment at 650 ° C. to 700 ° C. is performed. As a result, the titanium film (21) deposited on the surface of the n-type diffusion layer at the bottom of the contact hole reacts with silicon to form a titanium silicide layer. The titanium silicide layer formed on the high impurity concentration is used for reducing the contact resistance. Next, after tungsten is deposited and etched back to bury tungsten in the contact hole, an aluminum alloy film serving as a metal wiring is deposited, and the aluminum alloy film, the titanium nitride film and the titanium film are processed to form a laminated metal wiring. 23 are formed.

The n-type diffusion layer 6 formed first is a high impurity concentration n-type diffusion layer 16 used in a normal MOSFET.
Impurity concentration. As a result, the contact resistance at the bottom of the contact hole where the ion implantation is not performed after the contact opening is increased.

FIG. 3 is a diagram showing the relationship between the ion implantation dose after contact opening and the contact resistance at the bottom of the contact. It should be noted that in FIG.
This is because the value differs depending on the ion species material, implantation energy, heat treatment conditions, and the type of contact silicide used. Also, the channel resistance at the time of ON of the MOSFET has a width because of a structure such as a channel length, a channel width, a gate oxide film thickness, a gate terminal, a drain terminal,
This is because the channel resistance varies depending on the threshold voltage or the like. By properly selecting the amount of ion implantation,
It is possible to select a contact resistance at the contact bottom at a value similar to the channel resistance and a value sufficiently smaller than the channel resistance.

(Operation of the Embodiment) FIG. 4 is a circuit diagram showing a structure of a conventional MOS transistor according to the present invention.
FIG. 2 is a diagram showing a structure of a FET and a resistance component inside the FET.
In the MOSFET shown in FIG.
The drain current I in the linear region of the MOSFET when the resistance other than h (V) is sufficiently smaller than the channel resistance
d is represented by the following equation (1).

Id = Cox · μ · (W / L) [(Vgs−Vt) − (1/2) Vds] Vds (1)

Here, the symbols in the above formula (1) mean the following, respectively. Cox is the gate capacitance per unit area, μ is mobility, W is the channel width, L is the channel length, Vgs is the voltage between the gate and the source, Vt is the threshold voltage (varies depending on the voltage between the substrate and the source), Vd
s is a voltage between the drain and the source.

If the voltage condition of (Vgs-Vt) >> Vds is satisfied, the expression (1) is simplified to the following expression (2). Under the voltage condition of equation (2), M in state 0
Since the OSFET has a sufficiently small resistance other than the channel resistance, the drain Id is represented by the above-described equation (1).

Id = Cox · μ · (W / L) (Vgs−Vt) Vds (2)

A conventional multi-valued storage mask ROM is a MOSF
This was realized by changing the threshold voltage of ET. Specifically, when a certain gate voltage is applied, the threshold voltage is changed so that the channel resistance Rch (V) changes. At this time, the other resistors are set to be sufficiently smaller than the channel resistance.

On the other hand, according to the present invention, the channel resistance Rch
(V) is constant, and other resistances such as a source contact bottom contact resistance (Rcsb), a source contact top contact resistance (Rcst), and a drain contact bottom contact resistance (Rcst)
cdb), the contact resistance on the upper surface of the drain contact (Rcd
t) or source contact plug resistance (Rps),
Multi-value storage is realized by changing any of the drain contact plug resistances (Rpd). At this time, there is a feature that includes a condition that the contact resistance to be changed is substantially equal to the channel resistance. In addition, the source diffusion layer resistance (R
s), the resistance of the drain diffusion layer (Rd), the resistance of the source wiring (Rws), and the resistance of the drain wiring (Rwd) are set to values sufficiently smaller than the channel resistance and the contact resistance.

FIG. 5 is a circuit diagram showing four types of elements for distinguishing the four values of states 0, 1, 2, and 3. State 0
Is a case where the contact resistance is sufficiently smaller than the channel resistance. State 1 is a case where only the drain terminal D has the same contact resistance as the channel resistance. State 2
The case where only the source terminal S side has the same contact resistance as the channel resistance. State 3 is a case where the contact resistance is substantially equal to the channel resistance on both the drain terminal D side and the source terminal S side. This is a method utilizing the difference in the value of the current flowing through each MOSFET depending on the above four types of elements.

In the MOSFET in state 1, if the contact resistance on the drain side is substantially the same as the channel resistance, the voltage Vds actually applied to the source and drain at both ends of the channel is about half the value, and the drain current is 0
About half of Assuming that the contact resistance on the source side of the MOSFET in state 2 is substantially equal to the channel resistance, the voltage Vds actually applied to the source and the drain at both ends of the channel becomes about half the value, and furthermore, the voltage applied between the gate and the source. The voltage is also Vgs- (1/2) Vds.
Further, the voltage applied between the substrate and the source is also Vbs- (1 /
2) Vds, and the threshold voltage Vt increases. Therefore, the drain current of the MOSFET in state 2 has a smaller value than in state 1. Assuming that the contact resistance on both the source side and the drain side of the MOSFET in state 3 is substantially equal to the channel resistance, the drain current has a current value that is about half that in state 2.

In this embodiment, four-value storage is realized by performing one ion implantation. However, the present invention is not limited to this, and a plurality of resist patterns are formed to perform ion implantation with different implantation amounts. MOSFE with different current values
By forming T, a program with three or more values may be performed. Further, in this embodiment, the case of the n-channel MOSFET is shown, but a p-channel MOSFET may be used.

(Second Embodiment) FIGS. 6 and 7 are cross-sectional views of a semiconductor device showing a second embodiment of the present invention, and the structure and manufacturing method of the semiconductor device will be described with reference to FIGS. The difference of the second embodiment from the first embodiment is that the plug contact resistance is changed instead of the contact contact resistance. The configuration of the present embodiment will be described below with emphasis on points different from the first embodiment.

The n-type diffusion layer 56 is formed by ion implantation of arsenic and has an energy of 20 keV to 100 keV, preferably 20 keV to 40 keV, and a dose of 1 × 10 5
(15) cm ^-2 to 1 x 10 (16) cm ^-2 , preferably 2 x 10 (15) cm ^-2 to 5 x 10 (15) cm ^-2
Is used. The interlayer insulating film 57 is flattened by a CMP method or the like, and has a thickness of 0.2 μm to 1 μm, preferably 0.3 μm to 0.5 μm. After opening the contact, an amorphous or polycrystalline silicon film containing phosphorus is deposited on the entire surface and etched back to bury the silicon film in the contact hole.

The concentration of phosphorus in the silicon film embedded in the contact ^ranges from 1 × 10 (18) cm ⁻³ to 1 × 10
(20) cm ⁻³ , preferably about 5 × 10 (19) cm ⁻³ to 5 × 10 (19) cm ⁻³ . The phosphorus concentration is selected so that the contact plug resistance becomes substantially equal to the channel resistance. Thereafter, phosphorus ions are implanted into the n-type silicon layer in the desired contact plug using the resist as a mask. 0.4μ contact hole depth
In the case of m, 5 × 10 (15) cm ⁻² to 1 × 10 (16) at an energy of 100 keV and 200 keV, respectively.
An implantation of about cm ^-2 is performed. Then, from 800 ° C to 110
The lamp annealing at 0 ° C., preferably 950 ° C. to 1050 ° C. is performed to activate and diffuse the ion-implanted phosphorus, thereby increasing the impurity concentration of the silicon plug layer, thereby lowering the contact plug resistance. After the formation of the contact metal layer, it is the same as the first embodiment.

FIG. 8 is a diagram showing the relationship between the ion implantation dose and the contact resistance at the bottom of the contact. It should be noted that the numerical values are not plotted on the axis of FIG. 8 because the values differ depending on the ion species material, implantation energy, heat treatment conditions, contact plug diameter, depth, and the like. Also, MOSFET
MOSFET has a wide range of channel resistance when ON
This is because the channel resistance varies depending on the structure such as channel length, channel width, gate oxide film thickness, gate terminal, drain terminal, threshold voltage and the like. By appropriately selecting the amount of ion implantation, the contact plug resistance having a value similar to the channel resistance can be reduced to a value sufficiently smaller than the channel resistance.

In the second embodiment, quaternary storage is realized by performing one ion implantation. But,
The present invention is not limited to this. By forming a plurality of resist patterns and performing ion implantation with different implantation amounts on one of the contact plug layers on the drain side or the source side, by forming MOSFETs with different current values. A program with three or more values may be performed.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0050]

As is clear from the above description, according to the semiconductor device of the present invention, the contact contact resistance value and / or
And the resistance value of the contact plug is changed. Therefore, a MOSFET having a difference in the ON-time drive voltage value is formed by the change in the resistance value, and multi-value storage can be performed using this characteristic.

According to the method of manufacturing a semiconductor device of the present invention,
forming a field oxide film for isolating the active region of the MOSFET in a surface region on the p-type silicon substrate, forming a gate electrode through the gate oxide film formed on the surface of the defined device region; Phosphorus or arsenic is ion-implanted into the ion-implanted layer defined by the gate electrode, and heat treatment is performed to form an n-type diffusion layer. Also, an interlayer insulating film is formed on the surface of the p-type silicon substrate, a contact hole is opened so that the surfaces of the n-type diffusion layer and the gate electrode are exposed, and phosphorus or arsenic is ion-implanted on the exposed surface at the bottom of the contact hole. Implantation and heat treatment are performed to form a high impurity concentration n-type diffusion layer. Further, after depositing a titanium film as a contact metal layer and a titanium nitride film as a barrier metal layer,
Heat treatment is performed, and the titanium film deposited on the surface of the n-type diffusion layer at the bottom of the contact hole reacts with silicon to form a titanium silicide layer.

In the above-described ion implantation, the impurity is implanted into the exposed p-type silicon substrate, and an impurity layer having a desired concentration and distribution can be formed with little variation in one or more manufacturing steps. Also, by appropriately selecting the amount of ion implantation, it is possible to select a contact resistance at the bottom of the contact which is substantially equal to the channel resistance and a value sufficiently smaller than the channel resistance. By this step, it becomes possible to manufacture a semiconductor device capable of multi-value storage with little variation in characteristics.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view 1 of a semiconductor device showing a first embodiment of a semiconductor device and a method of manufacturing the semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the semiconductor device and the method of manufacturing the semiconductor device according to the present invention;

FIG. 3 is a diagram showing the relationship between the ion implantation dose after contact opening and the contact bottom contact resistance.

FIG. 4 is a diagram showing a structure of a MOSFET and a resistance component inside the MOSFET in order to explain a configuration in the present embodiment in comparison with a conventional technique.

FIG. 5 shows 4 for distinguishing the four values of states 0, 1, 2, and 3
FIG. 3 is a circuit diagram showing types of elements.

FIG. 6 is a cross-sectional view 1 of a semiconductor device according to a second embodiment.

FIG. 7 is a sectional view 2 of a semiconductor device according to a second embodiment;

FIG. 8 is a diagram showing the relationship between the ion implantation dose and the contact resistance at the bottom of the contact.

FIG. 9 shows a cross-sectional configuration of a conventional semiconductor device in an ion implantation step of a mask ROM.

FIG. 10 shows a cross-sectional configuration of a conventional semiconductor device in an ion implantation step of a mask ROM.

FIG. 11 shows an actual threshold voltage distribution of a conventional insulated gate field effect transistor set to four types of values.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 p-type silicon substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 arsenic ion implantation layer 6 n-type diffusion layer 7 interlayer insulating film 8 contact hole 9 resist 16 high impurity concentration n-type diffusion layer 21 contact metal layer 22 barrier metal Layer 23 Stacked metal wiring

Claims (12)

[Claims] 1. A MOSFET which changes a contact resistance value of a contact and / or a resistance value of a contact plug and makes a difference in a drive voltage value at the time of ON by the change of the resistance value to enable multi-value storage. A semiconductor device comprising: 2. A channel having a constant channel resistance value, a source and / or a drain having a changed contact resistance value, and the channel resistance value and / or the contact value for reliably performing multi-value storage. The source diffusion layer resistance value (Rs), the drain diffusion layer resistance value (Rd), the source wiring resistance value (Rws), and the drain wiring resistance value (Rwd), each of which is a resistance value smaller than the resistance value, A semiconductor device comprising: 3. The change in the contact resistance value includes: a state 0 when the contact resistance is sufficiently smaller than the channel resistance; a state 1 when the contact resistance is substantially equal to the channel resistance only on the drain terminal D side; State 2 when the contact resistance is almost equal to the channel resistance only on the terminal S side, and State 3 when the contact resistance is equal to the channel resistance on both the drain terminal D side and the source terminal S side. 3. The semiconductor device according to claim 2, wherein a difference in a value of a current flowing through each MOSFET is used for each type of element. 4. An MO on a surface region on a p-type silicon substrate.
Forming a field oxide film for isolating the active region of the SFET; forming a gate electrode via a gate oxide film formed on the surface of the element region defined by the field oxide film; Ion-implanting phosphorus or arsenic into the ion-implanted layer on the surface of the p-type silicon substrate defined by the gate electrode and performing a heat treatment to form an n-type diffusion layer; and a silicon oxide film on the surface of the p-type silicon substrate. , PSG
Alternatively, a step of forming an interlayer insulating film made of PBPSG; a step of opening a contact hole so that surfaces of the n-type diffusion layer and the gate electrode are exposed; Forming a high impurity concentration n-type diffusion layer by ion-implanting phosphorus or arsenic, which is an n-type impurity, into the surface of a silicon substrate, and forming a titanium film as a contact metal layer and a titanium nitride as a barrier metal layer Performing a heat treatment after depositing the film, and reacting the titanium film deposited on the surface of the n-type diffusion layer at the bottom of the contact hole with silicon to form a titanium silicide layer. Manufacturing method of a semiconductor device. 5. The ion implantation of phosphorus or arsenic is performed at an energy of 10 keV to 100 keV, preferably 20 keV.
From keV to 40 keV, dose amount 1 × 10 (15) c
m ⁻² to 1 × 10 (16) cm ⁻² , preferably 3 × 10
5. The method of manufacturing a semiconductor device according to claim 4, wherein a condition of (15) cm ^-2 to 5 × 10 (15) cm ^-2 is used. 6. The heat treatment for forming the n-type diffusion layer and the heat treatment for forming the high impurity concentration n-type diffusion layer are performed by 8
6. The method of manufacturing a semiconductor device according to claim 4, wherein the heat treatment is performed at a temperature of from 00.degree. C. to 950.degree. C. to activate the impurities. 7. The method for manufacturing a semiconductor device according to claim 4, wherein the heat treatment for forming the titanium silicide layer is a heat treatment at 650 ° C. to 700 ° C. 8. The method according to claim 4, wherein the interlayer insulating film made of PSG or PBPSG is an interlayer insulating film having a thickness of 300 nm. 9. An MO on a surface region on a p-type silicon substrate
Forming a field oxide film for isolating the active region of the SFET; forming a gate electrode via a gate oxide film formed on the surface of the element region defined by the field oxide film; Arsenic is ion-implanted into the ion-implanted layer on the surface of the p-type silicon substrate defined by the gate electrode, and heat treatment is performed to form an n-type diffusion layer; and a silicon oxide film and PSG are formed on the surface of the p-type silicon substrate.
Alternatively, a step of forming an interlayer insulating film made of PBPSG; a step of opening a contact hole so that the surface of the n-type diffusion layer and the surface of the gate electrode are exposed; Depositing a crystalline silicon film on the p-type silicon substrate and performing an etch-back to bury the silicon film in the contact hole to form an n-type silicon plug layer; A step of ion-implanting phosphorus and performing a heat treatment to form an n-type diffusion layer having a high impurity concentration; and depositing a titanium film as a contact metal layer and a titanium nitride film as a barrier metal layer, and then performing a heat treatment to form a contact. Reacting a titanium film deposited on the surface of the n-type diffusion layer at the bottom of the hole with silicon to form a titanium silicide layer; The method of manufacturing a semiconductor device, characterized in that made the. 10. The ion implantation of arsenic at an energy of 20 keV to 100 keV, preferably 20 keV to 40 keV, and a dose of 1 × 10 (15) cm ⁻² to 1 × 10 (16) cm ⁻² , preferably 2 × 10 (15)
10. The method for manufacturing a semiconductor device according to claim 9, wherein a condition of cm ⁻² to 5 × 10 (15) cm ⁻² is used. 11. The heat treatment for forming the n-type diffusion layer and the heat treatment for forming the high impurity concentration n-type diffusion layer are performed at a temperature of 800 ° C. to 1100 ° C., preferably 950 ° C. to 1050 ° C. 11. The method for manufacturing a semiconductor device according to claim 9, wherein the heat treatment is for activating the semiconductor device. 12. The interlayer insulating film made of PSG or PBPSG is an interlayer insulating film having a thickness of 0.2 μm to 1 μm, preferably 0.3 μm to 0.5 μm. 13. The method for manufacturing a semiconductor device according to claim 1.