JP2000031798A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable delay circuit that can conduct a function test of a selector even when a delay by a logic gate is small without increasing number of components of the circuit. SOLUTION: An OR circuit 2 connects to an input terminal A of a selector 2 and an OR circuit 23 connects to an input terminal B. An input signal of an input terminal IN and a signal applied to a test signal input terminal test1 are given to the OR circuit 22. An output signal from a delay circuit 21 delaying the input signal and a signal applied to a test signal input terminal test2 are given to the OR circuit 23. A low level voltage is fed to the terminals test1, test2 normally and a high level voltage is applied to the terminals test1, test2 when a function of the selector is tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a variable delay circuit, and more particularly to a variable delay circuit having a configuration in which a delay time is generated by a logic gate and the delay time of an output signal can be set by the number of the logic gates used.

[0002]

2. Description of the Related Art A variable delay circuit is configured such that a delay time changes in accordance with the number of stages of a logic gate (Gate) through which a signal passes.
Delay time can be lengthened.

FIG. 4 shows a configuration of a conventional variable delay circuit.
A gate circuit 1 is connected to the input terminal IN, and an output terminal thereof is connected to an input terminal B of a selector (Selector) 2. The selector 2 has input terminals A and S in addition to the input terminal B. The input terminal A is connected to a signal input terminal S ₀ to which a selection signal is input, and the input terminal B is connected to an output terminal of the gate circuit 1. The input terminal A of the selector 3 is connected to the output terminal of the selector 2. The selector 3 also has three input terminals A, B, and S, and the input terminal S
It is connected to the signal input terminal S _1. Gate circuits 4 and 5 for delaying the output signal of the selector 2 are inserted in series between the input terminals A and B of the selector 3 to delay the passing signal by two stages. The input terminal A of the selector 6 is connected to the output terminal of the selector 3. The selector 6 also has input terminals A, B, and S, and gate circuits 7, 8, 9, and 10 are connected in series between the input terminals A and B. As a result, the selector 3 performs four-stage delay processing. Input terminal S of the selector 6 is connected to a signal input terminal S _2. Selector 6
Is the output terminal OUT of the variable delay circuit 40.

In the above configuration, the signal input terminals S ₀ ,
When the selection signal is not input to S ₁ and S ₂ , the input terminal A is selected in each of the selectors 2, 3 and 6, and the input signal applied to the input terminal IN passes through the selectors 2, 3 and 6. That is, the input signal is not delayed. For example, when a signal is applied only to the signal input terminal S _0, an input terminal B of the selector 2 is selected, the output of the gate circuit 1 is captured. Therefore, the output signal of the selector 6 is a signal that has been delayed by one stage by the gate circuit 1. Also, if only the selected signal to the signal input terminal S ₂ is applied, the input signal applied to the input terminal IN, and passed through the selector 2,3, delay processing of the four stages by the gate circuit 7 to 10 is applied Is output from the selector 6. The selector 3 operates similarly. As described above, in the variable delay circuit 40 shown in FIG.
₀ , S ₁ , and S ₂ according to the state of the selection signal input thereto.
No delay or 1st, 2nd, 3rd, 4th, 5th, 6th
The delay amount of any one of the seven stages can be set.
Thus, in the configuration of FIG. 4, the signal input terminals S ₀ ,
In response to the selection signal applied to S ₁ and S ₂ , the input terminal IN
Since the number of stages of the gate circuit through which the signal input to the gate circuit passes can be set, the delay time of the variable delay circuit 40 can be changed.

FIG. 5 shows a detailed configuration of each selector used in FIG. The configuration shown here is a circuit configuration common to the selectors 2, 3, and 6. The multiple transistors
In each case, the NPN type is used. Transistor 11
And 12 form an ECL (Emitter Coupled Logic) circuit. The collector of the transistor 11 is directly connected to the higher power supply, and the collector of the transistor 12 is connected to the lower power supply via the resistor 13. The transistor 1 is connected to the emitters of the transistors 11 and 12 which are connected in common.
4 is connected, and its base is connected to the signal input terminal S.
(S ₀ , S ₁ , or S ₂ ). A constant current source 15 is connected between the emitter of the transistor 14 and the lower power supply. The base of the transistor 11 is connected to the input terminal A, and the first reference voltage VR ₁ is applied to the base of the transistor 12. The collector of the transistor 12 is connected to the output terminal OUT. The transistors 16 and 17 also form an ECL circuit. The collector of the transistor 16 is connected to the collector of the transistor 12, and the collector of the transistor 17 is connected to the higher power supply. Reference voltage VR ₁ first to the base of the transistor 16 is applied, the base of the transistor 17 is connected to the input terminal B. Transistor 16
The collector of the transistor 18 is connected to the emitters of the transistors 17 and 17, the second reference voltage VR ₂ is applied to the base thereof, and the emitter is connected to the emitter of the transistor 14.

Here, the input terminals A and B normally have a high level of about -0.8 V and a low level of -1.
A voltage of about 4 V is applied. In addition, the selection signal of the signal input terminal S is smaller than the voltage applied to the input terminals A and B by-
A voltage shifted by about 0.8 V, that is,
A voltage of about 1.6 V and a low level of about -2.2 V is applied. The reference voltage VR ₁ is an input terminal A, an intermediate voltage between the high level and the low level applied to the B -1.1
The order of V is applied, the reference voltage VR ₂ is an intermediate voltage between the high level and the low level applied to the selected signal -1.9
About V is applied.

Next, the operation of the selector of FIG. 5 will be described. The ECL circuit compares the base potentials of a pair of transistors whose emitters are connected to each other, and outputs a logical level when a current flows to the higher base potential. Here, the value of the current flowing through the constant current source 15 is I, and the resistance 13
Let us consider the case where the value of R is R. First, when the selection signal applied to the signal input terminal S is at a high level, when the base potentials of the transistors 14 and 18 are compared, the base potential of the transistor 14 is higher than the base potential of the transistor 18. Flow through 14. Next, comparing the base potentials of the transistors 11 and 12, when a high-level voltage is input to the input terminal A, the current I flows on the transistor 11 side. Therefore, the current I flows through the path from the higher power supply → the transistor 11 → the transistor 14 → the constant current source 15. in this case,
Since no current flows through the resistor 13, a voltage drop does not occur, and the potential of the output terminal OUT becomes almost the value of the higher power supply (high-level output).

On the other hand, when a low level is input to the input terminal A, the current I flows through the transistor 12. Therefore, the current I is from the high-order power supply → the resistor 13 → the transistor 12
The current flows through the path from the transistor 14 to the constant current source 15. In this case, the potential of the output terminal OUT has a voltage drop due to the resistance 13 and the current I, and has a value of [voltage of the high-order power supply−I × R] (low-level output). At this time, since no current flows through the transistors 16 and 17, the voltage at the output terminal OUT does not change due to the voltage applied to the input terminal B. As described above, when a high level is input to the input signal terminal S, the output level of the selector becomes logically the same as the signal level applied to the input terminal A.

Next, when the applied signal to the input signal terminal S is at a low level, comparing the base potentials of the transistors 14 and 18, when the base potential of the transistor 18 is higher than the base potential of the transistor 14, the current I becomes It will flow through the transistor 18. Next, comparing the base potentials of the transistors 16 and 17, when a high level is input to the input terminal B, the current I
Flow through 7. Therefore, the current I flows through the path from the higher power supply → the transistor 17 → the transistor 18 → the constant current source 15. In this case, since no current flows through the resistor 13,
The potential of the output terminal OUT is substantially equal to the value of the higher power supply (high-level output). On the other hand, when a low level is input to the input terminal B, the current I flows through the transistor 16. Therefore, the current I flows through the path of the higher power supply → the resistor 13 → the transistor 16 → the transistor 18 → the constant current source 15. In this case, the potential of the output terminal OUT causes a voltage drop due to the resistance 13 and the current I, and the voltage [the voltage −I
× R] (low-level output). At this time, since the current I does not flow through the transistors 11 and 12, the output voltage of the output terminal OUT does not change due to the voltage applied to the input terminal A. As described above, when a low level is input to the input signal terminal S, a level that is logically the same as the level applied to the input terminal B is output from the output terminal OUT.

Next, the operation of the variable delay circuit 40 shown in FIG. 4 will be described in detail. For example, when any of the selectors 2, 3, and 6 selects a signal that does not pass through the gate circuit (that is, selects the input terminal A), the variable delay circuit 40 in this case is selected.
Delay time tpd0 (synchronization circuit 4 without gate circuit)
0 delay time) is the delay time of each selector
Assuming pds, tpd0 = tpds + tpds + tpds = 3 × tpds

When the signal passed through the gate circuit 1 is applied only to the selector 2 (that is, when the input terminal B is selected), the delay time tpd1 of the variable delay circuit 40 (when one gate circuit is used) Is the delay time of one stage of the gate circuit tpdgate
Then, tpd1 = tpdgate + 3 × tpds = tpd0 + tpdgate.

Next, the gate circuits 4 and 5 are connected to the selector 3 only.
Delay circuit 40 when a signal passed through
Is the delay time tpd2 (the delay time of the synchronization circuit when passing through the two gate circuits) tpd2 = tpds + 2 × tpdgate + tpds + tpds = tpd0 + 2 × tpdgate

Further, a delay time tpd3 (in the case where the input terminal B of the selector 3 and the input terminal B of the selector 6 are selected) when a signal passed through a gate circuit is applied to the selectors 2 and 3 (three gate circuits) ) Is as follows. tpd3 = tpdgate + tpds + 2 × tpdgate + tpds + tpds = tpd0 + 3 × tpdgate

When only the selector 6 selects a signal passing through the gate, the delay time tpd4 of the signal passing through the four gate circuits (the synchronization circuit 4 when passing through the four gate circuits).
0 delay time) is as follows. tpd4 = tpds + tpds + tpds + 4 × tpdgate = tpd0 + 4 × tpdgate

Further, when all of the selectors 5, 6, 7 select the input terminal B, the delay time tpd7 of the signal passing through the seven gate circuits is tpd7 = tpdgate + tpds + 2 × tpdgate + tpds + tpds + 4 × tpdgate = tpd0 + 7 × tpdgate, and the delay time changes in eight stages (including no delay) with the delay time tpdgate for one gate as the minimum unit. At this time, since tpdgate needs to be the same, it is desirable to unify the gate circuits to the same specification.

The variable delay circuit 40 having the above configuration is merely a buffer configuration as a whole, and even if the selector is faulty, it is difficult to find out on a test. For example, even if the selector 2 fails and a state occurs in which only a signal that does not pass through the gate circuit 1 can be selected, the delay time is tpdgate.
Although it differs only by the amount, it does not change as a whole circuit function, so it is difficult to determine a good / defective product only by a functional test. Therefore, conventionally, in an LSI having a built-in variable delay circuit, the delay time is measured separately from the function test,
Non-defective / defective products were determined. However, when the delay time of one gate is small, such as an ECL circuit, the delay time tpdgate of one gate may exceed the resolution of the delay time measurement of the LSI tester. In this case, at present, the LSI tester has no means for measuring, and a defective product may be determined as a non-defective product.

As a solution to such a problem, there is a variable delay circuit disclosed in Japanese Patent Application Laid-Open No. 1-223823 (JP-B-3-81328), which measures the actual delay amount of an output signal without measuring the delay amount. The operation status of the circuit can be checked only by observing the logic.

[0018]

However, according to the conventional variable delay circuit, if the delay time of the logic gate is smaller than the resolution of the LSI tester, the operation cannot be confirmed. The reason is that the variable delay circuit using the logic gate and the selector as a whole is merely a buffer, so that a normal function test cannot determine good or bad.

Further, according to the variable delay circuit disclosed in Japanese Patent Application Laid-Open No. 1-223223, it is necessary that all delay gates of the selector be exclusive OR (Exclusive OR). There is a problem that the number increases. Further, even when only a part of the circuit is to be tested, it is necessary to unify all the circuit elements in an exclusive-OR manner in order to adjust the delay time.

Therefore, an object of the present invention is to provide a variable delay circuit which can perform a function test of a selector without increasing the number of elements used, even when the delay of a logic gate is small.

[0021]

In order to achieve the above object, the present invention has, as a first feature, a first input terminal for inputting an input signal and a predetermined delay time for the input signal. In a variable delay circuit constituted by a selector having a second input terminal input via a logic gate and an output terminal for outputting the input signal input to the first or second input terminal by a selection signal. A first input terminal for inputting the input signal, a second input terminal for inputting a first test signal for functionally testing the selector, and a selector for inputting the input signal or the first test signal to the selector. A first OR circuit having an output terminal for outputting to the first input terminal, a first input terminal for inputting the input signal that has passed through the logic gate, and a second circuit for testing the selector function. A second input terminal for inputting a test signal of the second of said logic the input signal gate passed through or the said second test signal selector
And a second OR circuit having an output terminal for outputting to an input terminal of the variable delay circuit.

In order to achieve the above object, the present invention has, as a second feature, a first input terminal for inputting an input signal and a second input terminal for inputting a first test signal. A first OR circuit having an output terminal for outputting the input signal or the first test signal, and a first input terminal for inputting the input signal passed through a logic gate having a predetermined delay time. A second OR circuit having a second input terminal for inputting a second test signal, and an output terminal for outputting the input signal or the second test signal passed through the logic gate; A first input terminal connected to the output terminal of the first OR circuit, a second input terminal connected to the second OR circuit, and the first or the second terminal in response to a selection signal input to a selection terminal. Signal input to the second input terminal A first selector having an output terminal for outputting, a first input terminal connected to the output terminal of the first selector, and an output terminal of the first selector having the same delay as the logic gate. A second input terminal connected via a first predetermined number of logic gates having time, and the first input terminal in response to a selection signal input to a selection terminal;
Alternatively, a second selector having an output terminal for outputting a signal input to a second input terminal; a first input terminal connected to the output terminal of the second selector;
A second input terminal connected to the output terminal of the selector via a second predetermined number of logic gates having the same delay time as the logic gate, and a selection signal input to the selection terminal. A third selector having an output terminal for outputting a signal input to the first or second input terminal;
Is provided.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the variable delay circuit according to the present invention. In the figure, the same reference numerals are used for those that are the same as those in FIG. 4, and thus redundant description will be omitted below. Input terminal I
N and an input signal terminal S, and two test signal input terminals (
test1, test2). Input terminal IN
Is connected to an OR circuit 22 to the input terminal IN and the test signal input terminal test1, and an OR circuit 23 is connected to the output terminal of the delay circuit 21 and the test signal input terminal test2. ing. The output terminal of the OR circuit 22 is connected to the input terminal A of the selector 2, and the output terminal of the OR circuit 23 is connected to the input terminal B. The input terminal S of the selector 2 is connected to the input signal terminal S _0.

[0024] In FIG. 1, when the input signal terminal S ₀ is not applied the selection signals, the selector 2 is an input terminal A is selected and the output signal of the OR circuit 22 is taken in the input terminal A. In this case, since the OR circuit 22 performs a logical sum,
An output signal is generated in the OR circuit 22 regardless of the presence or absence of a signal at the test signal input terminal test1. The delay time tpd0 of the variable delay circuit 20 in this case is expressed by the following equation, where tpdOR is the delay time of the OR circuit 22 (the delay time of the same tpdOR in the OR circuit 23) and tpds is the delay time of the selector 2. tpd0 = tpdOR + tpds

On the other hand, when the selection signal is applied to the input signal terminal S ₀ , the selector 2 selects the input terminal B, and the signal delayed by the delay circuit 21 is input to the input terminal B of the selector 2 via the OR circuit 23. Is input to The delay time tpd1 of the variable delay circuit 20 in this case is expressed by the following equation, where the delay time of the delay circuit 21 is tpdd. tpd1 = tpdd + tpdOR + tpds = tpd0 + tpdd Therefore, in this operation state, the delay time of the output signal can be changed by the delay time of the delay circuit 21 (tpdd). If it is desired to perform the same operation as in the related art, the voltages input to the test signal input terminals test1 and test2 of the two OR circuits 22 and 23 may be fixed to a low level.

Next, at the time of the function test of the selector 2, the input terminal IN is fixed to a low level voltage. Further, a high-level voltage is input to the test signal input terminal test1,
A low level voltage is input to the test signal input terminal test2. As a result, the test signal input to the test signal input terminal test1 is input to the input terminal B of the selector 2, and a high level voltage is output to the output terminal OUT of the selector 2. This state is confirmed by a not-shown inspection device (measurement device). Next, contrary to the above, the test signal input terminal t
After a low level voltage is input to test1 and a high level voltage is input to test signal input terminal test2, the selection signal of selector 1 is switched to output a signal passed through test2, and a high level voltage is output to output terminal OUT. If it is confirmed that the selector 1 has been operated, the selector 1 is operating normally.

FIG. 2 shows a second embodiment of the variable delay circuit according to the present invention. In the present embodiment, as in the variable delay circuit 40 of FIG. 4, the maximum number of delay stages is seven, and the same reference numerals are used for those having the same or the same functions as those in FIG. Therefore, a duplicate description will be omitted below. Input terminal _IN, S 0, test1, te
The configuration of each of the st2 and the selector 2 is the same as described in FIG. 1, but the gate circuit 1 described in FIG. The configuration from the selector 2 to the selector 6 is exactly the same as in FIG.

Next, the operation of the variable delay circuit 30 shown in FIG. 2 will be described. First, a case where the circuit is used as a normal variable delay circuit will be described. In this case, the test signal input terminal te
A low level signal is input to st1 and test2. In this state, since the OR circuits 22 and 23 take a logical sum, they function as a buffer circuit that transmits an input signal having a high-level voltage input to one input terminal to the selector 2 as it is. Therefore, the operation when the voltages of the test signal input terminals test1 and test2 are at the low level is the same as that of the conventional variable delay circuit 40 described above.

For example, when a selection signal for selecting the input terminal A is applied to each of the selectors 2, 3, and 6, the signal passed through the gate circuit is not input to any of the selectors, and the delay time of each of the selectors Only the operation that is given. That is, assuming that the delay time in the OR circuit 22 is tpdOR and the delay time in each selector is tpds, the delay time tpd0 of the variable delay circuit 30 in this case is expressed by the following equation. tpd0 = tpdOR + tpds + tpds + tpds = tpdOR + 3 × tpds

When only the selector 2 selects the input terminal B and the selectors 3 and 6 continue to select the input terminal A, if the delay time of the gate circuit for one stage is tpdgate, then the gate circuit 1 The delay time tpd1 is expressed by the following equation. tpd1 = tpd0R + tpdgate + 3 × tpds = tpd0 + tpdgate

Next, when the selectors 2 and 3 select the input terminal A and only the selector 6 selects the input terminal B,
The delay time tpd2 of the variable delay circuit 30 at this time is expressed by the following equation. tpd2 = tpdOR + tpds + 2 × tpdgate + tpds + tpds = tpd0 + 2 × tpdgate

Further, when the selectors 3 and 6 select the input terminal B and the selector 2 selects the input terminal A, the delay time tpd3 of the variable delay circuit 30 is expressed by the following equation. tpd3 = tpdOR + tpdgate + tpds + 2 × tpdgate + tpds + tpds = tpd0 + 3 × tpdgate

When the selectors 2 and 3 select the input terminal A and only the selector 6 selects the input terminal B, the delay time tpd4 of the variable delay circuit 30 is expressed by the following equation. tpd4 = tpdOR + tpds + tpds + tpds + 4 × tpdgate = tpd0 + 4 × tpdgate

Next, when each of the selectors 2, 3, and 6 selects the input terminal B, the delay time tpd7 of the variable delay circuit 30 is tpd7 = tpdOR + tpdgate + tpds + 2 × tpdgate + tpds + tpds + 4 × tpdgate = tpd0 + 7 × tpdgate, which is a variable delay circuit capable of changing the delay time in eight steps using tpdgate as the minimum unit.

Next, a case where a function test of the selector is performed will be described. First, the input terminal IN of the variable delay circuit 30
A low-level voltage is input to each of the test signal input terminals test1 and test2 as an initial setting value. Selection signal applied to the signal input terminal S ₀ may but be a signal for selecting one of the input terminals A or B,
Here, it is assumed that the input terminal A is selected. next,
A high-level voltage is input to the test signal input terminal test1. If the selector 2 operates normally, the output voltage of the selector 2 changes to the high level.
Also changes to the high level. Therefore, if the input terminal B of the selector 2 cannot be selected for some reason, the voltage of the output terminal OUT does not change, so that it can be seen that the selector 2 is abnormal. In this manner, a function test from the input terminal A side of the selector 2 can be performed.

Next, again, the input terminal IN of the variable delay circuit 30 and the test signal input terminals test1 and test2.
Input a low level to each of. Signal input terminal S0
, A selection signal for selecting the input signal B is input. Thereafter, a high-level voltage is input to the test signal input terminal test2. As a result, if the selector 2 operates normally, the output voltage of the selector 2 changes to the high level, and the output voltage of the output terminal OUT changes to the high level. At this time, if the selector 2 cannot select the input terminal A for some reason, the output voltage of the output terminal OUT does not change, so that the abnormality of the selector 2 can be determined. In this manner, a function test can be performed from the input terminal B side of the selector 2. As described above, the function test of the selector 2 can be performed from both the input terminal A and the input terminal B.

FIG. 3 shows the structure of the selector 2 with the OR circuit shown in FIG. In the drawing, the same reference numerals are used for the same components as those shown in FIG. 5, and thus, duplicate description will be omitted below. The collector and the emitter of the transistor 11 are connected in parallel to the collector and the emitter of the transistor 24, and the base is connected to the test signal input terminal test1. Further, the transistor 17
The collector and the emitter of the transistor 2 are connected in parallel.
The collector and emitter of No. 5 are connected, and the base is connected to a test signal input terminal test2.

As described above, when the selector 2 is an ECL circuit, the selector 2 with the OR circuit can be configured only by adding two transistors. That is, the transistors 11 and 24 form an OR circuit 22, and the transistors 17 and 25 form an OR circuit 23. In this case, the input signal from the input terminal IN is applied to the input terminal A, and the output of the delay circuit 21 (gate circuit 1) is
May be applied.

Incidentally, a voltage of about -0.8 V as a high level and a voltage of about -1.4 V as a low level are applied to the input terminals A and B and the test signal input terminals test1 and test2. The selection signal S has input terminals A,
A voltage shifted by about -0.8 V compared to B, that is, a voltage of about -1.6 V at a high level and a voltage of about -2.2 V at a low level is applied. Further, the reference voltage VR ₁ is an input terminal A, B
The order of -1.1V at a high level and the intermediate voltage of low level applied to the reference voltage VR ₂ is the intermediate voltage between the high level and low level applied to the selection signal S -
A voltage of about 1.9 V is applied.

In FIG. 3, the case where the value of the current flowing through the constant current source 15 is I and the value of the resistor 13 is R is considered. First, when the selection signal applied to the signal input terminal S is at a high level, comparing the base potentials of the transistors 14 and 18, the base potential of the transistor 14 is higher than the base potential of the transistor 18. Flows through. Next, transistors 11, 24
When a high level voltage is input to either the input terminal A or the test signal input terminal test1, the current I flows through the transistor 11 or 24. Therefore, the current I
Flows through the path from the higher power supply → the transistor 11 (or 24) → the transistor 14 → the constant current source 15. In this case, since no current flows through the resistor 13, the output terminal OUT
Is approximately the value of the higher power supply.

On the other hand, the input terminal A and the test signal input terminal t
When a low level voltage is input to both of the transistors est1, the current I flows through the transistor 12. Therefore,
The current I flows through the path from the higher power supply → the resistor 13 → the transistor 12 → the transistor 14 → the constant current source 15. In this case, the potential of the output terminal OUT has a voltage drop due to the resistance 13 and the current I, and has a value of [voltage of high-order power supply−I × R] (low-level output). Therefore, the output terminal OU
Considering the voltage level of T, when one (or both) of the input terminal A and the test signal input terminal test1 is at a high level, the output voltage becomes a high level, and the input terminal A
When both the test signal input terminal test1 and the test signal input terminal test1 are at the low level, the voltage of the output terminal OUT becomes low level, so that the OR logic of the input terminal A and the test signal input terminal test1 is output. At this time, since no current flows through the transistors 16, 25, and 17, there is no change in the voltage of the output terminal OUT due to the voltages of the input terminal B and the test signal input terminal test2. As described above, when a high-level voltage is input to the signal input terminal S, the voltage of the output terminal OUT is changed between the input terminal A and the test signal input terminal te.
A logical result is obtained by taking OR of st1.

Next, when the selection signal applied to the signal input terminal S is at a low level, comparing the base potentials of the transistors 14 and 18, the base potential of the transistor 18 is higher than the base potential of the transistor 14. I
Flows through the transistor 18.

Next, when the base potential of the transistor 16 is compared with the base potentials of the transistors 17 and 25, when a high-level voltage is input to one of the input terminal B and the test signal input terminal test2, the current I becomes the transistor 17 or 25. Will flow on the side. Therefore, the current I flows through the path from the higher power supply → the transistor 17 (or 25) → the transistor 18 → the constant current source 15. in this case,
Since no current flows through the resistor 13, the potential of the output terminal OUT becomes substantially the value of the higher power supply (high-level output).
On the other hand, when a low-level voltage is input to both the input terminal B and the test signal input terminal test2, the current I flows through the transistor 16. Therefore, the current I is high-side power supply → resistor 13 → transistor 16 → transistor 18 →
It flows through the path of the constant current source 15. In this case, the output terminal OU
As for the potential of T, a voltage drop occurs due to the resistance 13 and the current I,
[High-side power supply voltage-I x R] value (low-level output)
Becomes Therefore, as in the case of the input terminal A and the test signal input terminal test1, the OR logic of the input terminal B and the test signal input terminal test2 is output. At this time, since no current flows through the transistors 11, 24 and 12, the input terminal A and the test signal input terminal tes
Even if the voltage at t1 changes, the voltage at the output terminal OUT does not change. As described above, when the low-level selection signal is input to the signal input terminal S, a voltage according to the OR logic of the voltage of the input terminal B and the voltage of the test signal input terminal test2 is output to the output terminal OUT.

As described above, when an ECL circuit is used for the selector 2, a variable delay circuit with an OR circuit can be configured only by adding two transistors. In addition, an increase in the delay time (tpdOR) due to the addition of the OR circuit does not mean that a new logic circuit is created, and thus does not cause an increase in cost.

[0045]

As is clear from the above, according to the variable delay circuit of the present invention, an OR circuit to which an input signal, a delay circuit (gate circuit) output and a test signal are input is provided on the input side of the selector. Therefore, even when the delay of the logic gate is small, the function test of the selector can be performed.

Since the OR circuit can be easily incorporated into the selector using the ECL circuit with the minimum number of components, the circuit is not complicated and the cost is not increased.

Further, in a configuration in which selectors having a number of logic gates corresponding to a required delay time on the input side are provided in multiple stages, an input terminal for inputting a test signal is provided for each, so that the delay time can be set arbitrarily. And the function test of each selector becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a variable delay circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the variable delay circuit according to the present invention.

FIG. 3 is a circuit diagram showing a detailed configuration of an OR circuit and a selector in FIGS. 1 and 2;

FIG. 4 is a circuit diagram showing a conventional variable delay circuit.

FIG. 5 is a circuit diagram showing a detailed configuration of a selector of FIG. 4;

[Explanation of symbols]

1,4,5,7,8,9,10 Gate circuit 2,3,6 Selector 11,12,14,16,17,18 24,25 Transistor 13 Resistor 15 Constant current source 20,30,40 Variable delay circuit 21 delay circuits 22 and 23 an OR circuit A, B, S input terminal IN input terminal OUT output terminal S _{0, S} 1, _{S 2} signal input terminal test1, test2 test signal input terminal VR _1, VR ₂ reference voltage

Claims (6)

[Claims] A first input terminal for inputting an input signal;
A second input terminal for inputting the input signal via a logic gate having a predetermined delay time, and an output terminal for outputting the input signal input to the first or second input terminal by a selection signal. A variable delay circuit configured by a selector having: a first input terminal for inputting the input signal; a second input terminal for inputting a first test signal for functionally testing the selector; and the input signal. Alternatively, a first OR circuit having an output terminal that outputs the first test signal to the first input terminal of the selector, and a first input circuit that receives the input signal that has passed through the logic gate
And a second input terminal for inputting a second test signal for testing the selector function, and the input signal or the second test signal that has passed through the logic gate and the second test signal of the selector. And a second OR circuit having an output terminal for outputting to an input terminal of the variable delay circuit. 2. The first and second OR circuits, wherein the first and second test signals at a low level are normally input to the second input terminal. 3. The variable delay circuit according to 1. 3. The first and second OR circuits are configured to input a low-level input signal to the first input terminal during a function test of the selector, and to cause the first and second OR circuits to sequentially change to a high level. 2. The variable delay circuit according to claim 1, wherein a second test signal is input to said second input terminal. 4. The method according to claim 1, wherein the selector is an ECL (Emitter Coup).
led Logic) circuit, and the first and second
2. The OR circuit according to claim 1, wherein a transistor for individually inputting said first and second test signals to each of transistors constituting an input section of said selector is ECL-connected. A variable delay circuit as described. 5. A first input terminal for inputting an input signal,
A first OR circuit having a second input terminal for inputting a first test signal, an output terminal for outputting the input signal or the first test signal, and a logic gate having a predetermined delay time A first input terminal for inputting the input signal that has passed through, a second input terminal for inputting a second test signal, and the input signal or the second test signal that has passed through the logic gate. A second OR circuit having an output terminal for outputting, a first input terminal connected to the output terminal of the first OR circuit, and a second input terminal connected to the second OR circuit. A first selector having an output terminal for outputting a signal input to the first or second input terminal in accordance with a selection signal input to the selection terminal; and a first selector connected to the output terminal of the first selector. A first input terminal; A second input terminal connected to the output terminal of the first selector via a first predetermined number of logic gates having the same delay time as the logic gate, and a selection signal input to the selection terminal A second selector having an output terminal for outputting a signal input to the first or second input terminal according to the following: a first input terminal connected to the output terminal of the second selector; A second input terminal connected to the output terminal of the second selector via a second predetermined number of logic gates having the same delay time as the logic gate, and a selection signal input to the selection terminal And a third selector having an output terminal for outputting a signal input to the first or second input terminal according to the above. 6. The first predetermined number of logic gates,
6. The variable delay circuit according to claim 5, wherein the second predetermined number of logic gates is constituted by two logic gates, and the second predetermined number of logic gates is constituted by four logic gates.