JP4480880B2 - Semiconductor circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a monitor for inspection of a semiconductor process.
[0002]
[Prior art]
In order to establish a process technology at the time of starting a semiconductor process, it is necessary to actually create and test a semiconductor circuit element. Even after the semiconductor process is started, it is necessary to create and test a semiconductor circuit element as an inspection target for monitoring a product lot. A chip created for such a test purpose is called a TEG (Test Element Group), and each circuit element inside the TEG is called a monitor. For example, by actually creating a monitor with a transistor as a circuit element and testing the characteristics of the transistor under various voltage and current conditions, it is determined whether or not the semiconductor process used for creating the monitor is appropriate. I can do it.
[0003]
[Problems to be solved by the invention]
In order to investigate the limit points and reproducibility of the semiconductor process, it is preferable to mount many monitors on one chip. However, in general, a monitor that is a circuit element such as a resistor, a capacitor, or a transistor requires at least two terminals for each monitor. For example, when M monitors are mounted on one chip, 2M terminals are supported. 2M pads are provided on the chip. The number of pads that can be mounted on one chip is considerably limited due to the area of the pads, which hinders mounting a sufficient number of monitors.
[0004]
In order to solve this problem, the number of pads has been reduced by connecting terminals that can be shared into a single pad, for example, by combining the terminals on the input side of each monitor into one. Was configured to be. However, in this method, of course, if the output terminal is shared, the characteristics of each monitor cannot be measured independently, so it is impossible to share the output terminal, and the number of pads is halved. The degree was the limit.
[0005]
In view of the above, an object of the present invention is to provide a test semiconductor chip on which a large number of monitors can be mounted without being limited by the number of pads.
[0006]
[Means for Solving the Problems]
The semiconductor circuit according to the present invention includes a series connection circuit in which a plurality of test circuits including a monitor to be inspected and having two terminals are connected in series by connecting the terminals, and one end of the series connection circuit is externally connected to one end. A terminal for supplying a voltage of 1; a terminal for supplying a second voltage from the outside to the other end of the series connection circuit; The terminal that supplies the first voltage and the terminal that supplies the second voltage are separate terminals, A measuring terminal capable of measuring a potential from the outside; and a selection unit that selects an arbitrary test circuit from the series connection circuit and connects at least one of the two terminals of the selected test circuit to the measurement terminal. And
[0007]
In the above-described semiconductor circuit, a plurality of test circuits each including a monitor to be measured are connected in series, any one test circuit is selected, and the potential at the upper end connection point and the potential at the lower end connection point are selected. The voltage drop generated in the test circuit can be measured by adopting a configuration that can be measured via. In this configuration, the test circuit or the monitor circuit in the test circuit may be electrically connected to a total of three terminals: a power supply voltage terminal, a ground voltage terminal, and a measurement terminal for a plurality of test circuits connected in series. As a result, the number of terminals and thus the number of pads can be greatly reduced as compared with the conventional configuration. Accordingly, a large number of monitors can be mounted on a single chip, and an efficient test semiconductor chip can be generated.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the principle and embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0009]
FIG. 1 is a diagram for explaining a test semiconductor chip according to the principle of the present invention.
[0010]
In FIG. 1, a test semiconductor chip 10 includes a plurality of test circuits 11-1 to 11-n each including a monitor to be measured, a selection unit 12, and terminals T1 to T3. The plurality of test circuits 11-1 to 11-n are connected in series, and terminals T1 and T2 are provided at both ends of the series connection, respectively. For example, the terminal T1 is set to a high potential, and the terminal T2 is set to the ground potential. The selection unit 12 is connected to the upper end and the lower end of each of the plurality of test circuits 11-1 to 11-n connected in series, and selects an arbitrary connection point to connect to the terminal T3 that is a measurement terminal. . Accordingly, by measuring the potential appearing at the measurement terminal T3, it is possible to measure the potential at a selected position of the circuit in which the test circuits 11-1 to 11-n are connected in series.
[0011]
For example, the voltage drop generated in the test circuit 11-2 can be measured by measuring the potential at the upper end connection point and the potential at the lower end connection point of the test circuit 11-2. As a result, for example, whether or not the monitor (test target circuit element) that should originally be in the open state is correctly open, and whether the monitor (test target circuit element) that should be in the shorted state is correctly in the short state Whether or not can be determined.
[0012]
In this configuration, only three terminals T1 to T3 are electrically connected to the test circuit or the monitor circuit in the test circuit, and the number of terminals and thus the number of pads can be greatly increased as compared with the conventional configuration. Can be reduced. Accordingly, a large number of monitors can be mounted on a single chip, and an efficient test semiconductor chip can be generated. In reality, a terminal for controlling the selection operation of the selection means 12 is required. For example, when 63 test circuits 11-1 to 11-n (n = 63) are provided, 6-bit information selection (2 ⁶ = 64), six terminals and pads are added to the three terminals and pads. However, even in this case, when the 126 terminals are mounted on each of the 63 test circuits with 2 terminals as in the prior art, or the input terminals are shared, 64 terminals (input 1 terminal and output 63) are used. The number of terminals and pads can be greatly reduced compared to the case of terminals.
[0013]
FIG. 2 shows a circuit configuration when inspecting a monitor whose open state is normal.
[0014]
As in FIG. 1, test circuits 11-1 to 11-n are connected in series, and terminals T1 and T2 are provided at both ends of the series connection. The selection means 12 in FIG. 1 corresponds to the switches S1 to S64 in FIG. Based on the selection signal input to the terminal S, one of the switches S1 to S64 conducts, and the potential at the conduction destination appears at the measurement terminal T3. Although the terminal S is illustrated as one terminal, actually, a terminal for at least 6 bits is required.
[0015]
Each of the test circuits 11-1 to 11-n includes a monitor Mx and a resistor Rx (x is an integer from 1 to 63). Here, the resistors R1 to R63 are resistors whose resistance values on the standards are known (resistances manufactured according to a predetermined standard). The monitors M1 to M63 are circuit elements that are in a normal state and open, such as capacitors and off-state transistors.
[0016]
When a high voltage is applied to the terminal T1 and the terminal T2 is set to the ground potential, a current flows through the test circuits 11-1 to 11-63 connected in series. Here, since the monitors M1 to M63 are open elements, almost no current flows if they are normal. Since the resistor Rx is connected in parallel even when the monitor Mx is open, the current flows through the resistor Rx and is supplied to the next-stage test circuit. When the monitor Mx is not manufactured normally, or when the monitor Mx is destroyed by exceeding the allowable limit due to voltage application, the short circuit state occurs instead of the open state. In this case, by measuring the potential at both ends of the corresponding test circuit 11-x, it is detected that the monitor Mx is in a short circuit state, and the resistance value (a minute resistance value) of the monitor Mx is measured. I can do it. This makes it possible to evaluate the semiconductor process for manufacturing each monitor.
[0017]
FIG. 3 shows a circuit configuration when inspecting a monitor in which the short-circuit state is normal.
[0018]
As in FIG. 1, test circuits 11-1 to 11-n are connected in series, and terminals T1 and T2 are provided at both ends of the series connection. The selection means 12 in FIG. 1 corresponds to the switches S1 to S64 in FIG. Based on the selection signal input to the terminal S, one of the switches S1 to S64 conducts, and the potential at the conduction destination appears at the measurement terminal T3. Although the terminal S is illustrated as one terminal, actually, a terminal for at least 6 bits is required.
[0019]
Each of the test circuits 11-1 to 11-n includes a monitor Mx, a resistor rx, and a resistor Rx (x is an integer from 1 to 63). Here, the resistor rx is connected in series to the monitor Mx, and the resistor Rx is connected in parallel to this series connection. The resistors r1 to r63 and the resistors R1 to R63 are resistors with known resistance values (resistances manufactured according to a predetermined standard). The monitors M1 to M63 are circuit elements that are in a normal state and in a short-circuited state, such as a resistor or an on-state transistor.
[0020]
When a high voltage is applied to the terminal T1 and the terminal T2 is set to the ground potential, a current flows through the test circuits 11-1 to 11-63 connected in series. Here, the resistance rx is designed to have a resistance value much smaller than the resistance Rx (rx << Rx). Since the monitors M1 to M63 are short-circuited elements, if normal, most of the current flows not through the resistor Rx but through the resistor rx and the monitor Mx side. The resistor rx serves to prevent a large current from flowing due to a short circuit between the terminals T1 and T2 due to a current flowing through the short-circuit monitor. When the monitor Mx is not manufactured normally or when the monitor Mx is destroyed beyond the allowable limit due to voltage application, it is not in a short circuit state but in an open state. In this case, it is possible to detect that the monitor Mx is in an open state by measuring the potential at both ends of the corresponding test circuit 11-x, and to measure the resistance value (large resistance value) of the monitor Mx. I can do it. This makes it possible to evaluate the semiconductor process for manufacturing each monitor.
[0021]
Examples of the present invention will be described below.
[0022]
FIG. 4 is a diagram showing an embodiment of a circuit configuration when inspecting a monitor whose open state is a normal state.
[0023]
Similarly to FIG. 2, test circuits 11-1 to 11-63 are connected in series, and terminals T1 and T2 are provided at both ends of the series connection. Each of the test circuits 11-1 to 11-63 includes a parallel connection of a monitor Mx and a resistor Rx (where x is an integer from 1 to 63). Here, the resistors R1 to R63 are resistors whose resistance values on the standards are known (resistances manufactured according to a predetermined standard). The monitors M1 to M63 are circuit elements that are open in a normal state, such as capacitors and off-state transistors.
[0024]
The mechanism corresponding to the selection unit 12 in FIG. 1 includes a plurality of selector circuits 21. Each selector circuit 21 includes transfer gates 22 and 23 composed of a PMOS transistor and an NMOS transistor, and an inverter 24. A selection signal from an external terminal is supplied to the inverter 24. When this selection signal is HIGH, the transfer gate 22 is opened, and when the selection signal is LOW, the transfer gate 23 is opened. By this operation, one of the two input lines input to the selector circuit 21 is selected and electrically connected to the output line.
[0025]
Thirty-two selector circuits 21 are provided for the terminal D0 and are connected to 64 voltage measurement points connected in series of the test circuits 11-1 to 11-63. Sixteen selector circuits 21 controlled by a terminal D1 are connected to 32 output signal lines of these 32 selector circuits 21. Further, eight selector circuits 21 controlled by a terminal D2 are connected to 16 output signal lines of the 16 selector circuits 21. In this way, selection is sequentially performed at a ratio of 2 to 1, and the output of one selector circuit 21 controlled by the terminal D5 becomes the output terminal T3 of the selection means 12. With this configuration, it is possible to select one of the 64 voltage measurement points connected in series of the test circuits 11-1 to 11-63 and connect it to the output terminal T3.
[0026]
FIG. 5 is a diagram illustrating an example of the monitor and resistance values of the test circuit.
[0027]
FIG. 5 shows items 0 to 9 corresponding to different circuit element parameters. In any item, the number of monitors is 63, and a voltage of 2 V is applied between the terminals T1 and T2. The resistance value rm of the monitor Mx is assumed to be 10 MΩ (substantially open) at normal times and 300 kΩ at abnormal times.
[0028]
Item 0 corresponds to the case where the resistance value of Mx is infinite (10 MΩ or more) and there is no abnormality in Mx. In this case, if there is no abnormality monitor, the current flowing in the series connection of the test circuits 11-1 to 11-63 is 0.1058 μA, and the potential difference appearing at both ends of each normal monitor Mx is 31.7460 mV.
[0029]
Items 1 to 3 correspond to the case where the resistance value R of each resistor Rx is 100 kΩ. Item 1 is when the number of abnormal monitors is one, item 2 is when the number of abnormal monitors is 10, and item 3 is when the number of abnormal monitors is 15. For example, in the case of item 1 in which the number of abnormal monitors is one, the potential difference appearing at both ends of each normal monitor Mx is 31.8725 mV, and the potential difference appearing at both ends of the abnormal monitor Mx is 23.9044 mV.
[0030]
Items 4 to 6 correspond to the case where the resistance value R of each resistor Rx is 300 kΩ. Item 4 is when the number of abnormal monitors is one, item 5 is when the number of abnormal monitors is 10, and item 6 is when the number of abnormal monitors is 15. For example, in the case of item 4 where the number of abnormal monitors is one, the potential difference appearing at both ends of each normal monitor Mx is 32.0000 mV, and the potential difference appearing at both ends of the abnormal monitor Mx is 16.0000 mV.
[0031]
Items 7 to 9 correspond to the case where the resistance value R of each resistor Rx is 3 MΩ. Item 7 is when the number of abnormal monitors is one, item 8 is when the number of abnormal monitors is 10, and item 9 is when the number of abnormal monitors is 15. For example, in the case of item 7 in which the number of abnormal monitors is one, the potential difference appearing at both ends of each normal monitor Mx is 32.2108 mV, and the potential difference appearing at both ends of the abnormal monitor Mx is 2.9283 mV.
[0032]
In any of the above cases, by measuring the potential difference appearing at both ends of the monitor Mx (potential difference between both ends of the test circuit), it can be determined from the measured potential difference whether the monitor is in a normal state or an abnormal state. I can do it. Since the resistance value of the resistor Rx is known in the standard, the resistance value of the monitor is calculated from the measured potential difference based on this resistance value, regardless of whether it is normal or abnormal. I can do it.
[0033]
Strictly speaking, however, the resistance value of the resistor Rx is only known, and the actual resistance value is unknown. Also, this actual resistance value cannot be measured. Therefore, when the actual resistance value of the resistor Rx is different from the standard resistance value, the actual resistance value of the monitor is calculated by calculating the resistance value of the monitor from the potential difference measured using the standard resistance value. Will be different.
[0034]
This is shown in the lower part of FIG. For example, when the resistance value R of the actual resistance Rx is 20% larger than the resistance value on the standard, the potential difference between both ends of the abnormality monitor becomes large as compared with the standard case. In the case of item 1, the potential difference between both ends of the abnormality monitor is 27.3193 mV, which is increased compared to the case where the resistance value of the resistor Rx conforms to the standard (23.9044 mV). The error of the potential difference generated at both ends of the abnormality monitor (because the actual resistance value of the resistor Rx is different from the standard resistance value) becomes smaller as the resistance value R of the standard resistance Rx increases. In the case of item 7, that is, when the resistance value R on the standard is 3 MΩ, the potential difference between both ends of the abnormality monitor is 2.9283 mV when the resistance value R conforms to the standard, whereas the resistance value R is higher than the standard. In the case of a 20% increase, it is 2.9733 mV. As described above, as the resistance value R of the standard resistor Rx increases, the influence of the error of the resistor R on the potential difference between both ends of the abnormality monitor decreases.
[0035]
The error of the resistance R also affects the resistance value of the monitor calculated from the potential difference across the abnormal monitor. For example, when the resistance value R is 20% larger than the standard resistance value, in item 1, the potential difference between both ends of the abnormality monitor is 27.3193 mV. When this potential difference is measured and the resistance value of the monitor is calculated using the standard resistance value of 100 kΩ, it becomes 600 kΩ. This is about twice as large as 300 kΩ which is the resistance value of the actual abnormality monitor, resulting in a 100% error. However, this error decreases as the resistance value R of the standard resistor Rx increases. For example, when the resistance value R is 20% larger than the standard resistance value, in item 7, the potential difference between both ends of the abnormality monitor is 2.9733 mV. When this potential difference is measured and the resistance value of the monitor is calculated using the standard resistance value of 3 MΩ, it becomes 305 kΩ. This is approximately equal to 300 kΩ, which is the resistance value of the actual abnormality monitor, and only an error of about 1.7% occurs.
[0036]
As described above, in the present invention, as the resistance value of the resistor Rx connected in parallel to the monitor Mx in the test circuits 11-1 to 11-n increases, an error that deviates from the standard value of the resistance value is calculated. The influence on the monitor resistance value is reduced. This is because the larger the resistance value of the resistor Rx connected in parallel to the monitor Mx, the smaller the current flowing through the resistor Rx compared to the current flowing through the monitor Mx, and the potential difference appearing at both ends of the test circuit is only the resistance value of the monitor. This is because it approaches a potential difference reflecting the above. That is, the closer the potential difference appearing at both ends of the test circuit is to the potential difference reflecting only the resistance value of the monitor, the smaller the influence of the error of the resistance value of the resistor Rx, and the more accurate monitor resistance value can be measured.
[0037]
Actually, the larger the resistance, the larger the area occupied on the chip. Therefore, in consideration of the balance between the usable area and the measurement accuracy, for example, when the resistance value at the time of abnormality of the monitor to be measured is rm, rm <R In this range, the resistance value R of the resistor Rx may be set to an appropriate value.
[0038]
FIG. 6 is a diagram showing an embodiment of a circuit configuration when inspecting a monitor whose normal short circuit state is normal. The same elements as those in FIG. 4 are referred to by the same reference numerals, and the description thereof is omitted.
[0039]
As in FIG. 3, test circuits 11-1 to 11-63 are connected in series, and terminals T1 and T2 are provided at both ends of the series connection. Each of the test circuits 11-1 to 11-63 includes a monitor Mx, a resistor rx, and a resistor Rx (x is an integer from 1 to 63). Here, the resistor rx is connected in series to the monitor Mx, and the resistor Rx is connected in parallel to this series connection. Here, the resistors R1 to R63 and r1 to r63 are resistors with known resistance values (resistances manufactured according to a predetermined standard). The monitors M1 to M63 are circuit elements that are in a normal state and are in a conductive state, such as a resistor or an on-state transistor.
[0040]
FIG. 7 is a diagram illustrating an example of the monitor and resistance values of the test circuit.
[0041]
FIG. 7 shows items 0 to 9 corresponding to different circuit element parameters. In any item, the number of monitors is 63, and a voltage of 2 V is applied between the terminals T1 and T2. The resistance value rm of the monitor Mx is assumed to be 5Ω (substantially short-circuited) at normal times and 100Ω at abnormal times. Furthermore, the resistance value R of the resistor Rx is 500Ω.
[0042]
Item 0 corresponds to the case where the resistance value r of the resistor rx is 20Ω and there is no abnormality monitor. In this case, the current flowing in the series connection of the test circuits 11-1 to 11-63 is 1.3333 μA, and the potential difference of each normal monitor Mx is 31.7460 mV.
[0043]
Items 1 to 3 correspond to the case where the resistance rx does not exist (r = 0). Item 1 is when the number of abnormal monitors is one, item 2 is when the number of abnormal monitors is 10, and item 3 is when the number of abnormal monitors is 60. For example, in the case of item 3 where the number of abnormal monitors is 60, the potential difference of each normal monitor Mx is 1.9743 mV, and the potential difference of the abnormal monitor Mx is 33.2346 mV.
[0044]
Items 4 to 6 correspond to the case where the resistance value r of each resistor rx is 5Ω. Item 4 is when the number of abnormal monitors is one, item 5 is when the number of abnormal monitors is 20, and item 6 is when the number of abnormal monitors is 60. For example, in the case of item 6 in which the number of abnormal monitors is 60, the potential difference of each normal monitor Mx is 3.7448 mV, and the potential difference of the abnormal monitor Mx is 33.1461 mV.
[0045]
Items 7 to 9 correspond to the case where the resistance value r of each resistor rx is 20Ω. Item 7 is when the number of abnormal monitors is one, item 8 is when the number of abnormal monitors is 20, and item 9 is when the number of abnormal monitors is 60. For example, in the case of item 9 where the number of abnormal monitors is 60, the potential difference of each normal monitor Mx is 8.1014 mV, and the potential difference of the abnormal monitor Mx is 32.9283 mV.
[0046]
Here, the resistor rx plays a role of limiting the current and not destroying the element. Therefore, as shown in FIG. 8, if the resistor 30 is inserted in a part of the series connection of the test circuits 11-1 to 11-n, the resistor rx is not inserted in each test circuit. Good. However, in the configuration as shown in FIG. 8, the resistor 30 serves only a function of limiting the current, but the resistor rx of FIG. 6 performs a function other than the current limiting function.
[0047]
As shown in item 3 of FIG. 7, when the resistance rx does not exist and the number of abnormality monitors is large, the amount of current flowing decreases, and the potential difference of each normal monitor Mx is as small as 1.9743 mV. . At this time, for example, if the resolution of the voltmeter for measuring the voltage is 2 mV, 1.9743 mV is rounded to 2 mV. However, as shown in item 9, for example, when a resistance rx of 20Ω is provided, even if the number of abnormal monitors increases and the amount of flowing current decreases, the potential difference of each normal monitor Mx becomes 8.1014 mV. Therefore, a large potential difference can be secured even with a small current.
[0048]
However, if the resistance value r of the resistor rx is brought close to the resistance value R of the resistor Rx, there will be no significant difference in potential difference between the normal monitor and the abnormal monitor. FIG. 9 is a diagram illustrating current and voltage values when the resistance value r is close to the resistance value R. In FIG. As shown in FIG. 9, when the resistance value r is set to 300Ω and the resistance value R is close to 500Ω, the potential difference in the case of normal monitoring and the potential difference in the case of abnormality monitoring are not so different, and due to manufacturing variations of the resistance Rx. It becomes impossible to determine whether the difference is a difference or a difference caused by the actual change in the resistance value of the monitor.
[0049]
As described above, in a circuit configuration for inspecting a monitor in which the conduction state is normal, a configuration in which the resistor rx is connected in series to the monitor Mx and this series connection is connected in parallel to the resistor Rx is preferable. The resistance value r of the resistor rx is preferably rm <r <R, where rm is the normal resistance value of the monitor to be measured. For example, the resistance value r is preferably set so that its order is at least one digit higher than the resistance value rm and at least one digit lower than the resistance value R of the resistor Rx.
[0050]
As described above, in the test semiconductor chip of the present invention, a plurality of test circuits each including a monitor to be measured are connected in series, an arbitrary one test circuit is selected, and the potential at the upper end connection point is selected. And the potential at the lower end connection point can be measured via the selection means, the voltage drop generated in the test circuit can be measured. Thereby, for example, it can be determined whether or not a monitor that should originally be in an open state is correctly in an open state, and whether or not a monitor that is supposed to be in a short-circuit state is correctly in a short-circuit state.
[0051]
Note that the monitors of the plurality of test circuits connected in series need not be the same, and may be different monitors. Further, the resistance values of the resistance elements of the test circuits are not necessarily the same, and may be changed according to the monitor to be measured. Alternatively, all the resistance values of the resistance elements of the test circuits may be set to be the same.
[0052]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
[0053]
The contents of the present invention include the inventions within the scope described below.
[0054]
APPENDIX 1) A series connection circuit in which a plurality of test circuits including a monitor to be inspected and having two terminals are connected in series by connecting the terminals, and a first voltage is externally applied to one end of the series connection circuit. A terminal for supplying, a terminal for supplying a second voltage from the outside to the other end of the series connection circuit, a measurement terminal capable of measuring potential from the outside, and an arbitrary test circuit selected from the series connection circuit A semiconductor circuit comprising selection means for connecting at least one of the two terminals of the test circuit to the measurement terminal.
[0055]
(Supplementary note 2) The semiconductor circuit according to Supplementary note 1, wherein the monitor is a circuit element that is substantially open in a normal state and substantially in a conductive state in an abnormal state.
[0056]
(Supplementary note 3) The semiconductor circuit according to Supplementary note 1, wherein the monitor is substantially short-circuited when normal and is substantially in a high impedance state when abnormal.
[0057]
Appendix 4) The semiconductor circuit according to Appendix 1, wherein the test circuit is a circuit in which the monitor and a resistor are connected in parallel.
[0058]
(Supplementary note 5) The semiconductor circuit according to Supplementary note 4, wherein a resistance value of the resistor is larger than a resistance value of a measurement target of the monitor in an abnormal state.
[0059]
(Supplementary note 6) The semiconductor circuit according to Supplementary note 4, wherein the series connection circuit further includes a current limiting resistor connected in series.
[0060]
Supplementary Note 7) The test circuit is a circuit in which the monitor and the first resistor are connected in series, and a series connection of the monitor and the first resistor is connected in parallel with a second resistor. The semiconductor circuit according to appendix 1.
[0061]
(Supplementary note 8) The resistance value of the first resistor is larger than the resistance value of the monitor to be measured in a normal state, and the resistance value of the second resistor is larger than the resistance value of the first resistor. The semiconductor circuit according to appendix 7.
[0062]
Supplementary Note 9) The selection means is 2 ⁿ 2. The semiconductor device according to appendix 1, wherein n selection terminals are included for bit selection.
[0063]
【The invention's effect】
In the test semiconductor chip of the present invention, a plurality of test circuits each including a monitor to be measured are connected in series, any one test circuit is selected, and the potential at the upper end connection point and the potential at the lower end connection point Is configured to be measurable through the selection means, so that a voltage drop generated in the test circuit can be measured. In this configuration, the test circuit or the monitor circuit in the test circuit may be electrically connected to a total of three terminals: a power supply voltage terminal, a ground voltage terminal, and a measurement terminal for a plurality of test circuits connected in series. As a result, the number of terminals and thus the number of pads can be greatly reduced as compared with the conventional configuration. Accordingly, a large number of monitors can be mounted on a single chip, and an efficient test semiconductor chip can be generated.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a test semiconductor chip according to the principle of the present invention;
FIG. 2 is a diagram showing a circuit configuration when inspecting a monitor whose open state is a normal state.
FIG. 3 is a diagram showing a circuit configuration when inspecting a monitor whose normal state is a short circuit state;
FIG. 4 is a diagram showing an embodiment of a circuit configuration when inspecting a monitor whose open state is a normal state.
FIG. 5 is a diagram illustrating an example of a monitor and resistance value of a test circuit.
FIG. 6 is a diagram showing an example of a circuit configuration when inspecting a monitor whose normal short-circuit state is normal.
FIG. 7 is a diagram illustrating an example of monitor and resistance values of a test circuit.
FIG. 8 is a diagram showing another embodiment of a circuit configuration when inspecting a monitor in which a substantially short-circuit state is normal.
9 is a diagram showing current and voltage values when a resistance value r is brought close to the resistance value R. FIG.
[Explanation of symbols]
11-1 to 11-n test circuit
12 Selection means

Claims (7)

A series connection circuit in which a plurality of test circuits including a monitor to be inspected and having two terminals are connected in series by connecting the terminals;
A terminal for supplying a first voltage from the outside to one end of the series connection circuit;
A terminal for supplying a second voltage from the outside to the other end of the series connection circuit;
The terminal for supplying the first voltage and the terminal for supplying the second voltage are separate terminals, and a measurement terminal capable of measuring potential from the outside,
A semiconductor circuit comprising: selection means for selecting an arbitrary test circuit from the series connection circuit and connecting at least one of the two terminals of the selected test circuit to the measurement terminal.   2. The semiconductor circuit according to claim 1, wherein the monitor is a circuit element that is substantially open when normal and is substantially conductive when abnormal.   2. The semiconductor circuit according to claim 1, wherein the monitor is substantially short-circuited when normal and is substantially high-impedance when abnormal.   2. The semiconductor circuit according to claim 1, wherein the test circuit is a circuit in which the monitor and a resistor are connected in parallel.   5. The semiconductor circuit according to claim 4, wherein a resistance value of the resistor is larger than a resistance value of a measurement target of the monitor at the time of abnormality. A series connection circuit in which a plurality of test circuits including a monitor to be inspected and having two terminals are connected in series by connecting the terminals;
A terminal for supplying a first voltage from the outside to one end of the series connection circuit;
A terminal for supplying a second voltage from the outside to the other end of the series connection circuit;
A measurement terminal capable of measuring potential from the outside,
Selection means for selecting an arbitrary test circuit from the series connection circuit and connecting at least one of the two terminals of the selected test circuit to the measurement terminal
Including
The test circuit, said monitor and a first resistor connected in series, the semiconductor circuit which is a circuit for a series connection connected in parallel with the second resistor with the resistor the monitor and the first.   The resistance value of the first resistor is larger than the resistance value of the measurement target of the monitor in a normal state, and the resistance value of the second resistor is larger than the resistance value of the first resistor. Item 7. The semiconductor circuit according to Item 6.

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