JP2000031470A - Pattern layout of semiconductor ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern layout of a semiconductor IC which has a pattern layout of a gate forming part of a MOS transistor, wherein the gate forming part has a bending angle in 90 degrees and it is not swollen like a stomach after a lithography process. SOLUTION: In the pattern layout, firstly a source forming part 12 and a drain forming part 13 are formed. Then, contacts 14 are arranged individually in the source forming part 12 and in the drain forming part 13. As a result, a gate forming part 11 consisting of the first linear part 11a, the second linear part 11b, and a bending part 11c is formed. The first linear part 11a and the second linear part 11b, which have both long and short sides, are arranged in parallel to and obliquely to each other, and the said two parts are jointed by the rectangular bending part 11c. The bending part 11c is arranged in 90 degrees of the angle against the first linear part 11a and the second linear part 11b individually. In this case, the length of the jointed part of the first linear part 11a with the bending part 11c, and the length of the jointed part of the second linear part 11b with the bending part 11c are individually smaller than each short side length of the first linear part 11a and the second linear part 11b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern layout of a semiconductor integrated circuit, and more particularly to a pattern layout for a polysilicon gate electrode layer of a MOS transistor.

[0002]

2. Description of the Related Art A MOS transistor pattern layout has a structure in which contacts are arranged one by one on a source electrode and a drain electrode to reduce a chip area, and a gate electrode is wired so as to bypass the contacts.

FIG. 6A is a top view of a pattern layout of a conventional MOS transistor. A source forming section 12 and a drain forming section 13 are formed. The contacts 14 are arranged one by one in the source forming part 12 and the drain forming part 13, and the crank-shaped gate forming part 11 is formed. The gate forming portion 11 has a bending angle of 90 degrees and a constant wiring width. FIG.
FIG. 6B is a top view of the MOS transistor after a step such as lithography using the pattern layout of FIG. 6A. The gate electrode 21 is swelled like a stomach by a lithography process.

In order to prevent the gate electrode 21 after the lithography process from swelling like a stomach, a gate forming portion 11 is formed.
Is used. A pattern layout having a 45 ° bending angle is used.

FIG. 7A is a top view of a pattern layout of a MOS transistor in which a bending angle of a gate electrode is 45 degrees according to the prior art, and FIG. 7B is a plan view of FIG.
FIG. 21 is a top view of the MOS transistor after a step such as lithography by the pattern layout of FIG. Source forming part 12
And a drain forming portion 13. The contacts 14 are arranged one by one in the source forming part 12 and the drain forming part 13, and the gate forming part 11 is formed. The gate forming portion 11 has a bending angle of 45 degrees and a constant wiring width.

[0006]

As described above, when a structure having a bend angle of 90 degrees and a constant wiring width is used in the pattern layout of the gate electrode, the gate electrode after the lithography process is swelled like a stomach. Will be. For this reason, the control by the gate electrode is not constant, and the current supply capability is reduced.

In the case where a structure having a bending angle of 45 degrees is used for the pattern layout of the gate forming portion, it is necessary to introduce a rotary implantation facility for implanting the impurity layer.
Process costs increase. Further, if the chip shrink rate is changed due to the chip size reduction, off-grid data is generated, and a problem that the bending angle deviates from 45 degrees occurs, which is not suitable for chip shrink.

An object of the present invention is to provide a MOS transistor having a bending angle of 90 degrees and not expanding like a stomach after a lithography process.
An object of the present invention is to provide a pattern layout of a semiconductor integrated circuit having a gate formation portion of a transistor.

[0009]

A pattern layout of a semiconductor integrated circuit according to the present invention includes a source forming portion having a contact formed thereon, a drain forming portion having a contact formed therein, a first straight portion, and a second straight portion. A first straight portion and a second straight portion are parallel to each other, and the first straight portion and the second straight line are arranged between the first straight portion and the second straight portion. The part and the bent part are characterized by being arranged diagonally. Also,
The first straight portion and the second straight portion are composed of long sides and short sides, and the bent portion is rectangular, and a contact portion between the first straight portion, the second straight portion, and the bent portion is formed. The length is shorter than the short side, and the contact portions of the first straight portion, the second straight portion, and the bent portion overlap at corners.

Further, a pattern layout of a semiconductor integrated circuit according to the present invention includes a source forming portion having a contact formed therein, a drain forming portion having a contact formed therein, and first and second linear portions. A gate forming portion, wherein the first linear portion and the second linear portion are parallel and diagonally arranged.
In addition, the first straight portion and the second straight portion include a long side and a short side, and the first straight portion and the second straight portion.
The contact portion of the straight portion is shorter than the short side, and the contact portion of the first straight portion and the second straight portion overlaps at a corner.

According to the present invention, the bending angle is 90 degrees.
The gate electrode can be formed only by a pattern layout having a certain structure, and a MOS transistor which does not cause unnecessary bulging in the gate electrode after the lithography process and which is suitable for chip shrink can be formed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a top view of a pattern layout of a MOS transistor according to a first embodiment of the present invention, and FIG.
It is a top view of the MOS transistor after the processes, such as lithography by the pattern layout of (a). FIG. 1 (a)
As shown in FIG.
3 are formed. The contacts 14 are arranged one by one in the source forming part 12 and the drain forming part 13,
The gate forming portion 11 is formed of the straight portion 11a, the second straight portion 11b, and the bent portion 11c.
A first straight line portion 11a composed of a long side and a short side and a second
Are arranged in parallel and diagonally, and are connected by a rectangular bent portion 11c. The bent portion 11c is disposed at an angle of 90 degrees with respect to the first straight portion 11a and the second straight portion 11b, and the first straight portion 11a, the bent portion 11c, and the second straight portion 1c.
1b and the length of the contact portion between the bent portion 11c are the first
Are thinner than the short sides of the straight portion 11a and the second straight portion 11b.

In the first embodiment, the gate forming portion 11
Of the first straight portion 11a and the second bent portion 11c
1B, the wiring width is narrowed at an angle of 90 degrees with respect to the straight portion 11b. Therefore, as shown in FIG. No swelling occurs and the gate electrode 2 has a uniform width.
Since 1 can be formed, a decrease in current supply capability can be prevented. Further, the pattern layout of the gate forming portion 11 is such that the bent portion 11c is formed at 90 degrees with respect to the first straight portion 11a and the second straight portion 11b, so that it is not necessary to introduce a rotary implantation facility.
Costs can be reduced. In addition, it is possible to easily cope with chip shrink.

FIG. 2A is a top view of a pattern layout of a MOS transistor according to a second embodiment of the present invention, and FIG. 2B is a step of lithography using the pattern layout of FIG. 2A. It is a top view of the MOS transistor after. As shown in FIG. 2A, a source forming section 12 and a drain forming section 13 are formed.
The contacts 14 are arranged one by one in the source forming portion 12 and the drain forming portion 13, and the first straight portion 11 a and the second
The gate forming portion 11 is formed of the straight portion 11b and the bent portion 11c. First straight portion 11a and second straight portion 11b each having a long side and a short side
Are arranged in parallel and diagonally, and are connected by a rectangular bent portion 11c. 1st linear part 11a
And the contact portion of the bent portion 11c, the second straight portion 11
The contact portion between b and the bent portion 11c is shorter than the short sides of the first straight portion 11a and the second straight portion 11b. A cutout portion is formed by bringing the first straight portion 11a and the bent portion 11c into contact with each other and the second straight portion 11b and a portion of the bent portion 11c into contact with each other.

In the second embodiment, the first straight portion 11
a, the bent portion 11c and the second straight portion 11b are diagonally opposite, and the contact portion is in contact with the first straight portion 11a and the second straight portion 11b at a value shorter than the shorter side, and a cutout portion is provided to form a gate. By forming the formation portion 11, FIG.
As shown in (b), no unnecessary bulging occurs at the bent portion of the gate electrode 21 after the lithography process,
Since the gate electrode 21 can be formed with a uniform width, a decrease in current supply capability can be prevented. Since the pattern layout of the gate forming unit 11 is formed at an angle of 90 degrees, it is not necessary to introduce a rotary implantation facility, and the cost can be reduced. In addition, it is possible to easily cope with chip shrink.

In FIG. 2A, a first straight portion 11a
And a contact portion of the bent portion 11c with the second straight portion 11b is a first straight portion 11a and a second straight portion 11b.
However, if the gate electrode 21 after the step of lithography or the like is formed in a desired shape, the first
The first straight portion 11a and the bent portion 11c, and the second straight portion 11b and the bent portion 11c are the first straight portion 11a.
And may be in contact at the short side of the second straight portion 11b (FIG. 3A) or may overlap at the corner (FIG. 3A).
(B)) or may be in contact at a corner (FIG. 3)
(C)).

FIG. 4A is a top view of a pattern layout of a MOS transistor according to a third embodiment of the present invention, and FIG. 4B is a step of lithography using the pattern layout of FIG. It is a top view of the MOS transistor after. As shown in FIG. 4A, a source forming section 12 and a drain forming section 13 are formed. The contacts 14 are arranged one by one in the source forming portion 12 and the drain forming portion 13, and a gate forming portion 11c including a first straight portion 11a, a second straight portion 11b, and two bent portions 11c is formed. First straight portion 11a and second straight portion 11b each having a long side and a short side
Are arranged in parallel and diagonally, and are connected by two rectangular bent portions 11c. The bent portion 11c includes a first straight portion 11a and a second straight portion 11
It is formed at an angle of 90 degrees with respect to b. The contact portion between the first straight portion 11a and the bent portion 11c, the contact portion between the second straight portion 11b and the bent portion 11c, and the contact portion between the two bent portions 11c are the first straight portion 11a and the second straight portion. 11b is shorter than the short side.

In the third embodiment, the first straight portion 11
a, the second straight portion 11b and the two bent portions 11
c as a diagonal, the first straight portion 11a and the second straight portion 1
1b, the notch portion is provided, a cutout portion is provided, and the gate formation portion 11 is formed. As a result, as shown in FIG. Since the swelling does not occur and the gate electrode 21 can be formed with a uniform width, a reduction in current supply capability can be prevented. Since the pattern layout of the gate forming unit 11 is formed at an angle of 90 degrees, it is not necessary to introduce a rotary implantation facility, and the cost can be reduced. In addition, it is possible to easily cope with chip shrink.

In FIG. 4A, a first straight portion 11a
And the contact portion of the bent portion 11c, the second straight portion 11
The contact portion between b and the bent portion 11c is a long side of the first straight portion 11a and the second straight portion 11b, and the contact portion between the two bent portions 11c is in contact with a side parallel to the other contact portion. Is the gate electrode 21 after a process such as lithography.
Is formed in a desired shape, the first linear portion 1
The contact portion between the first straight portion 11a and the bent portion 11c and the contact portion between the second straight portion 11b and the bent portion 11c may be in contact with each other at the short side of the first straight portion 11a and the second straight portion 11b. They may be in contact, or the corners may overlap. In FIG. 4A, the number of the bent portions is two, but the number of the bent portions may be two or more.

FIG. 5A is a top view of a pattern layout of a MOS transistor according to a fourth embodiment of the present invention, and FIG. 5B is a step of lithography using the pattern layout of FIG. It is a top view of the MOS transistor after. As shown in FIG. 5A, a source forming section 12 and a drain forming section 13 are formed.
The contacts 14 are arranged one by one in the source forming portion 12 and the drain forming portion 13, and the gate forming portion 11 including the first straight portion 11a and the second straight portion 11b is formed. First straight line portion 11a consisting of a long side and a short side
And the second linear portion 11b are arranged in parallel and diagonally, and are in contact with each other on the long sides or on the respective short sides, and the length of the contact portion is the first linear portion 11a and It is shorter than the short side of the second straight portion 11b.

In the fourth embodiment, the gate forming portion 11
Since the contact portion between the first straight portion 11a and the second straight portion 11b is shorter than the short sides of the first straight portion 11a and the second straight portion, as shown in FIG. Unnecessary swelling at the contact portion of the gate electrode 21 after the process does not occur, and the gate electrode 21 can be formed with a uniform width, so that a decrease in current supply capability can be prevented. Since the pattern layout of the gate forming unit 11 is formed only by straight lines having the same width, it is not necessary to introduce a rotary implantation facility, and the cost can be reduced. In addition, it is possible to easily cope with chip shrink.

In FIG. 5A, the contact portions of the first straight portion 11a and the second straight portion 11b of the gate forming portion 11 are in contact with each other on the long sides. If 21 is formed in a desired shape, it may be in contact with each short side of first linear portion 11a and second linear portion 11b, may overlap at a corner, or They may be in contact at corners.

[0023]

According to the present invention, since the bent portion of the gate forming portion is formed shorter or diagonally shorter than the short side of the linear portion, the gate electrode after the lithography process is unnecessarily bulged. Does not occur, and the gate electrode can be formed with a uniform width, so that a reduction in current supply capability can be prevented.

In the pattern layout of the gate forming portion, since the bent portion is formed at an angle of 90 degrees with respect to the linear portion, it is not necessary to introduce a rotary implantation facility, and the cost can be reduced. In addition, it is possible to easily cope with chip shrink.

[Brief description of the drawings]

FIG. 1A is a top view of a pattern layout of a MOS transistor according to a first embodiment of the present invention. FIG. 1B is a MOS transistor after a process such as lithography in the pattern layout according to the first embodiment of the present invention. Top view of

FIG. 2A is a top view of a pattern layout of a MOS transistor according to a second embodiment of the present invention. FIG. 2B is a MOS transistor after a step of lithography or the like in the pattern layout according to the second embodiment of the present invention. Top view of

FIG. 3 is a top view of a pattern layout of a MOS transistor in a modification of the second embodiment according to the present invention;

FIG. 4A is a top view of a pattern layout of a MOS transistor according to a third embodiment of the present invention. FIG. 4B is a MOS transistor after a lithography process or the like in the pattern layout according to the third embodiment of the present invention. Top view of

FIG. 5A is a top view of a pattern layout of a MOS transistor according to a fourth embodiment of the present invention. FIG. 5B is a MOS transistor after a step of lithography or the like in the pattern layout according to the fourth embodiment of the present invention. Top view of

6A is a top view of a pattern layout of a MOS transistor according to the related art; FIG. 6B is a top view of the MOS transistor after a step such as lithography in the pattern layout according to the related art;

7A is a top view of a pattern layout of a MOS transistor according to the related art; FIG. 7B is a top view of the MOS transistor after a step such as lithography in the pattern layout according to the related art;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Gate formation part 11a ... 1st linear part 11b ... 2nd linear part 11c ... Bent part 12 ... Source formation part 13 ... Drain formation part 14 ... Contact 21 ... Gate electrode 22 ... Source electrode 23 ... Drain electrode 24 ... contact

Claims (6)

[Claims] A source forming portion having a contact formed therein; a drain forming portion having a contact formed therein; and a gate forming portion having a first linear portion, a second linear portion, and a bent portion disposed therein. The first straight portion and the second straight portion are parallel to each other, a bent portion is disposed therebetween, and the first straight portion, the second straight portion, and the bent portion are disposed diagonally. Layout of a semiconductor integrated circuit. 2. The first straight line portion and the second straight line portion have a long side and a short side, and the bent portion has a rectangular shape, and the first straight line portion, the second straight line portion, and the bent line. 2. The pattern layout of a semiconductor integrated circuit according to claim 1, wherein a length of a contact portion of the portion is shorter than the short side. 3. The first straight line portion and the second straight line portion include a long side and a short side, and the bent portion has a rectangular shape, and the first straight line portion, the second straight line portion, and the bent line. 2. The pattern layout of a semiconductor integrated circuit according to claim 1, wherein the contact portions of the portions overlap at corners. 4. A semiconductor device comprising: a source forming portion having a contact formed therein; a drain forming portion having a contact formed therein; and a gate forming portion having a first linear portion and a second linear portion disposed therein. A pattern layout of a semiconductor integrated circuit, wherein the first straight portion and the second straight portion are arranged in parallel and diagonally. 5. The first straight portion and the second straight portion include a long side and a short side, and a contact portion between the first straight portion and the second straight portion is shorter than the short side. The pattern layout of a semiconductor integrated circuit according to claim 4, wherein: 6. The first straight portion and the second straight portion each include a long side and a short side, and a contact portion between the first straight portion and the second straight portion overlaps at a corner. The pattern layout of a semiconductor integrated circuit according to claim 4, wherein: