JP2000031144A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the dielectric constant of an interlayer insulating film in the semiconductor device having an embedding wiring embedded in an insulating film, and the manufacturing method thereof. SOLUTION: This semiconductor device is constituted of an insulating film 12 which is formed on a lower substrate 10 and where a via hole 22 reaches a lower substrate 10, an insulating film 18 which is formed on the insulating film 12 where a wiring groove 24 is formed in a region including the region in which the via hole 22 is formed, a stopper film 14 which is selectively formed on the insulating film 12 in the wiring groove 24 and comprises a material having etching characteristics different from those of the insulating film 12 and the insulating film 18, and a wiring layer 30 which is embedded in the wiring groove where the stopper film 14 is formed and in the via hole 22 and connected to the lower substrate 10 via the via hole 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having embedded wiring embedded in an insulating film and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the large scale and high integration of semiconductor integrated circuits, there has been a demand for a wiring layer for interconnecting elements formed on a semiconductor substrate to have low resistance and multilayer wiring. For this reason, in recent years, it is possible to form a wiring layer using Cu (copper) or the like, which is a low-resistance material but does not generate a reactant having a high vapor pressure and is difficult to dry-etch, and furthermore, it is possible to form wiring while maintaining surface flatness. Attention has been focused on a buried interconnect technology that allows easy multilayering. The buried wiring technique is a technique for forming a wiring layer by selectively burying a wiring material in a groove formed in an insulating film.

A conventional method of manufacturing a semiconductor device using embedded wiring will be described with reference to FIGS.
15 and 16 are a plan view and a sectional view showing a conventional method for manufacturing a semiconductor device. First, an interlayer insulating film 102 made of, for example, a silicon oxide film is formed on a base substrate 100 on which predetermined elements and wiring layers have been formed.

Then, a stopper film 104 made of, for example, a silicon nitride film is formed on the interlayer insulating film 102 (FIG. 15A). Subsequently, an opening 106 reaching the interlayer insulating film is formed in the stopper film 104 by using a normal lithography technique and an etching technique (FIG. 15B). The opening 106 includes a predetermined wiring layer (not shown) formed in the base substrate 100 and a wiring layer (not shown) formed in an upper layer.
Are formed in a region where a via hole is to be formed to connect the via holes.

After that, an insulating film having an etching characteristic different from that of the stopper film 104, for example, an interlayer insulating film 108 made of a silicon oxide film is formed on the stopper film 104 in which the opening 106 is formed. Next, a photoresist 110 having a punched pattern corresponding to a pattern of a wiring layer to be formed is formed on the interlayer insulating film 108 by a normal lithography technique (FIG. 15C).

Then, the interlayer insulating film 108 is anisotropically etched using the photoresist 110 and the stopper film 104 as a mask. At this time, since the stopper film 104 does not exist in the formation region of the opening 106, after the interlayer insulating film 102 is exposed in the opening 106, the interlayer insulating film 102 in the opening 106 is etched. Thus,
A via hole 112 is formed in the interlayer insulating film 102 and the interlayer insulating film 1
A wiring groove 114 for embedding a wiring is formed at 08 (FIG. 16A).

Thereafter, a conductive layer 116 for forming a wiring layer is deposited on the entire surface (FIG. 16B). Conductive layer 11
For example, a Cu film deposited by sputtering and plating can be used as 6. Then, for example, CMP
(Chemical Mechanical Polishin
The conductive layer 116 is polished back by the method g) until the interlayer insulating film 106 is exposed, and the conductive layer 116 is selectively left in the via hole 112 and the wiring groove 114.

As described above, in the conventional method for manufacturing a semiconductor device, the semiconductor device is
The wiring layer 118 connected to the wiring layer (not shown) of the underlying substrate 100 via the second substrate 2 was formed (FIG. 16C).

[0009]

In recent years, semiconductor devices have been miniaturized, and the width of wiring has become extremely narrow. The transmission speed of an electric signal transmitted through wiring is large in the dielectric constant of an insulating film around a wiring layer. It is becoming dependent. Therefore, in order to improve the operation performance of the semiconductor device, a material having a lower dielectric constant is required for the insulating film applied to the interlayer insulating film. In addition, it is assumed that the frequency of application of the above-described embedded wiring technology increases in order to improve the wiring yield.

For this reason, when the process of forming the via hole 112 and the wiring groove 114 at the same time as in the above-described conventional method of manufacturing a semiconductor device is employed, the stopper film 10 is required.
4 is required to be sufficiently reduced, but a silicon nitride film having a relatively high dielectric constant is widely applied in order to selectively stop etching of an interlayer insulating film made of a silicon oxide film. Therefore, it was not easy to lower the dielectric constant of the interlayer insulating film. Further, other low dielectric constant materials capable of securing etching selectivity with respect to a silicon oxide film have not been found.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a via hole and a wiring groove are formed at the same time, in which the dielectric constant of an interlayer insulating film can be reduced, and a method of manufacturing the same.

[0012]

The object of the present invention is to provide a first insulating film formed on a base substrate and having a via hole reaching the base substrate, a first insulating film formed on the first insulating film,
A second insulating film in which a wiring groove is formed in a region including the region in which the via hole is formed, and a first insulating film selectively formed on the first insulating film in the wiring groove; A stopper film made of a material having an etching characteristic different from that of the second insulating film; and a wiring embedded in the wiring groove and the via hole in which the stopper film is formed, and connected to the base substrate via the via hole. And a semiconductor device characterized by having a layer. By configuring the semiconductor device in this manner, it is not necessary to form a stopper film on the entire surface between the first insulating film and the second insulating film, so that the dielectric constant of the interlayer insulating film can be reduced. . Thereby, the transmission delay of a signal propagating through the wiring layer can be reduced.

In the above-described semiconductor device, it is preferable that the stopper film has a forward tapered cross section at an end. By configuring the semiconductor device in this manner, an alignment margin in lithography for forming a wiring groove can be easily secured. According to the method of increasing the pattern size of the stopper film in this manner, the stopper film can be patterned at a pitch equal to or smaller than the minimum processing dimension of lithography.

In the above-described semiconductor device, it is preferable that the semiconductor device further includes a side wall film formed of a material having etching characteristics different from those of the first insulating film and the second insulating film, formed on the side wall of the stopper film. . By configuring the semiconductor device in this manner, an alignment margin in lithography for forming a wiring groove can be easily secured. According to the method of substantially enlarging the pattern size of the stopper film in this manner,
The stopper films can be arranged at a pitch smaller than the minimum processing dimension of lithography.

In the above-described semiconductor device, it is preferable that the stopper film has a pattern surrounding a region where the via hole is formed. By configuring the semiconductor device in this manner, the alignment margin with respect to the via hole can be improved. In the above-described semiconductor device, it is preferable that the stopper film is formed of a conductive material.

In the above-described semiconductor device, it is preferable that the stopper film is formed of a non-conductive material. Further, the object is to form a first insulating film on a base substrate, and to etch the first insulating film in a wiring layer forming region except for a via hole forming region on the first insulating film. Forming a stopper film made of a material having a different characteristic, and forming a second insulating film made of a material having a different etching characteristic from the stopper film on the first insulating film on which the stopper film is formed; Etching the first insulating film and the second insulating film in the wiring layer forming region using the stopper film as a mask,
Forming a via hole formed in the first insulating film in the area where the via hole is to be formed, and a wiring groove formed in the second insulating film in the area where the wiring layer is to be formed; Forming a wiring layer buried in the groove and connected to the underlying substrate via the via hole. By manufacturing the semiconductor device in this manner, it is not necessary to form a stopper film on the entire surface between the first insulating film and the second insulating film, so that the dielectric constant of the interlayer insulating film can be reduced. . Accordingly, in a method of manufacturing a semiconductor device in which a via hole and a wiring groove are simultaneously formed, a transmission delay of a signal propagating through a wiring layer can be reduced.

In the method of manufacturing a semiconductor device, in the step of forming the stopper film, the etching condition of the stopper film is controlled to form the stopper film having an end portion having a forward tapered cross section. Is desirable. By manufacturing the semiconductor device in this manner, a positioning margin in lithography for forming a wiring groove can be easily secured. According to the method of increasing the pattern size of the stopper film in this manner, the stopper film can be patterned at a pitch equal to or smaller than the minimum processing dimension of lithography.

In the method of manufacturing a semiconductor device described above, after the step of forming the stopper film, the first insulating film and the second insulating film have different etching characteristics on a side wall of the stopper film. It is desirable to further include a step of forming a sidewall film made of a material. By manufacturing the semiconductor device in this manner, a positioning margin in lithography for forming a wiring groove can be easily secured. According to the method of substantially enlarging the pattern size of the stopper film in this manner, the stopper films can be arranged at a pitch equal to or smaller than the minimum processing dimension of lithography.

In the above-described method for manufacturing a semiconductor device, it is preferable that, in the step of forming the stopper film, the stopper film having a pattern surrounding the region where the via hole is to be formed be formed. By manufacturing the semiconductor device in this manner, the alignment margin for the via hole can be improved.

[0020]

[First Embodiment] A semiconductor device according to a first embodiment of the present invention and a method for fabricating the same will be described with reference to FIG.
This will be described with reference to FIGS. FIG. 1 is a plan view and a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS.
Is a process sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 1 (a)
Is a plan view showing the structure of the semiconductor device according to the present embodiment, and FIG. 1B is a cross-sectional view taken along the line XX ′ of FIG. An interlayer insulating film 12 is formed on a base substrate 10 on which predetermined elements and wiring layers have been formed. Via holes 22 are formed in the interlayer insulating film 12 to lead out wiring from a predetermined wiring layer (not shown) formed on the base substrate 10. On the interlayer insulating film 12, an interlayer insulating film 18 is formed. A wiring groove 24 for embedding a wiring is formed in the interlayer insulating film 18. On the interlayer insulating film 12 in the wiring groove 24 in a region where the via hole 22 is not formed,
A stopper film 14 is formed. In the via hole 22 and the wiring groove 24 on the stopper film 14, the underlying substrate 10
The wiring layer 30 connected to the wiring layer (not shown) is formed.

As described above, in the semiconductor device according to the present embodiment, the stopper film 14 is formed by the interlayer insulating film 12 and the interlayer insulating film 18.
Are not formed on the entire surface between the wiring layers 30 and are formed only in the lower region of the wiring layer 30 excluding the region where the via hole 22 is formed. By reducing the region where the stopper film 14 is formed, the interlayer insulating films 12 to 12 are formed.
18 can be lowered, and the wiring layer 3
Signal transmission delay such as 0 can be reduced.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. In each drawing, the upper side is a plan view, and the lower side is a cross-sectional view taken along line XX ′ of the plan view. First, an interlayer insulating film 12 is formed on a base substrate 10 on which predetermined elements and wiring layers have been formed. For example, an interlayer insulating film 12 made of a silicon oxide film having a thickness of about 700 nm is formed by a plasma CVD method. The base substrate 10 may be a semiconductor substrate on which a predetermined element such as a MOS transistor is formed, or a semiconductor substrate on which one or more metal wiring layers are already formed. You may.

Next, a stopper film 14 is formed on the interlayer insulating film 12 (FIG. 2A). For example, the stopper film 14 of a silicon nitride film having a thickness of about 50 nm is formed by the CVD method. Note that the stopper film 14 may be any material that can provide etching selectivity with respect to the interlayer insulating film 12, and may be another film such as a silicon oxynitride film.

Subsequently, a photoresist 16 is formed on the stopper film 14 by a usual lithography technique. For example, an excimer resist having a thickness of about 700 nm is applied, and then exposed and developed to form a photoresist 16. The photoresist 16 is left in the wiring layer formation region except for the via hole formation region (FIG. 2B).

FIG. 2B shows a case where the stopper film 14 is patterned to have the same size as a wiring layer to be formed later. However, the pattern size is increased by that amount in consideration of a lithography alignment margin. It is desirable to keep. Note that the alignment margin can be secured by other methods. Examples thereof will be shown in embodiments described later.

Thereafter, the stopper film 14 is selectively etched with respect to the interlayer insulating film 12 using the photoresist 16 as a mask (FIG. 2C). For example, using RIE etcher, CHF ₃ flow rate is 60 cc, O ₂ flow rate is 10 c.
c, dry etching with RF power of 200 W, pressure of 40 mTorr, and stage chiller temperature of 20 ° C.

Next, the patterned stopper film 14 is formed.
An interlayer insulating film 18 is formed on the interlayer insulating film 12 on which is formed (FIG. 3A). For example, an interlayer insulating film 18 made of a silicon oxide film having a thickness of 400 nm is formed by a plasma CVD method. Subsequently, a photoresist 20 is formed on the interlayer insulating film 18 by a normal lithography technique (FIG. 3B). For example, an excimer resist having a thickness of about 700 nm is applied, and then exposed and developed to form a photoresist 20. The photoresist 20 is a cut pattern corresponding to the pattern of the wiring layer to be formed.

Thereafter, the interlayer insulating films 18 and 12 are anisotropically etched using the photoresist 20 and the stopper film 14 as a mask. Thus, the via hole 22 is formed in the interlayer insulating film 12 and the wiring groove 24 is formed in the interlayer insulating film 18.
(C), FIG. 4 (a)). Next, pre-cleaning is performed before forming a wiring layer in the via hole 22 and the wiring groove 24. For example, using a two-frequency parallel plate RIE apparatus, the interlayer insulating film is etched by about 7 nm with an Ar gas, a source power of 1500 W, a bias power of 160 W and a pressure of 0.4 mTorr.

Subsequently, a barrier metal 26 is formed on the entire surface. For example, a Ti film having a thickness of about 20 nm is formed by CVD.
A barrier metal 26 made of an N film is formed. Thereafter, a metal film 28 serving as a wiring layer is formed on the barrier metal (FIG. 4B). For example, a film thickness of about 10
After depositing a 0 nm Cu film as a seed layer, a Cu film having a thickness of about 1000 nm is plated to form a metal film 28 made of a Cu film.

Next, the metal film thus deposited is polished back by, for example, the CMP method, and the barrier metal 26 and the metal film 28 are left in the via holes and the wiring grooves. Thus, the via hole 2 is buried in the wiring groove 24.
2, a wiring layer 3 composed of a barrier metal 26 and a metal film 28,
0 is formed (FIG. 4C). In the above example, C
By polishing back the u film about 600 nm,
The Cu film can be selectively left in the via hole 22 and the wiring groove 24.

As described above, according to the present embodiment, the stopper film 14 is not formed on the entire surface between the interlayer insulating film 12 and the interlayer insulating film 18 and the lower region of the wiring layer 30 excluding the region where the via hole 22 is formed. , The dielectric constant of the interlayer insulating film can be reduced. Thereby, the signal transmission delay of the wiring layer 30 and the like can be reduced. In the semiconductor device and the method of manufacturing the same according to the present embodiment, the stopper film 14 is not formed on the entire surface between the interlayer insulating film 12 and the interlayer insulating film 18, and the wiring layer 3 excluding the region where the via hole 22 is formed is formed.
Since it is formed only in the lower region of 0, it does not necessarily need to be formed of an insulating film. That is, the interlayer insulating films 12, 1
A conductive material may be used as long as the material can obtain the etching selectivity with the insulating film constituting 8. For example, TiN
A conductive material that is compatible with the interlayer insulating films 12 and 18 and the wiring layer 30, such as a film, can be used.

[Second Embodiment] The semiconductor device and the method for fabricating the same according to a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. The same components as those of the semiconductor device according to the first embodiment and the method of manufacturing the same are denoted by the same reference numerals, and description thereof will be omitted or simplified. FIG. 5 is a plan view and a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 6 and 7 are process sectional views showing the method of manufacturing the semiconductor device according to the present embodiment.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 5 (a)
Is a plan view showing the structure of the semiconductor device according to the present embodiment, and FIG. 5B is a cross-sectional view taken along the line XX ′ of FIG. 5A. The semiconductor device according to the present embodiment has the same basic structure as that of the semiconductor device according to the first embodiment shown in FIG. 1, but the cross-sectional shape of the end portion of the stopper film 14 remaining under the wiring layer 30 has a forward taper. (Fig. 5
(B)). By providing the end of the stopper film 14 with a forward taper, a positioning margin can be secured in the lithography process in the process of forming the wiring groove 24.

Hereinafter, the method for fabricating the semiconductor device according to the present embodiment will be described in detail along the fabrication steps. First, for example, in the same manner as in the method for manufacturing the semiconductor device according to the first embodiment shown in FIG.
2. A stopper film 14 is formed (FIG. 6A).

Next, a photoresist 16 is formed on the stopper film 14 by a usual lithography technique. For example, an excimer resist having a thickness of about 700 nm is applied, and then exposed and developed to form a photoresist 16. The photoresist 16 is left in the wiring layer formation region except for the via hole formation region. Further, the photoresist is not left in a predetermined range surrounding the peripheral portion of the region where the via hole is to be formed. That is, as compared with the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. 2B, the pattern is a pattern required when the area where the via hole is to be formed is enlarged by a predetermined size. Here, the predetermined size corresponds to the length of the tapered region of the stopper film 14 formed in a later step.

Subsequently, the stopper film 14 is selectively etched using the photoresist 16 as a mask. On this occasion,
The etching conditions are set so that the cross-sectional shape of the end of the stopper film 14 is processed into a forward taper. For example, using a RIE etcher, the flow rate of CHF ₃ is 60 cc, and the flow rate of O ₂ is 3
0cc, RF power 200W, pressure 20mTorr
When the stopper film made of a silicon nitride film is etched by setting the temperature of the stage chiller to -20 ° C., a taper having a length of about 0.15 to 0.3 μm can be formed at the periphery of the stopper film 14 (FIG. 6 ( b)). Note that the forward taper referred to in this specification refers to a state in which the angle between the side surface of the stopper film 14 and the surface of the interlayer insulating film 12 is an acute angle.

The angle of the taper provided at the peripheral portion of the stopper film 14 can be adjusted by controlling the etching conditions. It is desirable that the angle of the taper be appropriately selected within a sufficient range as an alignment margin such as alignment accuracy required for lithography. Note that the method of providing the forward taper in the cross-sectional shape of the end portion of the stopper film 14 as in the present embodiment has an advantage compared to the method of enlarging the pattern size of the stopper film 14 itself. That is, when the patterns of the stopper films 14 are adjacent to each other,
In the method of enlarging the pattern size, the pitch between patterns of the stopper film 14 also needs to be narrowed, and the pitch between patterns may be smaller than the minimum extraction width in lithography. However, such a problem does not occur in the method of providing a forward taper in the cross-sectional shape of the end portion of the stopper film 14 by controlling the etching conditions, and even if the line and space become more severe in the future, photolithography,
A process margin for etching can be increased.

Thereafter, the photoresist 16 is removed, and an interlayer insulating film 18 is formed on the interlayer insulating film 12 on which the patterned stopper film 14 has been formed (FIG. 6C). For example, an interlayer insulating film 18 made of a silicon oxide film having a thickness of 400 nm is formed by a plasma CVD method. Next, the interlayer insulating film 18 is formed by a normal lithography technique.
A photoresist 20 is formed thereon. For example, a film thickness of about 7
After excimer resist of 00 nm is applied, exposure and development are performed to form a photoresist 20. Photoresist 2
0 is a blank pattern corresponding to the pattern of the wiring layer (FIG. 7A).

Note that the stopper film 14 is processed to have a forward tapered cross-sectional shape at the end and is larger than the pattern of the wiring layer. Therefore, even if a slight misalignment occurs when the photoresist 20 is formed. The pattern edge of the photoresist 20 is located above the stopper film 14. In other words, the inside of the pattern in which the photoresist 20 is removed is covered with the stopper film 14 except for the region where the via hole is to be formed.

Subsequently, the interlayer insulating films 12 and 18 are anisotropically etched using the photoresist 20 and the stopper film 14 as a mask. As a result, a via hole 22 is formed in the interlayer insulating film 12 and a wiring groove 24 is formed in the interlayer insulating film 18 (FIG. 7B). For example, using an ICP etcher, C ₄ F ₈
/ CH ₂ F ₂ / Ar gas, a source power of 2000 W, a bias power of 1400 W, a pressure of 10 mTorr, a stage chiller temperature of 10 ° C., and an interlayer insulating film 12, 1.
8 is etched.

Thereafter, for example, FIGS. 4 (a) to 4 (c)
A wiring layer 30 buried in the wiring groove 24 and connected to the wiring layer (not shown) of the underlying substrate 10 via the via hole 22 is formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. (FIG. 7 (c)). As described above, according to the present embodiment, since the cross-sectional shape of the end portion of the stopper film 14 is processed to have a forward taper, it is possible to secure a lithography alignment margin when forming the wiring groove 24.

In the above embodiment, a silicon nitride film is used as the stopper film 14, but the interlayer insulating films 12, 1
Another film may be used as long as the film has different etching characteristics from the film 8. For example, as described in the first embodiment, a SiON film or a TiN film can be applied. [Third Embodiment] The semiconductor device and the method for fabricating the same according to a third embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first and second embodiments and the method of manufacturing the same are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 8 is a plan view and a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 9 and 10 are plan views and sectional views showing the method of manufacturing the semiconductor device according to the present embodiment. First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 8A is a plan view showing the structure of the semiconductor device according to the present embodiment, and FIG.
FIG. 9B is a sectional view taken along line XX ′ of FIG.

As shown in FIG. 8, in the semiconductor device according to the present embodiment, the stopper film 14 remaining under the wiring layer 30 is formed.
Is characterized in that a sidewall insulating film 32 having an etching characteristic substantially equal to that of the stopper film 14 is formed on the peripheral portion of the substrate. By providing the side wall insulating film 32 on the peripheral portion of the stopper film 14 as described above, it is possible to secure an alignment margin in the lithography process in the process of forming the wiring groove 24.

Hereinafter, the method for fabricating the semiconductor device according to the present embodiment will be described in detail along the fabrication steps. First, for example, in the same manner as the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 2A to 2C,
An interlayer insulating film 12 and a stopper film 14 are formed (FIG. 9)
(A)).

Next, a photoresist 16 is formed on the stopper film 14 by a usual lithography technique. For example, an excimer resist having a thickness of about 700 nm is applied, and then exposed and developed to form a photoresist 16. The photoresist 16 is not left in a predetermined range surrounding the periphery of the region where the via hole 22 is to be formed, as in the case of the method for manufacturing a semiconductor device according to the second embodiment. Here, the predetermined range corresponds to a formation region of the sidewall insulating film 32 formed in the peripheral portion of the stopper film 14 in a later step.

Subsequently, the stopper film 14 is selectively etched using the photoresist 16 as a mask (FIG. 9).
(B)). After removing the photoresist 16,
An insulating film having substantially the same etching characteristics as the stopper film 14 is formed. For example, the film thickness is about 50 n by the CVD method.
An m-th silicon nitride film is formed.

Next, the silicon nitride film thus formed is subjected to anisotropic etching to leave an insulating film only on the side wall of the stopper film 14. Thus, the side wall insulating film 32 is formed on the peripheral portion of the stopper film 14 (FIG. 9C). For example, the reaction gas is CF ₄ / Ar gas, and the RF power is 500
W, a pressure of 1500 mTorr, a stage chiller temperature of 0 ° C., and a 50 nm-thick silicon nitride film are etched to form a width of about 0.03 to
The sidewall insulating film 32 of 0.05 μm can be formed.

The stopper film 14 as in this embodiment is used.
The method in which the sidewall insulating film 32 is provided on the peripheral portion has an advantage as compared with the method in which the pattern size of the stopper film 14 is increased. That is, when the patterns of the stopper film 14 are adjacent to each other, the method of enlarging the pattern size requires that the pitch between the patterns of the stopper film 14 also be reduced, and the pitch between the patterns may be smaller than the minimum width of lithography. There is. However, the method of forming the side wall insulating film 32 on the peripheral portion of the stopper film 14 does not have such a problem, and a process margin for photolithography and etching can be increased even if line and space become more severe in the future.

Subsequently, the patterned stopper film 14 is formed.
An interlayer insulating film 18 is formed on the interlayer insulating film 12 on which is formed. For example, a film thickness of 400 n
Then, an interlayer insulating film 18 made of a silicon oxide film is formed. Thereafter, a photoresist 20 is formed on the interlayer insulating film 18 by a normal lithography technique. For example,
After an excimer resist having a thickness of about 700 nm is applied, exposure and development are performed to form a photoresist. The photoresist is a blank pattern corresponding to the pattern of the wiring layer (FIG. 10A).

Since the sidewall insulating film 32 is formed on the peripheral portion of the stopper film 14 and is substantially larger than the pattern of the wiring layer, a slight misalignment occurs when the photoresist 20 is formed. Occurs, the pattern edge of the photoresist 20 is located above the stopper film 14 or the sidewall insulating film 32. That is, the photoresist 2
The inside of the pattern of “0” is covered with the stopper film 14 or the sidewall insulating film 32 except for the region where the via hole is to be formed.

Next, using the photoresist 20, the stopper film 14, and the side wall insulating film 32 as a mask, the interlayer insulating film 1 is formed.
8 and 12 are anisotropically etched. As a result, a via hole 22 is formed in the interlayer insulating film 12 and a wiring groove 24 is formed in the interlayer insulating film 18 (FIG. 10B). For example, by using an ICP etcher, the interlayer insulating films 12 and 18 are etched with a C ₄ F ₈ / CH ₂ F ₂ / Ar gas, a source power of 2000 W, a bias power of 1400 W, a pressure of 10 mTorr and a stage chiller temperature of 10 ° C. I do.

Thereafter, for example, FIGS. 4 (a) to 4 (c)
A wiring layer 30 buried in the wiring groove 24 and connected to the wiring layer (not shown) of the underlying substrate 10 via the via hole 22 is formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. (FIG. 10 (c)). As described above, according to the present embodiment, the sidewall insulating film 32 having substantially the same etching characteristics as the stopper film 14 is provided at the peripheral portion of the stopper film 14, so that the lithography alignment margin in forming the wiring groove 24 is secured. can do.

In the above embodiment, the stopper film 14,
Although the silicon nitride film is applied as the sidewall insulating film 32, any other film may be used as long as it has a different etching characteristic from the interlayer insulating films 12 and 18. For example, as described in the first embodiment, a SiON film or a TiN film can be applied. [Fourth Embodiment] The semiconductor device and the method for fabricating the same according to a fourth embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first to third embodiments and the method of manufacturing the same are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 11 is a plan view and a sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 12 and 13 are process sectional views showing the method of manufacturing the semiconductor device according to the present embodiment. In the method of manufacturing the semiconductor device according to the first to third embodiments, the pattern of the via hole 22 is defined by the stopper film 14 and the wiring groove 24. That is, the end of the via hole 22 located in the direction in which the wiring layer 30 extends (horizontal direction in the drawing) is defined by the stopper film 14, and the end of the via hole 22 located in the direction crossing the wiring layer 30 (vertical direction in the drawing). The part is defined by the wiring groove 24.
Therefore, in the semiconductor device according to the first embodiment shown in FIG. 1, the alignment margin in the direction in which the wiring layer 30 extends is sufficient, but the alignment margin in the direction intersecting with the wiring layer 30 is not always sufficient. The present embodiment provides a semiconductor device and a method for manufacturing the same, which can secure an alignment margin in any direction.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. Note that FIG.
FIG. 11A is a plan view illustrating the structure of the semiconductor device according to the present embodiment, and FIG. 11B is a cross-sectional view taken along line XX ′ of FIG. In the semiconductor device according to the present embodiment, as shown in FIG. 11, the stopper film 14 is formed in the lower region of the wiring layer 30 excluding the region where the via hole 22 is formed, and in the via hole 2.
It is characterized in that it is formed in a region surrounding 2. By providing the stopper film 14 also in the region surrounding the via hole 22, the alignment margin with respect to the via hole 22 can be improved.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained. First, the interlayer insulating film 12 and the etching stopper film 14 are formed on the base substrate 10 in the same manner as in, for example, the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. 2A (FIG. 12A). . Then
A photoresist 16 is formed on the stopper film 14 by a usual lithography technique. For example, a film thickness of about 700
After applying an excimer resist of nm, it is exposed and developed,
A photoresist 16 is formed. Photoresist 16
Are formed in the region where the wiring layer is to be formed except for the region where the via hole 22 is to be formed, as in the case of the method of manufacturing the semiconductor device according to the first embodiment, and are also formed in the region surrounding the region where the via hole 22 is to be formed ( FIG. 12 (b).

Subsequently, the stopper film 14 is selectively etched using the photoresist 16 as a mask (FIG. 12).
(C)). After removing the photoresist 16, an interlayer insulating film 18 is formed on the interlayer insulating film 12 on which the patterned stopper film 14 is formed. For example, plasma CVD
By the method, an interlayer insulating film 18 made of a silicon oxide film having a thickness of 400 nm is formed.

Subsequently, a photoresist 20 is formed on the interlayer insulating film 18 by a usual lithography technique. The photoresist 20 is a blank pattern corresponding to the pattern of the wiring layer 30 (FIG. 13A). The region where the via hole 22 is to be formed is defined by the stopper film 14 and the wiring groove 24. However, in the method of manufacturing the semiconductor device according to the present embodiment, since the stopper film 14 surrounding the region where the via hole 22 is formed is formed, Resist 20
Can be improved at the time of forming the alignment.

Thereafter, the interlayer insulating film 18 is anisotropically etched using the photoresist 20 and the stopper film 14 as a mask to form a via hole 22 in the interlayer insulating film 12 and a wiring groove 24 in the interlayer insulating film 18 (FIG. 13). (B)). Then, for example, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS.
4 and embedded in the underlying substrate 10 through the via hole 22.
The wiring layer 30 connected to the wiring layer (not shown) is formed.

As described above, according to the present embodiment, since the stopper film 14 surrounding the region where the via hole 22 is to be formed is formed in advance, the alignment margin with respect to the via hole 22 can be improved. In the above embodiment,
Although the annular stopper film 14 is provided so as to surround the via hole 22, it is not always necessary to form the annular stopper film. For example, the first
The stopper film 14 in the semiconductor device according to the embodiment
As shown in FIG. 14, the same effect as in the present embodiment can be obtained only by adding a pattern surrounding the upper and lower sides of the via hole 22.

In the above embodiment, an example in which the present invention is applied to the semiconductor device according to the first embodiment has been described.
The same can be applied to the semiconductor device according to the embodiment.

[0064]

As described above, according to the present invention, a first insulating film formed on a base substrate and having a via hole reaching the base substrate is formed, and a via hole formed on the first insulating film is formed on the first insulating film. A second insulating film having a wiring groove formed in a region including the formed region; and a first insulating film and a second insulating film selectively formed on the first insulating film in the wiring groove. The semiconductor device is composed of a stopper film made of a material having a different etching characteristic and a wiring layer embedded in the wiring groove and the via hole in which the stopper film is formed and connected to the underlying substrate through the via hole. It is not necessary to form a stopper film on the entire surface between the insulating film and the second insulating film. Thus, the dielectric constant of the interlayer insulating film can be reduced, and the transmission delay of a signal propagating through the wiring layer can be reduced.

Further, according to the present invention, the first substrate is provided on the underlying substrate.
Forming a stopper film made of a material having a different etching characteristic from that of the first insulating film in a wiring layer forming region other than a via hole forming region on the first insulating film; Forming a second insulating film made of a material having a different etching characteristic from that of the stopper film on the first insulating film on which the stopper film is formed; and forming a first insulating film in a region where a wiring layer is to be formed using the stopper film as a mask. The film and the second insulating film are etched to form a first hole in a region where a via hole is to be formed.
Forming a via hole formed in the insulating film and a wiring groove formed in the second insulating film in a region where a wiring layer is to be formed; and filling the via hole and the wiring groove with the underlying substrate via the via hole. Since the semiconductor device is manufactured by the method of manufacturing a semiconductor device by the step of forming a wiring layer connected to the semiconductor device, it is not necessary to form a stopper film on the entire surface between the first insulating film and the second insulating film. Accordingly, in the method of manufacturing a semiconductor device in which the via hole and the wiring groove are formed simultaneously, the dielectric constant of the interlayer insulating film can be reduced, and the transmission delay of a signal propagating through the wiring layer can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a sectional view, respectively, showing the structure of a semiconductor device according to a first embodiment of the present invention;

2A and 2B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 1);

3A and 3B are a plan view and a sectional view, respectively, showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 2);

4A and 4B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention (part 3);

FIGS. 5A and 5B are a plan view and a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment;

6A and 6B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention (part 1).

7A and 7B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention (part 2).

FIGS. 8A and 8B are a plan view and a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment;

9A and 9B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention (part 1).

10A and 10B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention (part 2).

FIGS. 11A and 11B are a plan view and a cross-sectional view illustrating a structure of a semiconductor device according to a fourth embodiment;

12A and 12B are a plan view and a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment (Part 1).

13A and 13B are a plan view and a sectional view illustrating the method for manufacturing a semiconductor device according to the fourth embodiment (Part 2).

14A and 14B are a plan view and a cross-sectional view illustrating a structure and a method of manufacturing a semiconductor device according to a modification of the fourth embodiment.

FIG. 15 is a plan view and a cross-sectional view (part 1) illustrating a conventional method for manufacturing a semiconductor device.

FIG. 16 is a plan view and a cross-sectional view (part 2) illustrating a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Base board 12 ... Interlayer insulating film 14 ... Stopper film 16 ... Photoresist 18 ... Interlayer insulating film 20 ... Photoresist 22 ... Via hole 24 ... Wiring groove 26 ... Barrier metal 28 ... Metal film 30 ... Wiring layer 32 ... Side wall insulating film REFERENCE SIGNS LIST 100 base substrate 102 interlayer insulating film 104 stopper film 106 interlayer insulating film 110 photoresist 112 via hole 114 wiring groove 116 conductive layer 118 wiring layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F033 AA15 AA19 AA28 AA29 AA64 AA66 BA15 BA25 EA03 EA22 EA25 EA32 FA03

Claims (10)

[Claims] A first insulating film formed on a base substrate and having a via hole reaching the base substrate; and a region including a region formed on the first insulating film and having the via hole formed therein. A second insulating film in which a wiring groove is formed; and a second insulating film selectively formed on the first insulating film in the wiring groove, the etching characteristics of the first insulating film and the second insulating film being different from those of the first insulating film and the second insulating film. A semiconductor, comprising: a stopper film made of a different material; and a wiring layer embedded in the wiring groove and the via hole in which the stopper film is formed and connected to the base substrate via the via hole. apparatus. 2. The semiconductor device according to claim 1, wherein the stopper film has a forward tapered cross section at an end. 3. The semiconductor device according to claim 1, further comprising a side wall film formed on a side wall portion of said stopper film and made of a material having an etching characteristic different from that of said first insulating film and said second insulating film. A semiconductor device characterized by the above-mentioned. 4. The semiconductor device according to claim 1, wherein the stopper film has a pattern surrounding a region where the via hole is formed. 5. The semiconductor device according to claim 1, wherein the stopper film is formed of a conductive material. 6. The semiconductor device according to claim 1, wherein said stopper film is formed of a non-conductive material. 7. A step of forming a first insulating film on an undersubstrate; and forming the first insulating film and an etching characteristic on a wiring layer forming region other than a via hole forming region on the first insulating film. Forming a stopper film made of a different material; and forming a second insulating film made of a material having a different etching characteristic from the stopper film on the first insulating film on which the stopper film is formed. Using the stopper film as a mask, etching the first insulating film and the second insulating film in the region where the wiring layer is to be formed, and forming a via hole formed in the first insulating film in the region where the via hole is to be formed; Forming a wiring groove formed in a second insulating film in the wiring layer formation planned region; and forming the wiring groove in the via hole and the wiring groove, and forming the wiring groove in the base substrate through the via hole. The method of manufacturing a semiconductor device characterized by a step of forming a connection to the wiring layer. 8. The method for manufacturing a semiconductor device according to claim 7, wherein, in the step of forming the stopper film, etching conditions for the stopper film are controlled to remove the stopper film having a forward tapered cross-sectional shape at an end. A method for manufacturing a semiconductor device, comprising: 9. The method according to claim 7, wherein after the step of forming the stopper film, the first insulating film and the second insulating film are etched on a side wall of the stopper film. A method for manufacturing a semiconductor device, further comprising a step of forming a sidewall film made of materials having different characteristics. 10. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the stopper film, the stopper film having a pattern surrounding the via hole formation planned region is formed. A method of manufacturing a semiconductor device.