JP2000030476A - Nonvolatile semiconductor storage and threshold voltage writing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the write-in of a threshold voltage whose accuracy is high and which has good efficiency by performing the write-in of the threshold voltage while lowering a write voltage to be impressed on the drain terminal of a nonvolatile memory cell. SOLUTION: At the time of writing a threshold voltage to a nonvolatile memory 1, a pulse voltage corresponding to an initial write voltage is impressed on a bit line 4 by outputting a high initial write voltage from an initial voltage generating circuit 6 while turning the switch 7a of a drain voltage control circuit 7 on and operating transistors 9,10 for controlling the inputting of a pulse and the inputting of a write voltage. Here, the pulse voltage is impressed on a memory cell 1 in which a threshold voltage is to be written as a drain electrode. During the impressing of the voltage, the movement of electrons is generated from the source electrode of the cell to the drain electrode of the cell and one part of the electrons pierces a tunnel oxidized film to perform the injecting of charge to a floating gate of the cell. After the outputting of this high voltage initial write pulse is repeated by a prescribed times, the cumulative write voltage of the cell 1 is set to a prescribed threshold voltage by repeating a write-in with a standard write voltage while changing over the switch 7a to a switch 7b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a nonvolatile memory cell and a threshold voltage writing method, and more particularly to a method for writing a predetermined threshold voltage to a nonvolatile memory cell accurately and efficiently. It is related to the improvement of.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a partial configuration of a conventional nonvolatile semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 7-249294. In the figure, 1, 2, 3
Is a nonvolatile memory cell having a floating gate, a word line connected to the gate electrode and a transistor grounded at the source electrode, and 4 is the drain of these nonvolatile memory cells 1, 2, 3 A bit line 29 connected to the electrodes; 29, a pulse generating circuit for generating a write pulse; 8, a high-voltage side power supply terminal;
Reference numerals 10, 11, and 12 denote control transistors each having a drain electrode and a source electrode connected in series between the high-voltage side power supply terminal 8 and the bit line 4, respectively. Is applied to one of the (9) gate electrodes.

Next, the operation will be described. When a write pulse is output from the pulse generation circuit 29, a write voltage corresponding to the write pulse is applied to the bit line 4 and the drain voltages of the nonvolatile memory cells 1, 2, and 3. Since the high-voltage side power supply voltage is supplied to the gate electrode of the nonvolatile memory cell (for example, 1) for writing, a part of the hot electrons moving from the gate electrode to the drain electrode in response to the application of the write pulse. Is injected into the floating gate through the tunnel oxide film. And
By supplying the write pulse several times, a predetermined amount of charge is accumulated in the floating gate, and thereby a predetermined read threshold voltage is set.

FIG. 8 is a write characteristic diagram showing the relationship between the cumulative number of write pulses and the read threshold voltage in such a conventional nonvolatile semiconductor memory device. In the figure, the horizontal axis represents the cumulative number of write pulses, and the vertical axis represents the read threshold voltage. As shown in the figure, each time a write pulse is supplied, the read threshold voltage increases, and finally, the cumulative write voltage increases until a desired threshold voltage is obtained.

[0005]

Since the conventional nonvolatile semiconductor memory device and the threshold voltage writing method are configured as described above, the voltage for controlling the writing used in a series of writing is constant. As a result, when trying to suppress the variation in the threshold voltage, a series of write operations is repeated using a write pulse having a low voltage, resulting in a longer write time, and conversely, a longer write time. In the case of suppressing it, there is a problem in that a series of write operations is repeated using a write pulse having a high voltage, thereby causing a variation in threshold voltage to become apparent.

In a case where a screening test is performed by baking for a volatile defect of the nonvolatile semiconductor memory device, the voltage difference between the test voltage and the threshold voltage of each of the nonvolatile memory cells 1, 2, and 3 is extremely small. Since it is necessary to set (it is necessary to make the writing depth shallow), it is necessary to keep the voltage variation of the cumulative writing voltage of the nonvolatile memory cells 1, 2, 3 very small.
A very long writing time was required. In a general non-volatile semiconductor memory device, such a screening test is performed at each manufacturing stage, for example, at a wafer stage, a chip stage, a packaging stage, and the like. Is a serious problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a nonvolatile semiconductor memory device and a threshold voltage capable of accurately and efficiently writing a predetermined threshold voltage to a nonvolatile memory cell. The purpose is to obtain a writing method.

[0008]

A threshold voltage writing method according to the present invention is a threshold voltage writing method for writing a threshold voltage to a nonvolatile memory cell of a nonvolatile semiconductor memory device. This is to write the threshold voltage to the nonvolatile memory cell while temporarily reducing the applied write voltage.

A nonvolatile semiconductor memory device according to the present invention comprises: a nonvolatile memory cell; a standard voltage generating circuit for outputting a standard write voltage used when writing a threshold voltage to the nonvolatile memory cell; One or a plurality of initial voltage generating circuits for outputting an initial write voltage higher than a write voltage, and the standard write voltage and the one or a plurality of initial write voltages are inputted, and the nonvolatile memory cells are switched by switching these write voltages. And a drain voltage control circuit for supplying the voltage to the drain terminal and for reducing the voltage of the drain terminal for a while.

In a nonvolatile semiconductor memory device according to the present invention, a cumulative write voltage of a nonvolatile memory cell is inputted,
A switching signal generating circuit is provided for outputting a switching signal when the cumulative writing voltage exceeds a provisional threshold voltage lower than the target threshold voltage, and a drain voltage control circuit supplies the switching signal to the drain terminal of the nonvolatile memory cell based on the switching signal. This is for switching the write voltage.

[0011] The nonvolatile semiconductor memory device according to the present invention counts the number of times of writing by the initial voltage generating circuit,
An initial write monitor circuit for outputting an initial write control signal according to the count value is provided, and the drain voltage control circuit changes a write voltage used at the time of the initial write based on the initial write control signal.

A nonvolatile semiconductor memory device according to the present invention includes an initial write information memory for storing an initial write control signal, and the drain voltage control circuit performs the above-described operation based on the initial write control signal stored in the initial write information memory. This is for selecting a write voltage to be used at the time of initial writing.

A nonvolatile semiconductor memory device according to the present invention includes a nonvolatile memory cell, one or more transistors connected between a drain terminal of the nonvolatile memory cell and a power supply voltage, A drain voltage control terminal connected to the gate of one of the transistors.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention. In the figure, reference numerals 1, 2, and 3 denote nonvolatile memory cells each having a floating gate, a transistor having a gate electrode connected to a word line and a source electrode grounded, and 4 represents a plurality of nonvolatile memories. Reference numeral 5 denotes a bit line connected to the drain electrodes of the cells 1, 2, and 3, and 5 denotes a standard write voltage at which the nonvolatile memory cells 1, 2, and 3 can be written to a threshold voltage with a predetermined voltage variation accuracy. Output standard voltage generator,
Reference numeral 6 denotes an initial voltage generating circuit that outputs an initial write voltage higher than the standard write voltage, 7 denotes a drain voltage control circuit having two switches 7a and 7b to which the standard write voltage and the initial write voltage are input, and 8 denotes a high voltage side. Power terminal,
Reference numerals 9, 10, 11 and 12 denote the high-voltage power supply terminals 8 respectively.
A control transistor 13 having a drain electrode and a source electrode connected in series between the bit line 4 and the bit line 4, and a sense amplifier 13 connected to the bit line 4. Also,
A voltage pulse is input to the gate electrode of the control transistor 9 as a write enable signal, a write voltage is input to the gate electrode of the control transistor 10, and the select signal of the bit line is input to the control transistor 12 and the gate electrode of the control transistor 12. In the following, the control transistor 9 is a pulse input control transistor (transistor), the control transistor 10 is a write voltage input control transistor (a drain voltage control circuit, a transistor), and the control transistor 11 and the control transistor 12 are each selectively controlled. It is called a transistor.

Next, the operation will be described. First, an operation of writing a threshold voltage to the nonvolatile memory cell 1 will be described. At this time, the first power supply voltage higher than the initial write voltage is supplied to the high-voltage side power supply terminal 8 and the gate electrode of the nonvolatile memory cell 1, and the gate electrodes of the other nonvolatile memory cells 2 and 3 are supplied with the initial power supply voltage. A second power supply voltage lower than the write voltage is supplied. A select signal is input to the select control transistors 11 and 12.

In such a setting state, the drain voltage control circuit 7 first turns on the switch 7a connected to the initial voltage generation circuit 6 to output a high initial write voltage and write it to the pulse input control transistor 9. Input a pulse as a permission signal. As a result, the pulse input control transistor 9 and the write voltage input control transistor 10 operate, and a pulse voltage corresponding to the initial write voltage is applied to the bit line 4. Then, in the nonvolatile memory cell 1 where writing is performed, the above-mentioned pulse voltage is applied as the drain electrode, so that hot electrons move from the source electrode to the drain electrode while the pulse voltage is applied. ,
Some of the hot electrons penetrate through the tunnel oxide film and charge is injected into the floating gate.
On the other hand, in the non-volatile memory cells 2 and 3 where writing is not performed, since a low voltage is applied to the gate electrodes, some of the hot electrons do not penetrate through the tunnel oxide film, and charge injection into the floating gate is not performed. Not done.

After repeating the output of the high voltage initial write pulse a predetermined number of times, the drain voltage control circuit 7
Switches the switch to be ON-controlled from the switch 7a to the switch 7b, and outputs a low standard write voltage. Then, writing with this standard writing voltage is repeated,
The cumulative write voltage of the written nonvolatile memory cell 1 is set to a predetermined threshold voltage. Since the standard write voltage is used when setting the predetermined threshold voltage, the final cumulative write voltage of the nonvolatile memory cell 1 is written with a predetermined voltage variation accuracy with respect to the threshold voltage. be able to. In addition, other nonvolatile memory cells 2,
Similarly, when writing to the memory cell 3, the first power supply voltage is supplied to the gate electrodes of the nonvolatile memory cells 2 and 3, and a write pulse may be applied in this state.

Next, the read operation of the nonvolatile memory cells 1, 2, 3 will be described. The second power supply voltage is supplied to the gate electrode of the nonvolatile memory cell (for example, 1) from which reading is performed. In this state, the sense amplifier 13 controls the supply of current to the bit line 4. When writing is performed at a predetermined threshold voltage, an inversion region is formed between the source and the drain due to the charge injected into the floating gate in the nonvolatile memory cell (for example, 1) that performs the reading. No current flows through the bit line 4. Conversely, when writing is not performed to the predetermined threshold voltage, no charge is injected into the floating gate in the nonvolatile memory cell (for example, 2) from which reading is performed, and the source and drain are not charged by the voltage of the gate electrode. An inversion region is formed between them, and a current flows through the bit line. The sense amplifier 13 outputs a detection voltage signal having a level corresponding to the current flowing through the bit line 4.

FIG. 2 is a write characteristic diagram showing the relationship between the cumulative number of write pulses and the read threshold voltage according to the first embodiment of the present invention. In the figure, the horizontal axis represents the cumulative number of write pulses, and the vertical axis represents the read threshold voltage. As can be seen from the figure, in the initial stage of writing, writing is performed at once with a high-voltage writing pulse, and in the latter stage of writing, writing is performed slowly with a low-voltage writing pulse. Writing is performed up to the voltage. In FIG. 3, A is a provisional threshold voltage set at a voltage level slightly lower than the predetermined threshold voltage, and the drain voltage control circuit 7 writes the cumulative write voltage up to the provisional threshold voltage, Is set so as to switch the voltage.

As described above, according to the first embodiment, the standard voltage generating circuit 5 for outputting the standard write voltage used for writing the threshold voltage to the nonvolatile memory cells 1, 2, 3; An initial voltage generating circuit 6 for outputting an initial write voltage higher than the standard write voltage, the standard write voltage and the initial write voltage being input, the initial write voltage being applied first, and then the standard write voltage being applied to the nonvolatile memory cell 1. , 2 and 3 are provided with a drain voltage control circuit 7 and a pulse input control transistor 9 for temporarily reducing the accumulated write voltage with a small number of write operations, and a voltage based on the standard write voltage. The threshold voltage can be written with variation accuracy. Therefore, it is possible to perform writing up to the threshold voltage with a smaller number of times of writing as compared with the case where writing up to the threshold voltage is performed only with the standard write voltage as in the related art. There is an effect that variation in threshold voltage can be suppressed as in the case where writing up to the voltage is performed. Further, in the first embodiment, the writing time can be shortened as compared with the conventional case, and accordingly, the standard writing voltage is set to a voltage lower than that of the conventional case. There is an effect that writing can be performed and voltage variation can be suppressed as compared with the related art.

Therefore, according to the first embodiment, the writing time can be suppressed while suppressing the variation in the threshold voltage. For example, in the case where a screening test is performed by baking for a volatile defect of the nonvolatile semiconductor memory device. In this case, writing can be performed in a short time while the voltage variation of the cumulative writing voltage of the nonvolatile memory cells 1, 2 and 3 is kept very small. The writing can be performed in a short time even if the screening test is performed by the above method, and the shipping test time is significantly reduced.

Embodiment 2 FIG. FIG. 3 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to Embodiment 2 of the present invention. In the figure, reference numeral 14 denotes a sense amplifier (switching signal generation circuit) that outputs a determination signal (switching signal) that changes according to the read values of the nonvolatile memory cells 1, 2, and 3, and reference numeral 15 denotes a standard write voltage and an initial write voltage. When this determination signal is input and the determination signal changes, the switch to be turned on is changed from the switch 15a to the switch 1
5b is a drain voltage control circuit that outputs a write voltage by switching to 5b, 16 is a threshold voltage generation circuit that outputs a threshold voltage, 1
7 is a provisional threshold voltage generation circuit that outputs a provisional threshold voltage,
Reference numeral 8 has two switches 18a and 18b to which a threshold voltage or a provisional threshold voltage is input. In an initial state at the time of writing, the switch 18b is turned on to control the gate electrodes of the nonvolatile memory cells 1, 2, and 3. A temporary threshold voltage is output to the non-volatile memory cells 1, 2, 3, and 3 in the later state of the write operation.
Is a verify voltage switching circuit that outputs a threshold voltage to the gate electrode (word line). The other configuration is the same as that of the first embodiment, and the same reference numerals are given and the description is omitted.

Next, the operation will be described. Each time the initial write pulse is input to a predetermined nonvolatile memory cell (for example, 1), the verify voltage switching circuit 18 outputs a provisional threshold voltage to the gate electrode of the nonvolatile memory cell (for example, 1), The sense amplifier 14 outputs a determination signal according to the read determination result of the accumulated write voltage based on the provisional threshold voltage. Then, while the writing by the initial write pulse and the determination operation are repeated, the charge injection amount of the floating gate increases and the cumulative write voltage exceeds the provisional threshold voltage. Therefore, the read determination of the cumulative write voltage based on the provisional threshold voltage is performed. The result changes, and the corresponding determination signal changes.

When the determination signal changes, the drain voltage control circuit 15 switches the switch to be turned on from the switch 15a to the switch 15b to output a low standard write voltage, and the verify voltage switching circuit 18 The voltage output to the (for example, 1) gate electrode is switched to the threshold voltage. Then, the writing with the standard write voltage and the judging operation are repeated, and when the read judgment result (judgment signal) of the accumulated write voltage based on the threshold voltage of the sense amplifier 14 changes again, the pulse output by the WREN signal ends. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, according to the second embodiment, the cumulative write voltage of the nonvolatile memory cells 1, 2, 3 is input, and the cumulative write voltage exceeds the provisional threshold voltage lower than the target threshold voltage. Then, a sense amplifier 14 for outputting a determination signal is provided, and the drain voltage control circuit 15 changes the write voltage supplied to the drain terminals of the nonvolatile memory cells 1, 2, 3 from the initial write voltage to the standard write voltage based on the determination signal. Since the switching is performed, there is an effect that the voltage of the write pulse can be surely reduced before the cumulative write voltage exceeds the threshold voltage. Therefore, the voltage of the write pulse can be reliably switched from the initial write voltage to the standard write voltage when the temporary threshold voltage is exceeded, regardless of the write characteristic variation of the nonvolatile semiconductor memory device. There is an effect that it is possible to prevent the accumulated write voltage from exceeding the threshold voltage erroneously while being set close to and maximizing the effect of reducing the number of times of writing while maximizing the effect of reducing the number of times of writing.

Embodiment 3 FIG. FIG. 4 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to Embodiment 3 of the present invention. In the figure, reference numerals 19, 20, and 21 denote initial write number counters (initial write monitoring circuits) for counting the number of times of initial write voltage applied to the nonvolatile memory cells 1, 2, and 3, respectively, and reference numeral 22 denotes a standard initial write voltage write. A reference counter (initial write monitoring circuit) 23 for storing the number of times is provided by these four counters 19 and 2.
The count values of 0, 21, and 22 are input, and the average value of the number of times of writing of the initial writing voltage is compared with the number of times of writing of the standard initial writing voltage. A comparator (initial write monitoring circuit) 24 that outputs a signal, and an extra high initial voltage generation circuit (initial voltage generation circuit) 24 that outputs an extra high initial write voltage having a voltage higher than the initial write voltage of the initial voltage generation circuit 6 ,
Reference numeral 25 denotes three switches 25a, 25b, and 2 to which a standard write voltage, an initial write voltage, and an extra-high initial write voltage are input.
5c, a drain voltage for turning on a switch corresponding to the initial write control signal to output an initial write voltage, and switching a switch to be turned on to a switch 25b to output a late write voltage when the determination signal changes. It is a control circuit. The other configuration is the same as that of the second embodiment, and the same reference numerals are given and the description is omitted.

Next, the operation will be described. When threshold writing to the nonvolatile semiconductor memory device is started, the drain voltage control circuit 25 generates an initial write voltage based on the initial write voltage, and the initial write voltage starts writing to the first nonvolatile memory cells 1, 2, and 3. Is done. Then, the initial write number counter (for example, 19) counts the number of times of writing the initial write pulse to the first nonvolatile memory cell (for example, 1) and stores the number. When the writing of the threshold voltage to the first nonvolatile memory cell (for example, 1) is completed, the drain voltage control circuit 25 again generates an initial write voltage based on the initial write voltage, and the second nonvolatile memory cell is generated by the initial write voltage. Writing of the volatile memory cell (for example, 2) is started. By repeating such an operation, a predetermined number of initial writings is sequentially stored in the plurality of initial writing number counters 19, 20, and 21.

All initial write counters 19 and 2
When the predetermined number of initial write times is stored in 0, 21, the comparator 23 sets all the initial write number counters 19, 20, 2.
The average value of the initial number of times of writing 1 is compared with the standard number of times of writing stored in the reference counter 22, and a different initial writing control signal is output in accordance with the magnitude relation.

The drain voltage control circuit 25 selects a voltage to be used as the initial write voltage from the standard write voltage, the initial write voltage, and the extra-high initial write voltage in accordance with the initial write control signal, and sets the selected voltage to the selected voltage. change. In the third embodiment, all the initial write counters 19,
The average value of the initial write times of 20, 21 is the reference counter 2
When the initial write control signal is input in a case where the initial write control signal is larger than the standard number of times of writing stored in 2 by a predetermined value or more,
The extra high initial write voltage is used as the initial write voltage, and the average value of the initial write times of all the initial write number counters 19, 20, and 21 is smaller than the standard write number stored in the reference counter 22 by a predetermined value or more. In this case, when the initial write control signal is input, the standard write voltage is used as the initial write voltage, and when the initial write control signal is input in other cases, the initial write voltage is used as the initial write voltage. Set. Other operations are the same as those in the second embodiment, and a description thereof will be omitted.

As described above, according to the third embodiment, the first few bits (3 in this embodiment) of the nonvolatile semiconductor memory device are written with the initial write voltage, and the initial write number counter 19, 20 and 21 count the number of times of writing, the comparator 23 outputs an initial write control signal corresponding to the count value, and the drain voltage control circuit 25 writes based on the initial write control signal the write used in the initial write. Change the voltage. Therefore,
Even if the characteristics of the nonvolatile semiconductor memory devices of the nonvolatile memory cells 1, 2, and 3 fluctuate, the initial write can be performed using the optimum write voltage.

Embodiment 4 FIG. FIG. 5 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to Embodiment 4 of the present invention. In the figure, reference numeral 26 denotes an initial write information memory cell for storing an initial write control signal. The other configuration is the same as that of the third embodiment, and the same reference numerals are given and the description is omitted.

Next, the operation will be described. The initial write information memory cell 26 stores an initial write control signal output from the comparator 23 in the first test of the nonvolatile semiconductor memory device. Then, in the second and subsequent tests, the drain voltage control circuit 25 calls the initial write control signal stored in the initial write information memory cell 26 at the start of writing, and sets the initial write voltage in accordance with the called initial write control signal. Is selected from the standard write voltage, the initial write voltage, and the extra high initial write voltage. Other operations are the same as those in the third embodiment, and a description thereof will be omitted.

As described above, according to the fourth embodiment, the initial write information memory cell 26 for storing the initial write control signal is provided, and the drain voltage control circuit 25 performs the initial write in the second and subsequent write tests. Since the write voltage to be used at the time of the initial write is selected based on the initial write control signal stored in the information memory cell 26, the initial write can be always performed using the optimum write voltage in the second and subsequent tests. effective.

Embodiment 5 FIG. 6 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to Embodiment 5 of the present invention. In the figure, 27 is a drain voltage control terminal connected to the base electrode of the write voltage input control transistor 10 and connected to a circuit external to the nonvolatile semiconductor memory device, and 28 is connected to the drain voltage control terminal 27 and An external pulse generator capable of generating a voltage. The other configuration is the same as that of the first embodiment, and the same reference numerals are given and the description is omitted.

Next, the operation will be described. At the time of writing, first, the external voltage generator 28 inputs an external initial write voltage having an initial write voltage to the drain voltage control terminal 27. As a result, the write voltage input control transistor 10 operates, charges are injected into the floating gate of a predetermined nonvolatile memory cell (for example, 1), and the read threshold voltage of this nonvolatile memory cell (for example, 1) increases. The external voltage generator 28 outputs the external initial write pulse having the standard write voltage after outputting the external initial write pulse based on the initial write voltage a predetermined number of times. Then, the writing with the external initial writing pulse of the standard writing voltage is repeated to set the cumulative writing voltage of the nonvolatile memory cell (for example, 1) to a predetermined threshold voltage. Since the standard write voltage is used when setting the predetermined threshold voltage, the final cumulative write voltage of the nonvolatile memory cell (for example, 1) is determined with a predetermined voltage variation accuracy with respect to the threshold voltage. Writing can be performed. Other operations are the same as those in the first embodiment, and a description thereof will be omitted.

According to the fifth embodiment, the nonvolatile memory cells 1, 2, 3 and the nonvolatile memory cells 1, 2, 2, 3
3 and a plurality of control transistors 9, 10, 11, and 12 connected between the drain terminal and the power supply voltage, and a gate of one of the plurality of control transistors (write voltage input control transistor 10). And a drain voltage control terminal 27 connected thereto, so that the voltage applied to the drain voltage control terminal 27 is reduced from the initial write voltage to the standard write voltage while the threshold voltage applied to the nonvolatile memory cells 1, 2, and 3 is reduced. Can be written. Therefore, for example, as the initial voltage, a write voltage higher than the standard write voltage is set to the drain voltage control terminal 27.
To increase the cumulative write voltage at a stretch with a small number of write times, and finally increase the cumulative write voltage little by little by applying a standard write voltage to the drain voltage control terminal 27. Writing up to the threshold voltage can be performed with a smaller number of times of writing as compared to the case where writing up to the threshold voltage is performed only with the writing voltage,
In addition, there is an effect that variation in threshold voltage can be suppressed as in the case where writing up to the threshold voltage is performed using only the standard write voltage as in the related art.

Therefore, according to the fifth embodiment, the writing time can be suppressed while suppressing the variation in the threshold voltage. For example, in the case where a screening test is performed by baking for a volatile defect of the nonvolatile semiconductor memory device. In this case, writing can be performed in a short time while the voltage variation of the cumulative writing voltage of the nonvolatile memory cells 1, 2 and 3 is kept very small. The writing can be performed in a short time even if the screening test is performed by the above method, and the shipping test time is significantly reduced.

[0038]

As described above, according to the present invention, the threshold voltage is written to the nonvolatile memory cell while temporarily lowering the write voltage applied to the drain terminal of the nonvolatile memory cell. As the initial voltage, a write voltage higher than the standard write voltage is used, and the cumulative write voltage can be increased at a stretch with a small number of write operations, and finally, the cumulative write voltage can be gradually increased with the standard write voltage. Therefore, it is possible to perform writing up to the threshold voltage with a smaller number of times of writing as compared with the case where writing up to the threshold voltage is performed only with the standard write voltage as in the conventional case, and furthermore, as in the conventional case, the threshold voltage is written only with the standard write voltage. Thus, there is an effect that variation in threshold voltage can be suppressed as in the case where writing is performed up to.

According to the present invention, a standard voltage generating circuit for outputting a standard write voltage used when writing a threshold voltage to a volatile memory cell, and an initial write voltage for outputting an initial write voltage higher than the standard write voltage Or, a plurality of initial voltage generating circuits, the standard write voltage and the one or more initial write voltages are input, and these write voltages are switched and supplied to the drain terminal of the nonvolatile memory cell, and the voltage of the drain terminal is changed. And a drain voltage control circuit for supplying the voltage so as to temporarily decrease the voltage, and use a higher write voltage than the standard write voltage as the initial voltage to increase the cumulative write voltage at once with a small number of write operations, and finally, Since the cumulative write voltage can be increased little by little with the standard write voltage, the threshold voltage can be increased only with the standard write voltage as in the past. Writing up to the threshold voltage can be performed with a smaller number of times of writing as compared to the case where writing is performed, and the variation in threshold voltage is the same as when writing up to the threshold voltage with only the standard writing voltage as in the conventional case. There is an effect that can be suppressed.

According to the present invention, there is provided a switching signal generating circuit for receiving a cumulative writing voltage of a nonvolatile memory cell, outputting a switching signal when the cumulative writing voltage exceeds a provisional threshold voltage lower than a target threshold voltage, Since the drain voltage control circuit switches the write voltage supplied to the drain terminal of the nonvolatile memory cell based on the switching signal, the write voltage can be surely reduced before the cumulative write voltage exceeds the target threshold voltage. effective.

According to the present invention, there is provided an initial write monitor circuit for counting the number of times of writing by the initial voltage generating circuit and outputting an initial write control signal corresponding to the count value. The write voltage used at the time of the above-mentioned initial write is changed on the basis of the above, so that even if the characteristics of the nonvolatile memory cells vary, there is an effect that the initial write can be performed using the optimum write voltage in accordance therewith. .

According to the present invention, the initial write information memory for storing the initial write control signal is provided, and the drain voltage control circuit is used at the time of the initial write based on the initial write control signal stored in the initial write information memory. Since the write voltage is selected, after the initial write control signal is once output from the initial write monitoring circuit, the initial write can be always performed using the optimum write voltage.

According to the present invention, the nonvolatile memory cell, one or more transistors connected between the drain terminal of the nonvolatile memory cell and the power supply voltage, and one of the one or more transistors Since the semiconductor device includes the drain voltage control terminal connected to the gates of the two transistors, the threshold voltage can be written to the nonvolatile memory cell while temporarily reducing the voltage applied to the drain voltage control terminal. Therefore, for example, a write voltage higher than the standard write voltage is applied to the drain voltage control terminal as the initial voltage, and the cumulative write voltage is increased at a stretch with a small number of write operations, and finally, the standard write voltage is applied to the drain voltage control terminal. To increase the cumulative write voltage little by little, the write up to the threshold voltage can be performed with a smaller number of write times compared to the case where the write up to the threshold voltage is performed using only the standard write voltage as in the conventional case. In addition, there is an effect that the variation of the threshold voltage can be suppressed as in the case where the writing up to the threshold voltage is performed only with the standard write voltage as in the related art.

Therefore, in the above invention, the writing time can be suppressed while suppressing the variation of the threshold voltage. For example, even when a screening test is performed by baking for a volatile defect of the nonvolatile semiconductor memory device, the nonvolatile memory can be used. Writing can be performed in a short time while the voltage variation of the cumulative writing voltage of the non-volatile memory cell is kept very small, and even if the screening test by the bake is performed at each manufacturing stage in a general nonvolatile semiconductor memory device, There is an effect that writing can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a write characteristic diagram showing a relationship between a cumulative number of write pulses and a read threshold voltage according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention;

FIG. 4 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to a third embodiment of the present invention;

FIG. 5 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing a partial configuration of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration of a part of a conventional nonvolatile semiconductor memory device.

FIG. 8 is a write characteristic diagram showing a relationship between the cumulative number of write pulses and a read threshold voltage in a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

1, 2, 3 nonvolatile memory cell, 5 standard voltage generator, 6 initial voltage generator, 7, 15, 25 drain voltage control circuit, 9 pulse input control transistor (transistor), 10 write voltage input control transistor (drain voltage Control circuit, transistor), 11, 12
Select control transistor (transistor), 14
Sense amplifier (switching signal generation circuit), 19, 20, 21
Initial write counter (initial write monitoring circuit), 2
2 Reference counter (initial writing monitoring circuit), 23 Comparator (initial writing monitoring circuit), 24 Extra high initial voltage generating circuit (initial voltage generating circuit), 26 Initial writing information memory cell, 27 Drain voltage control terminal.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Sayuri Nakahira 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term in Mitsubishi Electric Corporation (reference) 5B025 AA01 AC01 AD04 AE05

Claims (6)

[Claims] 1. A threshold voltage writing method for writing a threshold voltage in a nonvolatile memory cell of a nonvolatile semiconductor memory device, wherein the write voltage applied to a drain terminal of the nonvolatile memory cell is temporarily reduced while the nonvolatile memory cell is Writing a threshold voltage to a memory cell. 2. A nonvolatile memory cell, a standard voltage generating circuit for outputting a standard write voltage used for writing a threshold voltage to the nonvolatile memory cell, and an initial write voltage higher than the standard write voltage. One or a plurality of initial voltage generating circuits to be output, the standard write voltage and the one or a plurality of initial write voltages are input, and these write voltages are switched to be supplied to a drain terminal of the nonvolatile memory cell and to be supplied to the drain. A non-volatile semiconductor memory device comprising: a drain voltage control circuit for supplying a voltage of a terminal so as to temporarily decrease. 3. A switching signal generating circuit for receiving a cumulative writing voltage of a nonvolatile memory cell and outputting a switching signal when the cumulative writing voltage exceeds a provisional threshold voltage lower than a target threshold voltage, wherein a drain voltage control circuit is provided. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said switch switches a write voltage supplied to a drain terminal of said nonvolatile memory cell based on said switching signal. 4. An initial write monitoring circuit which counts the number of write operations by an initial voltage generation circuit and outputs an initial write control signal according to the count value, wherein the drain voltage control circuit performs the above-mentioned operation based on the initial write control signal 3. The nonvolatile semiconductor memory device according to claim 2, wherein a write voltage used at the time of initial write is changed. 5. An initial write information memory for storing an initial write control signal, and a drain voltage control circuit selects a write voltage to be used at the time of the initial write based on the initial write control signal stored in the initial write information memory. The nonvolatile semiconductor memory device according to claim 4, wherein: 6. A nonvolatile memory cell, one or more transistors connected between a drain terminal of the nonvolatile memory cell and a power supply voltage, and a gate of one of the one or more transistors And a drain voltage control terminal connected to the nonvolatile semiconductor memory device.