CN113409841B - Reference current generation circuit, reference current generation method, electronic equipment and test tool - Google Patents
Reference current generation circuit, reference current generation method, electronic equipment and test tool Download PDFInfo
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- CN113409841B CN113409841B CN202110736049.3A CN202110736049A CN113409841B CN 113409841 B CN113409841 B CN 113409841B CN 202110736049 A CN202110736049 A CN 202110736049A CN 113409841 B CN113409841 B CN 113409841B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a reference current generation circuit, a reference current generation method, electronic equipment and a test tool, wherein the circuit comprises: the precharge circuit with the change-over switch, the reference current generating circuit with a plurality of first storage units for adjusting output current, the comparison circuit with the change-over switch and the reference current reading circuit, wherein the precharge circuit can adjust the threshold voltage of the first storage units in the reference current generating circuit through the reference voltage signal so as to change an initial reference current signal and adjust a final reference current signal; the final reference current signal generated by the reference current generating circuit is generated based on the first memory cell, compared with the traditional reference current generated based on the reference voltage and the resistor, the reference current generated by the reference voltage and the resistor cannot be well and accurately matched with the current output by the target memory cell due to the floating influence of the process, the voltage and the temperature, and the problem of inaccurate reading operation precision is solved.
Description
Technical Field
The application relates to the technical field of chips, in particular to a reference current generating circuit, a reference current generating method, electronic equipment and a test tool.
Background
In general, when performing a read operation, the Nor Flash compares the bit line current Icell and Isen of a target memory cell to form a feedback voltage Vsen, and then amplifies and outputs the feedback voltage Vsen by a sense amplifier, and performs data reading and current regulation by using the feedback voltage Vsen, as shown in fig. 1.
As can be seen in connection with fig. 1, the reference current in such a reference current circuit can be calculated by the following conversion formula:
。
as can be seen from the conversion formula, the reference current generated by the circuit is directly related to the resistor RES and the reference voltage Vref, and Vref is generally a bandgap reference voltage, which does not substantially change with the process/voltage/temperature; however, during the read operation of Nor Flash, since the word line terminal RD_WL of the target memory cell is typically generated by a charge pump, the voltage level thereof will float within a certain range in different processes/voltages/temperatures, resulting in floating the bit line current Icell, and the feedback voltage Vsen will also affect the bit line current Icell because the memory cell is a real transistor.
The resistance value of the resistor RES can float within a certain range under the influence of the process, the voltage and the temperature, and the floating change condition is inconsistent with the corresponding floating change condition of the memory cell, so that a plurality of factors in the bit line current Icell and the reference current Isen can change along with the process, the voltage and the temperature, and the change amplitude and the change range can not be mutually offset.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
An objective of the embodiments of the present application is to provide a reference current generating circuit, a reference current generating method, an electronic device and a test tool, so that the generated reference current floating is consistent with the target memory cell bit line current floating, and the read operation accuracy is improved.
In a first aspect, an embodiment of the present application provides a reference current generating circuit for generating a reference current required for operating a memory cell for a Nor Flash, including:
a precharge circuit with a change-over switch for supplying a precharge signal and outputting a reference voltage signal generated based on the precharge signal;
a reference current generating circuit for regulating the output current by a plurality of first memory cells, electrically connected with the precharge circuit, for receiving the reference voltage signal and outputting an initial reference current signal;
a comparison circuit with a change-over switch, which is electrically connected with the reference current generation circuit and is used for receiving the initial reference current signal and outputting a final reference current signal acted on the target storage unit;
a reference current reading circuit electrically connected to the reference current generating circuit for receiving an initial reference current signal and outputting a final reference current signal;
the precharge circuit may adjust the final reference current signal by adjusting a threshold voltage of a first memory cell in the reference current generation circuit by the reference voltage signal to change the initial reference current signal.
The reference current generating circuit, wherein the precharge circuit includes:
the precharge power supply with a change-over switch is used for sending out precharge signals;
the second storage units are electrically connected with the precharge power supply through bit lines and are used for receiving precharge signals and outputting reference voltage signals;
the number of the second memory cells is consistent with that of the first memory cells, and the second memory cells are connected with the first memory cells through word lines, and can be matched with a precharge signal sent by a precharge power supply to generate a reference voltage signal so as to adjust the threshold voltage of the first memory cells to change the magnitude of the reference current signal generated after the second memory cells receive the reference voltage signal.
The reference current generating circuit further comprises a bit line current reading circuit electrically connected with the pre-charging circuit and the reference current generating circuit, and the sum of the bit line current of the first memory cell, the bit line current of the second memory cell and the bit line current of the first memory cell and the second memory cell can be read and output.
The reference voltage signal is the drain voltage of the second memory cell.
The reference current generating circuit includes:
a plurality of first memory cells electrically connected to the precharge circuit through word line ends;
the operational amplifier is electrically connected with the precharge circuit and the first storage unit and is used for clamping and adjusting the threshold voltage of the first storage unit so that the first storage unit outputs an initial current signal;
and the plurality of first PMOS tubes are electrically connected with the operational amplifier and the first storage unit and are used for receiving the initial current signal and outputting an initial reference current signal.
The reference current generating circuit, wherein the comparing circuit includes:
the change-over switch is electrically connected with the reference current generation circuit and is used for controlling whether the initial reference current signal is conducted or not;
and the second PMOS tubes are electrically connected with the change-over switch and the bit line of the target storage unit and are used for receiving the initial reference current signal and outputting a final reference current signal, and comparing the final reference current signal with the bit line current signal of the target storage unit to generate a reference voltage signal.
The reference current generating circuit comprises a plurality of third PMOS tubes electrically connected with the reference current generating circuit.
In a second aspect, an embodiment of the present application further provides a reference current generating method based on the reference current generating circuit, for generating a reference current required by an operation of a memory cell for a Nor Flash, including the following steps:
s1, opening a precharge circuit according to an operation instruction to output a precharge signal and a reference voltage signal generated based on the precharge signal;
s2, adjusting the threshold voltage of the first storage unit by using the reference voltage signal so that the reference current generating circuit outputs an initial reference current signal;
s3, reading and calculating whether the initial reference current signal can generate an expected final reference current signal through a reference current reading circuit;
and S4, if yes, a change-over switch of the comparison circuit is turned on to generate and output a final reference current signal, and if not, a precharge signal is regulated, and the steps S2-S4 are executed again.
In a third aspect, embodiments of the present application also provide an electronic device comprising a processor and a memory storing computer readable instructions which, when executed by the processor, perform the steps of the method as provided in the first aspect above.
In a fourth aspect, an embodiment of the present application further provides a test tool, including the above reference current generating circuit.
It can be seen from the foregoing that, according to the reference current generating circuit, the reference current generating method, the electronic device and the test tool provided by the embodiment of the application, the final reference current signal generated by the circuit is generated based on the adjustment of the first storage unit, the first storage unit and the target storage unit are the same storage unit, and the first storage unit and the target storage unit have the same electrical performance, so that the reference current generated by the embodiment of the application is more accurate, and represents the current value which the target storage unit should output under the same operation parameter.
Drawings
Fig. 1 is a schematic diagram of a conventional reference current generating circuit.
Fig. 2 is a schematic structural diagram of a reference current generating circuit according to an embodiment of the present application.
Fig. 3 is a flowchart of a reference current generating method according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 1. a precharge circuit; 2. a reference current generation circuit; 3. a comparison circuit; 4. a reference current reading circuit; 5. a bit line current reading circuit.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 2, fig. 2 is a reference current generating circuit according to some embodiments of the present application, for generating a reference current required for a memory cell operation for a Nor Flash, and includes:
a precharge circuit 1 with a change-over switch for supplying a precharge signal and outputting a reference voltage signal generated based on the precharge signal;
a reference current generating circuit 2 for regulating the output current by a plurality of first memory cells, electrically connected to the precharge circuit 1, for receiving a reference voltage signal and outputting an initial reference current signal;
a comparison circuit 3 with a change-over switch, electrically connected to the reference current generation circuit 2, for receiving the initial reference current signal and outputting a final reference current signal acting on the target memory cell;
a reference current reading circuit 4 electrically connected to the reference current generating circuit 2 for receiving the initial reference current signal and outputting a final reference current signal;
the precharge circuit 1 may adjust the final reference current signal by adjusting the threshold voltage of the first memory cell in the reference current generation circuit 2 by the reference voltage signal to change the initial reference current signal.
Specifically, the final reference current signal is conducted with the bit line voltage of the target memory cell to generate feedback voltage information.
In the reference current generating circuit of the embodiment of the application, the precharge circuit 1 is matched with the reference current generating circuit 2 with a first memory cell to generate an initial reference current signal, and the comparison circuit 3 is used for generating a final reference current signal to be compared with the bit line current of a target memory cell to generate a feedback voltage signal; the final reference current signal generated by the circuit is generated based on the adjustment of the first storage unit, the first storage unit and the target storage unit are the same storage unit (memory cell), the first storage unit and the target storage unit have the same electrical property, the reference current generated by the embodiment of the application is more accurate, the current value which is required to be output by the target storage unit under the same operation parameter is represented, compared with the traditional reference current generated based on the reference voltage and the resistor, the reference current generated by the reference voltage and the resistor cannot be well and accurately matched with the current output by the target storage unit due to the floating influence of the process, the voltage and the temperature, and the problem of inaccurate reading operation precision is caused.
More specifically, the embodiment of the application matches the final reference current signal generated by the first memory cell with the target current when the target cell is subjected to corresponding operation due to the floating influence of the same process/voltage/temperature, and is particularly suitable for the read operation, so that the target memory cell can be adjusted based on the reference current containing the relevant floating influence, thereby accurately achieving the current required by the read operation and accurately completing the read operation.
More specifically, in the embodiment of the present application, the precharge circuit 1 performs the write operation on the first memory cell of the reference current generation circuit 2 to change the threshold voltage of the first memory cell, and then the reference current generation circuit 2 can accurately output the initial reference current signal based on the first memory cell after the threshold voltage is adjusted by the write operation.
Specifically, in the embodiment of the present application, a reference current generating circuit is connected to a master controller, and a comparing circuit 3 is connected to a target memory cell; the change-over switch of the precharge circuit 1 can be opened according to the instruction issued by the main controller so as to start the generation of an initial reference current signal; secondly, the master controller can calculate and acquire final reference current information in real time through the reference current reading circuit 4, and based on the final reference current information reaching preset reference current information, a change-over switch in the comparison circuit 3 is opened to control the final reference current signal and the bit line current conduction of the target memory cell, so as to acquire feedback voltage signals generated by the conduction of the two circuits.
Specifically, to clearly show the layout structure of the components of the reference current generating circuit according to the embodiments of the present application, the components in fig. 1 are simplified to be expressed, that is, a plurality of components that are repeatedly and serially connected are combined into one component to be expressed, for example, N first memory cells Fcell1 are only drawn in the figure to be expressed, and are labeled Fecll1×n, where N is the number corresponding to the first memory cells Fcell 1.
In some preferred embodiments, the precharge circuit 1 comprises:
the precharge power supply with a change-over switch is used for sending out precharge signals;
the second storage units are electrically connected with the precharge power supply through bit lines and are used for receiving precharge signals and outputting reference voltage signals;
the number of the second memory cells is consistent with that of the first memory cells, and the second memory cells are connected with the first memory cells through word lines, and can be matched with a precharge signal sent by a precharge power supply to generate a reference voltage signal so as to adjust the threshold voltage of the first memory cells to change the magnitude of the reference current signal generated after the second memory cells receive the reference voltage signal.
Specifically, the second memory cell is charged after the transfer switch of the power supply is precharged, and the bit line end of the charged second memory cell can apply a corresponding reference voltage signal to the reference current generating circuit 2 according to the charged amount.
More specifically, the number of the second memory cells is set to be identical to the number of the first memory cells, so that the two memory cells can be in one-to-one correspondence and connected through word lines, and the reference voltage signal can be copied to the drain of the first memory cell by using the structure of the reference current generating circuit 2 to generate corresponding current information.
According to the embodiment of the application, the precharge power supply is matched with the combined circuit structure of the second storage unit to realize the supply of the reference voltage information, so that the reference voltage information required by the first storage unit can be accurately applied, and the precharge power supply has the characteristics of high regulation precision and convenience in regulation.
More specifically, the precharge power supply performs a write operation on the second memory cell using the precharge signal so that the second memory cell outputs the reference voltage information, and the reference current generation circuit 2 acquires the reference voltage information and duplicates the application to the first memory cell therein to perform a write operation on the first memory cell to change the threshold voltage of the first memory cell, thereby allowing the reference current generation circuit 2 to accurately output the required initial reference current signal based on the first memory cell.
In some preferred embodiments, the memory device further comprises a bit line current reading circuit 5 electrically connected to the precharge circuit 1 and the reference current generating circuit 2, and capable of reading and outputting the sum of the bit line current of the first memory cell, the bit line current of the second memory cell, and the bit line currents of the first memory cell and the second memory cell.
Specifically, the embodiment of the application may output the bit line current of the first memory cell or the bit line current of the second memory cell or the sum of the bit line currents of the first memory cell and the second memory cell through the bit line current reading circuit 5, the output current value is generally received by the main controller, and the main controller may control the adjustment of the precharge signal according to the current values, that is, obtain the bit line current on the corresponding bit line in the writing operation stage of the first memory cell or the second memory cell, so as to change the precharge signal output by the precharge power supply, change the programming data of the first memory cell and/or the second memory cell, and further realize the accurate adjustment of the threshold voltage of the second memory cell in the writing operation stage.
More specifically, the bit line current reading circuit 5 includes two parallel reading switches, and is electrically connected to the bit line of the first memory cell and the bit line of the second memory cell, respectively.
In some preferred embodiments, the reference voltage signal is a drain voltage of the second memory cell.
In some preferred embodiments, the reference voltage generation circuit includes:
a plurality of first memory cells electrically connected with the precharge circuit 1 through word line ends;
the operational amplifier is electrically connected with the precharge circuit 1 and the first memory cell and is used for clamping and adjusting the threshold voltage of the first memory cell so that the first memory cell outputs an initial current signal;
and the plurality of first PMOS tubes are electrically connected with the operational amplifier and the first storage unit and are used for receiving the initial current signal and outputting an initial reference current signal.
Specifically, the operational amplifier is electrically connected to the drain of the second memory cell, so that the reference voltage signal output by the second memory cell, i.e., the leakage voltage, can be copied to the drain of the first memory cell, and thus the threshold voltage of the first memory cell, i.e., the read voltage, can be indirectly adjusted according to the precharge signal.
More specifically, the gate, drain and source of the adjusted first memory cell are completely consistent with the bias condition of the target memory cell, and the floating effect of the process/voltage/temperature of the first memory cell and the target memory cell is the same, so that the adjusted first memory cell can be used as a technical guarantee for generating accurate read current, namely accurate final reference current signal.
More specifically, the initial current signal output by the first storage unit is controlled by the gate-source voltage through a plurality of first PMOS transistors to control the drain-source current, so that the initial current signal is noise-reduced and stably output as an initial reference current signal.
More specifically, the second memory cell can be replaced by any current source mode with little floating, because the difference of the bit line current caused by the floating voltage of the drain terminal of the target memory cell of the NOR flash is not obvious when the target memory cell performs the read operation in the saturation region.
In some preferred embodiments, the comparison circuit 3 comprises:
the change-over switch is electrically connected with the reference current generation circuit 2 and is used for controlling whether the initial reference current signal is conducted or not;
and the second PMOS tubes are electrically connected with the change-over switch and the bit line of the target storage unit and are used for receiving the initial reference current signal and outputting a final reference current signal, and comparing the final reference current signal with the bit line current signal of the target storage unit to generate a reference voltage signal.
More specifically, since the target memory cells are generally memory arrays, the number of which is different from that of the second memory cells, and the initial reference current signal output after passing through the first PMOS is smaller than the initial current signal, the second PMOS is required to amplify the initial reference current signal to make the initial reference current signal amplified to the final reference current signal, so as to be used for generating the feedback voltage signal.
Specifically, the change-over switch may be switched based on the information read by the reference current reading circuit 4 based on the master to control whether the final reference current signal is turned on or not.
In some preferred embodiments, the reference current reading circuit 4 includes a number of third PMOS transistors electrically connected to the reference current generating circuit 2.
Specifically, the third PMOS transistor is utilized to transform and output the initial reference current signal, so that the master controller can directly or indirectly obtain the final reference current signal, when the number of the third PMOS transistor is consistent with that of the second PMOS transistor, the signal output by the reference current reading circuit 4 can be directly regarded as the final reference current signal, and when the number of the third PMOS transistor is inconsistent with that of the second PMOS transistor, the final reference current signal can be output according to the indirect settlement of the ratio of the number of the third PMOS transistor and the second PMOS transistor.
Example 1
As shown in fig. 2, the pre-charge power supply SA pre-charge is electrically connected to N second memory cells Fcell2, the N second memory cells Fcell2 are electrically connected to N first memory cells Fcell1 through word lines rd_wl, the operational amplifier OP and the positive and negative electrodes are respectively connected to the second memory cells Fcell2 and the drain electrode of the first memory cells Fcell1, the first memory cells Fcell1 are connected to M first PMOS tubes P1, the gate electrode of the first PMOS tube P1 is connected to the output terminal of the operational amplifier OP and to the gate electrode of the Q second PMOS tubes P2, the second PMOS tube P2 is connected to the bit line of the target memory cell, the gate electrode of the third PMOS tube P3 is connected to the gate electrode of the first PMOS tube P1, the switch S1 and the switch S2 are respectively connected to the first memory cells Fcell1 and the second memory cells Fcell2, and the switch SA is hidden in the figure.
After the precharge power supply SA pre-charge sends out a precharge signal, writing operation is performed on the second memory cell Fcell2, so that the drain electrode of the second memory cell outputs reference voltage information Vbl1, the operational amplifier OP obtains the reference voltage information Vbl1 and copies the reference voltage information Vbl1 and applies the reference voltage information to the first memory cell Fcell1, and the switches S1 and S2 are respectively closed to respectively read the bit line currents of bit lines of the first memory cell Fcell1 and the second memory cell Fcell2, so that the threshold voltage Vt of the first memory cell Fcell1 can be changed through writing operation; after the threshold voltages of the first memory cells are regulated, stable power supply is performed through the pre-charge of the pre-charge power supply SA, each first memory cell Fcell1 outputs a reading current Ifcell, N output reading currents Ifcell are superposed to generate an initial current signal, an initial reference current signal is generated after passing through M first PMOS tubes PI, and a final reference current signal Isen is generated after passing through Q second MOS tubes, so that the calculation formula of the final reference current signal Isen is as follows:
。
it can be seen that the final reference current signal Isen is associated with the output read current Ifcell of the first memory cell Fcell1, such that the reference current generated in the embodiments of the present application is affected by the same process/voltage/temperature fluctuations as the target memory cell.
In a second aspect, referring to fig. 3, fig. 3 is a reference current generating method based on the reference current generating circuit according to some embodiments of the present application, for generating a reference current required for the operation of a memory cell for a Nor Flash, including the following steps:
s1, opening a precharge circuit 1 according to an operation instruction to output a precharge signal and a reference voltage signal generated based on the precharge signal;
specifically, according to the operation instruction, a change-over switch of the precharge power supply is turned on, so that the precharge power supply generates a precharge signal, and the second storage unit receives the precharge signal to generate a reference voltage signal.
S2, adjusting the threshold voltage of the first memory cell by using the reference voltage signal to enable the reference current generating circuit 2 to output an initial reference current signal,
specifically, the reference voltage signal is copied to the drain electrode of the first memory cell by matching the reference voltage signal with the bit line current reading circuit 5 and the operational amplifier to adjust the threshold voltage of the first memory cell, then the second memory cell outputs a stable initial current signal by stabilizing power supply, and the first PMOS transistor is used for controlling the initial current signal to output a stable initial reference current signal.
S3, reading and calculating whether the initial reference current signal can generate an expected final reference current signal through the reference current reading circuit 4;
and S4, if yes, a change-over switch of the comparison circuit 3 is turned on to generate and output a final reference current signal, and if not, a precharge signal is adjusted, and the steps S2-S4 are executed again.
In the reference current generation method of the embodiment of the application, the precharge circuit 1 is matched with the reference current generation circuit 2 with the first memory cell to generate an initial reference current signal, and the comparison circuit 3 is used for generating a final reference current signal to be compared with the bit line current of the target memory cell to generate a feedback voltage signal; the final reference current signal generated by the circuit is generated based on the first memory cell, compared with the reference current generated by a traditional method based on the reference voltage and the resistor, the reference current generated by the reference voltage and the resistor cannot be well and accurately matched with the current output by the target memory cell due to the floating influence of the process, the voltage and the temperature, and the problem of inaccurate reading operation precision is solved.
In a third aspect, referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and the present application provides an electronic device 300, including: processor 301 and memory 302, the processor 301 and memory 302 being interconnected and in communication with each other by a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, which when run by a computing device, the processor 301 executes to perform the method in any of the alternative implementations of the embodiments described above.
In a fourth aspect, an embodiment of the present application further provides a test tool, including the above reference current generating circuit; the test fixture comprises the reference current generating circuit, and the reference current generating circuit structure of the test fixture can refer to the embodiment and is not repeated; it can be appreciated that, because the test fixture of the embodiment of the application adopts the technical scheme of the reference current generating circuit, the test fixture has all the beneficial effects.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (9)
1. A reference current generating circuit for generating a reference current for a memory cell operation requirement for a Nor Flash, comprising:
a precharge circuit (1) with a changeover switch for supplying a precharge signal and outputting a reference voltage signal generated based on the precharge signal;
a reference current generating circuit (2) for regulating the output current by a plurality of first memory cells, electrically connected with the precharge circuit (1), and used for receiving a reference voltage signal and outputting an initial reference current signal;
a comparison circuit (3) with a change-over switch, which is electrically connected with the reference current generation circuit (2) and is used for receiving an initial reference current signal and outputting a final reference current signal acted on a target storage unit;
a reference current reading circuit (4) electrically connected to the reference current generating circuit (2) for receiving an initial reference current signal and outputting a final reference current signal;
the precharge circuit (1) may adjust a final reference current signal by adjusting a threshold voltage of a first memory cell in the reference current generation circuit (2) by a reference voltage signal to change an initial reference current signal;
the precharge circuit (1) includes:
the precharge power supply with a change-over switch is used for sending out precharge signals;
the second storage units are electrically connected with the precharge power supply through bit lines and are used for receiving precharge signals and outputting reference voltage signals;
the number of the second memory cells is consistent with that of the first memory cells, and the second memory cells are connected with the first memory cells through word lines, and can be matched with a precharge signal sent by a precharge power supply to generate a reference voltage signal so as to adjust the threshold voltage of the first memory cells to change the magnitude of the reference current signal generated after the second memory cells receive the reference voltage signal.
2. A reference current generating circuit according to claim 1, further comprising a bit line current reading circuit (5) electrically connected to the precharge circuit (1) and the reference current generating circuit (2) for reading and outputting a sum of a bit line current of the first memory cell, a bit line current of the second memory cell, and bit line currents of the first memory cell and the second memory cell.
3. The reference current generating circuit of claim 1, wherein the reference voltage signal is a drain voltage of the second memory cell.
4. The reference current generating circuit according to claim 1, wherein the reference voltage generating circuit comprises:
a plurality of first memory cells electrically connected with the precharge circuit (1) through word line ends;
the operational amplifier is electrically connected with the precharge circuit (1) and the first storage unit and is used for clamping and adjusting the threshold voltage of the first storage unit so that the first storage unit outputs an initial current signal;
and the plurality of first PMOS tubes are electrically connected with the operational amplifier and the first storage unit and are used for receiving the initial current signal and outputting an initial reference current signal.
5. A reference current generating circuit according to claim 1, wherein the comparing circuit (3) comprises:
the change-over switch is electrically connected with the reference current generation circuit (2) and is used for controlling whether an initial reference current signal is conducted or not;
and the second PMOS tubes are electrically connected with the change-over switch and the bit line of the target storage unit and are used for receiving the initial reference current signal and outputting a final reference current signal, and comparing the final reference current signal with the bit line current signal of the target storage unit to generate a reference voltage signal.
6. The reference current generating circuit according to claim 5, wherein the reference current reading circuit (4) comprises a plurality of third PMOS transistors electrically connected to the reference current generating circuit (2).
7. A reference current generating method based on the reference current generating circuit of any one of claims 1 to 6 for generating a reference current for the operation requirement of a memory cell for a Nor Flash, comprising the steps of:
s1, opening a precharge circuit (1) according to an operation instruction to output a precharge signal and a reference voltage signal generated based on the precharge signal;
s2, adjusting the threshold voltage of the first storage unit by using the reference voltage signal so that the reference current generation circuit (2) outputs an initial reference current signal;
s3, reading and calculating whether the initial reference current signal can generate an expected final reference current signal or not through a reference current reading circuit (4);
s4, if yes, a change-over switch of the comparison circuit (3) is turned on to generate and output a final reference current signal, and if not, a precharge signal is adjusted, and the steps S2-S4 are executed again.
8. An electronic device comprising a processor and a memory storing computer readable instructions that, when executed by the processor, perform the steps in the method of claim 7.
9. A test fixture comprising a reference current generating circuit as claimed in any one of claims 1 to 6.
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