JPH10228786A - Non-volatile semiconductor memory and its threshold value control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of over program bit at the time of writing and erasing operation in a non-volatile semiconductor memory and its threshold value control method. SOLUTION: When data is written in a memory cell transistor, initial setting of applied pulse voltage, a pulse duration, and a verifying voltage level is performed (step S1), and a memory cell transistor of one bit performing write-in is selected (step S2), and pulse voltage is applied (step S3). At the time, it is judged whether the set verifying voltage level is satisfied or not (step S4), when it is not satisfied, a pulse is applied again (step S3). When it is satisfied, it is judged whether the level is the last verifying voltage level or not (step S5), when it is not satisfied, applied pulse voltage, pulse duration are decreased (step S6), and a verifying voltage level is updated (step S7). If it is satisfied, writing is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of writing and erasing electrical information.

[0002]

2. Description of the Related Art FIG. 1 is a sectional view for explaining a write operation of a DINOR (AND), NOR and NAND type flash memory in a conventional nonvolatile semiconductor memory device.
This is shown in FIGS. 41, 44 and 45. Further, when a write voltage is applied to a DINOR type (AND type) flash memory, the write time for each verify is fixed (4
FIG. 42 shows a change in the threshold value of the memory cell transistor in the case of (00 μSEC), and FIG. 43 shows a change in the threshold value of the memory cell transistor in the case where the write time for each verification is gradually increased.

In FIG. 41 to FIG. 45, reference numerals indicate the following. 100 is a gate terminal, 101 is a drain terminal, 102 is a floating source terminal, 103
Is a control gate, 104 is a floating gate, 105 is an n ⁺ diffusion layer drain, 106 is an n ⁺ diffusion layer source, 107 is a grounded p-type semiconductor substrate, and 108 and 110 are memory cell transistor write speeds. Is a slow graph, 109 and 111 are graphs when the writing speed of the memory cell transistor is fast, 11
2 is a grounded source terminal, and 113 is a grounded drain terminal.

As shown in FIG. 41, a DINOR type (AN
In a D-type flash memory, the control gate terminal 100, the drain terminal 101, and the source terminal 102 are connected to a negative or zero potential (V
g ≦ 0 V), a positive potential (Vd> 0 V), a floating state, and by utilizing the FN tunnel phenomenon, electrons are extracted from the floating gate 104 and the drain 1
05 (IEICE TRANS.ELEC
TRON, VOL.E77-C, NO.8, AUGUST 1994, pages 1279-1285 and IE
DM 1992, pp. 991-993). On the other hand, in the case of a NOR type flash memory, as shown in FIG. 44, the control gate terminal 100, the drain terminal 101, and the source terminal 11
2 are connected to a positive potential (Vg> 0 V) and a positive potential (V
d> 0 V), the potential was set to the GND potential, and writing was performed by injecting electrons from GND to the floating gate 104 through the source 106 and the p-type semiconductor substrate 107 (IEDM 1990, pp. 115-118). As shown in FIG. 45, in the NAND flash memory, the control gate terminal 100, the source terminal 112, and the drain terminal 113 are connected to a positive potential (Vg> 0 V), GND, respectively.
In this case, electrons are extracted from the p-type semiconductor substrate 107 grounded to GND and injected into the floating gate 104 by using the FN tunnel phenomenon, and writing is performed (552 in IEDM 1987).
-555 page).

[0005] In writing in such a nonvolatile semiconductor memory device, the voltage applied to each terminal (drain terminal, control gate terminal, source terminal) is set to a constant value, or the voltage is applied to the nonvolatile semiconductor memory device for each verification. Until the applied voltage reaches the maximum value, the difference between the applied voltages of the terminals was gradually increased.

As shown in FIG. 42, the threshold value (109a) of the memory cell transistor (109), which is liable to be written in the memory cell transistor and becomes extremely close to the verify threshold voltage (Vv) in the first write, is verified after the verify operation. In the second writing to the memory cell transistor, the threshold value (109b) becomes 0 V (over-program level Vo) or less. On the other hand, in the first writing, the writing is slow, and the memory cell transistor (108) having a threshold (108a) somewhat higher than the verify threshold voltage has the verify threshold voltage (V
The threshold (108b) is set between v) and 0V (Vo) and does not become lower than Vo, so that no over-program failure occurs.

It goes without saying that this phenomenon becomes more severe as the voltage of the flash memory decreases and the verify threshold voltage decreases (closes to 0 V).

Further, as shown in FIG. 43, there is also a method in which the write voltage application time is gradually increased every certain number of times of verification. In the case of this method, if a longer write voltage is applied to the memory cell transistor whose threshold voltage is as close as possible to the verify threshold voltage in the next write, the write time is further constant than in the above-described case where the write time is constant. Easy to over program.

[0009]

Since the conventional nonvolatile semiconductor memory device is configured as described above, it has the following problems. That is, in the prior art shown in FIG. 42, the voltage and time applied to the memory cell transistor are independent of whether the threshold voltage of the memory cell transistor is extremely close to the verify threshold voltage Vv (109a) or whether the threshold voltage is far away (108a). It is constant. Therefore,
In the case of the memory cell transistor whose writing speed is fast and the threshold value is as close as possible to the verify threshold voltage Vv (1
09a) indicates that the threshold value is 0 V in the next write after verification.
(109b), and there is a problem that over-programming may occur.

[0010] This phenomenon is more likely to occur when the applied voltage is high and the amount of one write is large (the write speed is high). On the other hand, if the applied voltage is reduced to reduce the writing speed in order to increase the controllability of the writing threshold,
There has been a problem that the total writing time is significantly increased.

Further, as shown in FIG. 43, in the case of a system in which the write voltage application time is gradually increased every certain number of times of verification, the over-programming time is further increased as compared with the case where the write time in FIG. There was a problem that it easily became defective.

The above description is based on the DINOR type and the AN in which writing corresponds to extraction of electrons from the floating gate.
Although the D-type flash memory has been described, the writing corresponds to the injection of electrons into the floating gate.
The same problems as described above also occur in flash memories of the NAND type and NAND type. That is, when a multi-level flash memory is configured by NOR or NAND flash memories, it is necessary to set a plurality of write levels. In writing information, it is necessary to accurately set the threshold value of the memory cell transistor between specific levels among a plurality of write levels. In this case, a problem similar to that of the above-described overprogram (when the write threshold value deviates from between the specific levels) occurs, so that the controllability of the write threshold value must be improved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a nonvolatile semiconductor memory device which suppresses the occurrence of over-program bits by improving controllability of a threshold change, and a threshold voltage of the nonvolatile semiconductor memory device It is intended to provide a control method.

[0014]

A nonvolatile semiconductor memory device according to a first aspect of the present invention has a memory cell array and stores information by changing a threshold value of a memory transistor in the memory cell array. And a pulse generator for generating a pulse for changing a threshold of the memory cell transistor, wherein the pulse has at least one of a pulse voltage and a pulse time variable, and the threshold of the memory cell transistor by the pulse is provided. Further comprising a verify voltage generator for generating a verify voltage for verifying a change in the memory cell transistor, wherein the verify voltage includes at least a first and a second verify voltage, and when the threshold of the memory cell transistor changes, the threshold is changed to the second voltage. 1. In response to entering between the second verify voltage , The absolute value of the pulse voltage in the pulse generator further comprises a control means for reducing at least one of the pulse time.

A nonvolatile semiconductor memory device according to a second invention is the nonvolatile semiconductor memory device according to the first invention, wherein the verify voltage includes first to n-th (n ≧ 3) verify voltages, When the threshold value of the memory cell transistor changes, the control means sets the threshold value between the first and second verify voltages, between the second and third verify voltages,...
In response to each time between the (n-1) th and the nth verify voltage, at least one of the absolute value of the pulse voltage and the pulse time in the pulse generator is sequentially reduced.

A nonvolatile semiconductor memory device according to a third invention is the nonvolatile semiconductor memory device according to the first or second invention, wherein at least one of an absolute value of the pulse voltage and a pulse time by the control means is provided. The reduction is performed on the pulse applied to the drain of the memory cell transistor.

A nonvolatile semiconductor memory device according to a fourth invention is the nonvolatile semiconductor memory device according to the first or second invention, wherein at least one of an absolute value of the pulse voltage and a pulse time by the control means is provided. The reduction is performed for the pulse applied to the control gate of the memory cell transistor.

A nonvolatile semiconductor memory device according to a fifth aspect of the present invention is the nonvolatile semiconductor memory device according to the first or second aspect, wherein at least one of an absolute value of the pulse voltage and a pulse time by the control means is provided. The reduction is performed on the pulse applied to the drain and control gate of the memory cell transistor.

According to a sixth aspect of the present invention, there is provided a method of controlling a threshold value of a nonvolatile semiconductor memory device, comprising a memory cell array, wherein information is stored by changing a threshold value of a memory cell transistor in the memory cell array. A threshold control method, wherein a first step of changing the threshold at a first change rate while verifying a change in a threshold of the memory cell transistor; and wherein the threshold is a first verify voltage in the first step. And the second
A second step of changing the threshold value at a second change rate that is slower than the first change rate while verifying the change in the threshold value in response to the change in the threshold voltage. ing.

According to a seventh aspect of the present invention, there is provided a method of controlling a threshold value of a nonvolatile semiconductor memory device according to the sixth aspect of the present invention, wherein the threshold value is different from the first and second verify voltages. Between the second and third verify voltages,
... between the (n-1) th and n-th verify voltages (n ≧
Each time 3), the threshold value is changed while sequentially changing the threshold change rate to a gradual change rate in response to the change.

According to an eighth aspect of the present invention, there is provided a method of controlling a threshold value of a nonvolatile semiconductor memory device according to the sixth or seventh aspect, wherein the change of the threshold value of the memory cell transistor is changed. The change of the ratio is performed by reducing at least one of an absolute value of a pulse voltage and a pulse time in a pulse applied to the memory cell transistor to change the threshold.

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a nonvolatile semiconductor memory device and a threshold control method according to the present invention.

FIG. 1 shows a first embodiment of the present invention to be described later.
FIG. 4 is a block diagram illustrating a circuit configuration of a nonvolatile semiconductor memory device of FIGS. FIG. 2 is a flowchart showing a processing procedure of the sequence controller of the nonvolatile semiconductor memory device shown in FIG.

As shown in FIG. 1, a sequence controller 2 is connected to the mode control circuit 1. The sequence controller 2 is connected so as to be able to control the variable write / erase verify voltage generator 3, the variable write / erase pulse generator 4, and the column decoder 5.
The variable write / erase verify voltage generator 3 generates a voltage for verifying writing or erasing of a memory cell of the memory cell array 6 and supplies this voltage to a memory cell of a selected word line via a row decoder 7. The variable write / erase pulse generator 4 generates a pulse for writing or erasing a memory cell, and outputs this pulse via a column decoder 5 to a memory cell of a selected bit line or a selected word via a row decoder 7. Give to line memory cells. Here, when the verify voltage is applied, the current of the selected cell is read, and the column decoder 5 is used to determine whether the verify value is satisfied.
The inside sense amplifier is connected to the sequence controller 2.

The mode control circuit 1 controls a write mode, an erase mode, and a read mode
To instruct. In the following, the procedure for writing or erasing one bit of the sequence controller 2 in the writing or erasing mode will be described with reference to FIG.

First, an instruction is given to the variable write / erase verify voltage generator 3 and the variable write / erase pulse generator 4 by the sequence controller 2 to verify the verify voltage level, the absolute value of the write or erase pulse voltage / initial of the pulse time. The setting is performed (step S1).

Next, the column decoder 5 and the row decoder 7
To select a memory cell to be written or erased in the memory cell array 6 (step S2).

Next, the variable write / erase pulse generator 4
Applies a write or erase pulse voltage to the cell selected in step S2 via the column decoder 5 and the row decoder 7 (step S3). Thereby, the threshold value of the memory cell transistor of the selected cell changes.

A variable write / erase verify voltage generator 4 applies a write or erase verify voltage to a selected word line via a row decoder 7, and a current flowing / non-flowing when a selected cell is turned on / off is column decoder. 5 through the sense amplifier. Thus, the sequence controller 2 determines whether the current threshold value of the selected cell satisfies the current verify voltage level. If it is determined that the current verify voltage level is not satisfied, the process returns to step S3, and if it is satisfied, the process proceeds to the next step (step S4).

Next, the sequence controller 2 determines whether or not the current verify voltage level is the final verify voltage level. If the current verify voltage level is the final verify voltage level, writing or erasing to the selected cell (bit) ends. (Step S5).

If it is not the final verify voltage level in step S5, the sequence controller 2 decreases the pulse voltage (absolute value) and / or pulse time applied to the variable write / erase pulse generator 4 for writing or erasing. (Step S6).

The sequence controller 2 controls the variable write / erase verify voltage generator 3 to update the verify voltage level and returns to step S3 (step S7).

While the above description has been directed to the writing or erasing of 1-bit information, erasing is generally performed collectively for multiple bits. In this case, the step S4
Is to determine whether any of the multiple bits to be erased satisfies the current verify voltage level. If any one bit satisfies the current verify voltage level, the process proceeds to step S5, and the same operation as described above is performed.

(Embodiment 1) FIGS. 3 to 20 show the case where the configuration shown in FIGS. 1 and 2 is applied to writing in a DINOR type or AND type flash memory.
In the odd-numbered figures, the procedure for applying the drain voltage Vd and the control gate voltage Vg during the write operation (ie, the procedure for applying the write pulse to the drain and control gate of the memory cell transistor of the selected cell)
The figure of the even-numbered figure shows the change of the threshold value Vth of the memory transistor accompanying the application of the write pulse, along with the verify voltage levels Vv1, Vv2 (and Vv3).

As shown in FIG. 3, a pulse voltage of a gate voltage (Vg) and a drain voltage (Vd) having the same absolute value for the first time is applied to the cell selected in step S2 for a time of 200 (μSEC). I do. The pulse voltage absolute value and the pulse time are initially set in step S1. At this time, the change in the threshold value of the selected cell in FIG. 4 decreases to the threshold value 8a (corresponding to step S3). If this situation is described with reference to FIG. 41, electrons are extracted from the floating gate 104 to the drain diffusion region 105 in response to application of a write pulse to the control gate terminal 100 and the drain terminal 101. Next, the current threshold value 8a is set to the verify voltage level Vv initially set in step S1.
It is determined whether or not 1 is satisfied (step S4). In this case, since the threshold value 8a does not satisfy the initially set verify voltage level Vv1, the operation returns to the operation of applying the pulse voltage in step S3. The second step S3 also
When the initially set pulse voltage of the gate voltage (Vg) and the drain voltage (Vd) having the same absolute value as shown in FIG. 3 is applied to 200 (μSEC), the threshold value of the selected cell becomes as shown in FIG. In step S4, it is determined whether or not the threshold value 8b satisfies the initially set verify voltage level Vv1. In this case, the operation is shifted to the next operation.

Next, it is determined whether the verify voltage level Vv1 is the final verify voltage level Vv2 (step S5). At this time, since it is not the final verify voltage level Vv2, the operation of decreasing the applied pulse voltage (drain voltage) is performed (step S6), and the verify voltage level is updated from Vv1 to Vv2 (step S7). Again, the third application of the pulse voltage is shown in FIG.
As shown in FIG. 4, when the drain voltage (Vd) is smaller than the absolute value of the normal pulse voltage value (dotted line) and the pulse voltage of the normal gate voltage (Vg) is applied for only 200 (μSEC), the selection in FIG. The cell threshold becomes the threshold 8c (step S3). Since the threshold value 8c at this time satisfies the current verify voltage level Vv2, the operation proceeds to the next operation (step S5).
4) Since the current verify voltage level Vv2 is the final verify voltage level (step S5), the writing ends.

As described above, the threshold value 7a in the conventional case (dotted line in FIG. 4) is lower than Vo, and an over-program failure occurs. However, in the present invention, when the threshold value of the memory cell transistor exceeds the verify voltage level Vv1 for the first time, the third drain voltage (write pulse) is lower than the first and second applied voltages. Thus, the writing is finally completed between the target verify voltage level Vv2 and the over-program level Vo.

In the above-described method, the over-program failure is prevented by reducing the absolute value of the applied pulse voltage. However, the same effect can be obtained by reducing the pulse time. The method will be described below.

As shown in FIGS. 5 and 6, the threshold voltages 9a and 9b are respectively obtained by applying the first and second pulse voltages to the selected cell as in FIG. Since the verify voltage level Vv1 is not the final verify voltage level, the process moves from step S5 to step S6. In step S6 of the current applied pulse voltage / pulse time reduction, the absolute value of the applied pulse voltage is not changed. Reduce the applied pulse time. Then, the verify voltage level is updated from Vv1 to Vv2 (step S7), and the application of the write pulse voltage of the gate voltage (Vg) and the drain voltage (Vd) having the same absolute value for the third time shown in FIG.
SEC) (step S3), the threshold 9c in FIG. 4 satisfies the current verify voltage level Vv2 and the final verify voltage level, and thus the operation ends (steps S4 and S).
5).

As described above, the threshold value 7a in the conventional case (dotted line in FIG. 6) reaches Vo, and an over-program failure occurs. However, in the present invention, when the threshold value of the memory cell transistor exceeds the verify voltage level Vv1 for the first time, the application time of the third writing pulse voltage is shorter than the application time of the first and second applications. As a result, finally, the target verify voltage level Vv2
The writing is completed between and the over program level Vo.

Similar effects can be obtained by reducing the absolute value and time of the applied pulse voltage by combining the above two methods. Hereinafter, the method will be described.

As shown in FIGS. 7 and 8, threshold voltages 10a and 10b are respectively obtained by applying the first and second pulse voltages to the selected cells as in FIG. In step S6 of reducing the applied pulse voltage / pulse time, both the absolute value of the applied pulse voltage and the applied pulse time are reduced. As a result, the gate voltage (Vg) whose absolute value is different from the first and second times shown in FIG.
When the application of the write pulse voltage of d) is performed at 100 (μSEC) (step S3), the threshold 10c in FIG. 8 satisfies the current verify voltage level Vv2 and the final verify voltage level, and thus the operation ends (steps S4 and S5). ).

As described above, the threshold value 8 shown in FIGS.
The threshold 10c stops near the final verify voltage level Vv2 than the threshold voltages c and 9c. As a result, FIG.
The writing is completed more effectively than the case of FIG. 6 while exceeding the target verify voltage level Vv2 and effectively preventing an over-program failure.

As described above, according to the nonvolatile semiconductor memory device and the threshold value control method of the first embodiment, the degree of change of the threshold value of the memory cell transistor can be changed by providing two verify voltage levels. As a result, it is possible to eliminate the over-program defect generated in the conventional technology.

(First Modification of First Embodiment) In the first embodiment, when the absolute value of the write pulse is changed,
By decreasing the absolute value of the drain voltage, the degree of change was changed so that the threshold value of the memory cell transistor did not fall below the overprogram level, but the absolute value of the gate voltage was changed instead of the drain voltage The same effect can be obtained. Hereinafter, the method will be described.

The first modification is the same in structure and operation as FIG. 3 of the first embodiment. Embodiment 1 and Modification 1
9 is that the absolute value of the gate voltage is reduced instead of the absolute value of the drain voltage in step S6 in FIG. 2 as shown in FIG. By doing this,
The threshold values 11a, 11b, and 11c as shown in FIG. 10 are obtained, and do not reach the over-program level Vo like the threshold value 7a in the conventional case.

Further, in addition to decreasing the absolute value of the gate voltage, by reducing the application time of the drain voltage and the gate voltage as shown in FIG. 11, the threshold values 12a, 12b and 12c in FIG. As a result, the operation is stopped near the verify voltage level Vv2 than the threshold value 11c.
In the vicinity of 2, the writing ends. Thus, over-program failure does not occur much more.

(Modification 2 of Embodiment 1) As described in Embodiment 1 and Modification 1, when the absolute value of the write pulse is changed, either the drain voltage or the gate voltage is changed. In this case, the object of the present invention can be achieved, but the same effect can be obtained when both the drain voltage and the gate voltage are changed.

In the second modification, the structural and functional aspects at the time of writing are the same as those in FIG. 3, and only the step S6 in FIG. 2 is changed.

In this case, as shown in FIG. 13, the absolute value of both the gate voltage and the drain voltage is reduced in the write pulse. By doing so, as shown in FIG.
The thresholds 13a, 13b, and 13c are obtained, and the threshold value 7a of the related art has reached the overprogram level Vo, but the writing ends between Vv2 and Vo without reaching Vo.

As shown in FIG. 15, in addition to the above, by reducing the application time of the drain voltage and the gate voltage in the write pulse, the threshold 14 shown in FIG.
a, 14b, and 14c are obtained, and the writing is completed in the vicinity of the verify voltage level Vv2 below the threshold 13c in FIG. This does not lead to further over-program failure.

(Modification 3 of Embodiment 1) The case where the verify voltage level is binary has been described above.
The present invention can be applied not only to the case of binary values but also to the case where the verify voltage level is ternary or more. Hereinafter, the method will be described.

The structure and operation procedure for writing are shown in FIG.
There is no difference from FIG. The only difference is that the number of times of executing the processing of steps S6 and S7 increases. It is to be noted that the present invention can be applied to general writing of three or more verify voltage levels, but the description will be limited to the simplest case of three values.

As shown in FIGS. 17 and 18, in the initial setting, the writing time is set to 200 (μSEC) (step S1). When a memory cell to be written is selected (step S2) and a pulse voltage is applied (step S3), the threshold value 15a is reached. Thereafter, it is determined whether or not the initially set verify voltage level Vv1 is satisfied (Step S).
4) In this case, since the verify voltage level Vv1 is satisfied, the process proceeds to the next step, and it is determined whether or not Vv1 is the final verify voltage level (Step S5).
Move to 6. Here, the absolute value of the drain voltage in the write pulse is reduced (step S6), the verify voltage level is updated from Vv1 to Vv2 (step S7), and when the write pulse voltage is applied again, the change rate changes and the threshold value changes. 15b (step S
3). Thereafter, the set verify voltage level Vv2
(Step S4), the process proceeds to Step S5, and since Vv2 is not the final verify voltage level, the absolute value of the write pulse voltage (drain voltage) is further reduced (Step S6). Thereafter, the verify voltage level is updated from Vv2 to Vv3 (step S7),
When a pulse voltage is applied to the selected cell, a threshold 15c (FIG. 1)
8) and not less than Vo (step S
3). Then, the current verify voltage level Vv3 is satisfied (step S4), and the write ends because Vv3 is the final verify voltage level (step S5).

As shown in FIGS. 19 and 20, in addition to the absolute value of both the drain voltage and the gate voltage in the write pulse, the threshold value when the applied pulse time is gradually reduced in the second and third times Are the thresholds 16a, 16b, 1
6c. Although the threshold value 7c of the prior art has reached the overprogram level Vo, the writing is completed between Vv3 and Vo and very close to the target Vv3 without reaching Vo.

As described above, when the verify voltage level is a ternary value, the over-program defect which has occurred in the prior art can be more effectively suppressed. Although the verification voltage level is limited to three values here, the present invention is applicable to four or more values, and even in this case, the threshold value is gradually increased as in threshold values 15a, 15b, and 15c shown in FIG. The degree of change changes.

As described above, the third modification of the first embodiment
According to the nonvolatile semiconductor memory device and the threshold control method according to the above, by providing three or more verify voltage levels, the degree of change of the threshold value of the memory cell transistor can be changed each time the verify voltage level is reached. As a result, it is possible to further eliminate over-program defects as compared with the case of binary.

(Embodiment 2) Next, a nonvolatile semiconductor memory device and a threshold control method thereof according to Embodiment 2 of the present invention will be described with reference to FIGS. In the second embodiment of the present invention, the configurations of FIGS.
This is applied to writing in an R-type flash memory, and the DINOR type or A
It differs from the ND type in that the gate voltage in the write pulse is positive.

In FIGS. 21 to 30, the odd-numbered figures show the procedure for applying the drain voltage Vd and the control gate voltage Vg during the write operation (ie, the procedure for applying the write pulse to the drain and control gate of the memory cell transistor of the selected cell). ), And the even-numbered figures show the change in the threshold voltage Vth of the memory transistor caused by the application of the write pulse to verify voltage levels Vv11 and Vv11.
It is a figure shown with v21 (and Vv31).

In the NOR flash memory, DINOR
Unlike the flash memory of the floating gate type 1 and the floating gate 1,
04 (FIG. 44), the threshold voltage of the selected cell increases. Therefore, in updating the verify voltage level in step S7 in FIG. 2, the verify voltage level is sequentially changed to a higher value.

The operation up to step S6 in FIG. 2 is the same as in the first embodiment. In step S6, as shown in FIG. 21, only the absolute value of the drain voltage in the write pulse is reduced, and then the verify voltage level Vv1
1 is updated to Vv21 (step S7), and a write pulse voltage is applied again (step S3). By doing so, as shown in FIG. 22, the thresholds 18a, 18b, 1
8c is obtained, and the threshold value 17 of the conventional technique has reached the overprogram level Vo1 or more, but the writing ends at the threshold value 18c accurately falling between Vv21 and Vo1 without reaching Vo1. As a result, even when a multi-valued memory is configured, over-program failure does not occur.

In step S6, as shown in FIG. 23, the application pulse time of the gate voltage and the drain voltage in the write pulse may be reduced (step S6).
7). In this case, as shown in FIG.
9b and 19c are obtained, and the threshold 17 of the prior art reaches the overprogram level Vo1 in the same manner as described above, but Vv21 and Vv21 do not reach Vo1.
The writing ends at the threshold value 19c that falls exactly between the threshold value o1.

In step S6, as shown in FIG. 25, both the application pulse time of the gate voltage and the drain voltage in the write pulse and the absolute value of the drain voltage may be reduced. By doing so, as shown in FIG. 26, the thresholds 20a, 20b, and 20c are obtained, and the threshold 17 of the related art reaches the overprogram level Vo1 instead of the threshold 17 of the prior art, as in the case described above. Instead, the writing ends with the threshold value 20c accurately falling between Vv21 and Vo1.

As described above, the final verify voltage level V is lower than the thresholds 18c and 19c in FIGS.
The threshold value 20c is stopped near v21. As a result, the writing is completed beyond the target verify voltage Vv21 more effectively than in the cases of FIGS.

As described above, according to the nonvolatile semiconductor memory device and the threshold value control method of the second embodiment, the degree of change of the threshold value of the memory cell transistor can be changed by providing two verify voltage levels. As a result, when a multi-valued memory is configured, it is possible to eliminate the over-program defect that has occurred in the conventional technique.

(Modification of Second Embodiment) The case where the verify voltage level has two values has been described above. However, as in the case of the third modification of the first embodiment, three or more verify voltage levels exist. In this case, it is also possible to apply to the second embodiment. Here, a case where there are three levels of verify voltage will be described.

As shown in FIG. 27, the absolute value of the drain voltage gradually decreases in the write pulse. When the writing pulse voltage is applied in this manner, the threshold values 22a, 22b, and 22c in FIG. 26 are reached, and the writing is completed. The threshold value 21 in the conventional case, which has become equal to or higher than the overprogram level Vo1, does not become equal to or higher than Vo1, and the writing ends with the threshold value 22c between Vo1 and Vv3. As a result, over-programming failure can be avoided in the multi-valued memory.

As shown in FIGS. 29 and 30, the application time may be reduced while the absolute value of both the drain voltage and the gate voltage is reduced in the write pulse. In this case, as shown in FIG. 30, the threshold value of the selected cell becomes the threshold value 23a, 23b, 23c, and the writing is completed. Therefore, the threshold value 21b in the conventional case is equal to or higher than the overprogram level Vo1, Vv
It falls exactly between 31 and Vo1, and ends. As a result, an over-program defect can be avoided in the multi-valued memory.

(Embodiment 3) Next, a nonvolatile semiconductor memory device and a threshold value control method thereof according to Embodiment 3 of the present invention will be described with reference to FIGS. In the third embodiment, the configuration shown in FIGS. 1 and 2 is applied to writing in a NAND flash memory, and the DINOR (AND) type and the N
Unlike the OR type, writing is performed by applying a voltage only to the control gate terminal.

In FIGS. 31 to 40, the odd-numbered figures show the procedure of applying the control gate voltage Vg during the write operation (ie, the procedure of applying the write pulse to the control gate of the memory cell transistor of the selected cell). And the even-numbered figures show the change in the threshold value Vth of the memory transistor accompanying the application of the write pulse, together with the verify voltage levels Vv12, Vv22 (and Vv32).

In the NAND flash memory, NOR
Since the injection of electrons into the floating gate 104 (FIG. 45) is performed in the write operation as in the case of the flash memory, the threshold voltage of the selected cell increases. Therefore, in updating the verify voltage level in step S7 in FIG. 2, the verify voltage level is sequentially changed to a higher value.

The operation up to step S6 in FIG. 2 is the same as in the first embodiment. In step S6, as shown in FIG. 31, the absolute value of the gate voltage in the write pulse is reduced, then the verify voltage level is updated from Vv12 to Vv22 (step S7), and the write pulse voltage is applied again (step S7). S3). By doing so, as shown in FIG. 32, the thresholds 25a, 25b, 25c
Is obtained, and the threshold value 24 of the conventional technique has reached the overprogram level Vo2 or more, but the writing ends at the threshold value 25c accurately falling between Vv22 and Vo2 without reaching Vo2. As a result, even when a multi-valued memory is configured, no over-program failure occurs.

In step S6, as shown in FIG. 33, the same effect as the above-mentioned technical idea can be obtained even if the application pulse time of the gate voltage in the write pulse is reduced. In this case, as shown in FIG.
6b and 26c are obtained, and the threshold value 24 of the prior art reaches the over-program level Vo2 in the same manner as described above.
The writing ends when the threshold value 26c falls exactly between the time o2 and the threshold value 26c.

Further, in step S6, as shown in FIG. 35, both the reduction of the application time of the gate voltage in the write pulse and the reduction of the absolute value of the gate voltage may be performed. In this case, as shown in FIG.
a, 27b, 27c are obtained, and the threshold value 24 of the prior art is set to the overprogram level Vo2 as in the case described above.
Has reached Vv2 without reaching Vo2.
Writing ends when the threshold value 26c falls exactly between 2 and Vo2.

As described above, the threshold 25c shown in FIG.
The threshold value 27c stops near the final verify voltage level Vv22. 32 and FIG.
4 is more effective than the target verify voltage Vv22.
, The writing ends.

As described above, the NAND of the third embodiment
According to the nonvolatile semiconductor memory device of the type and the threshold control method thereof, by providing two verify voltage levels, the degree of change of the threshold value of the memory cell transistor can be changed, and as a result, a multi-valued memory is configured. In this case, it is possible to eliminate the over-program defect that has occurred in the related art.

(Modification of Third Embodiment) The NAND
Although the case where the verify voltage level has two values in the nonvolatile semiconductor memory device of the type and the threshold control method thereof has been described, the object of the present invention can be similarly achieved even when the verify voltage level has three or more values. The ternary case will be described below.

As shown in FIG. 37, the absolute value of the gate voltage in the write pulse gradually decreases. When the write pulse voltage is applied in this manner, FIG.
Thus, the thresholds 29a, 29b, and 29c of 8 are reached, and the writing ends. The threshold 28 in the conventional case, which has become equal to or higher than the overprogram level Vo2, does not become equal to or higher than Vo2, and the threshold 2 accurately falls between Vo2 and Vv32.
The writing ends at 9c. As a result, over-programming failure can be avoided in the multi-valued memory.

As shown in FIGS. 39 and 40, both the absolute value of the gate voltage and the application time may be reduced in the write pulse. In this case, as shown in FIG. 40, the threshold values of the selected cells are set to the threshold values 30a, 30b, 30
c, the writing ends, and the threshold value 28b in the conventional case, which has become equal to or higher than the overprogram level Vo2, is accurately settled between Vv32 and Vo2 and ends. As a result, an over-program defect can be avoided in the multi-valued memory.

[0080]

According to the present invention, a pulse generator for generating a pulse for changing the threshold of a memory cell transistor, a verify voltage generator for verifying a change in the threshold of a memory cell transistor, Control means for reducing at least one of the absolute value of the pulse voltage and the pulse time in response to the threshold value falling between the first and second verify voltages when the threshold value of the memory cell transistor changes. In addition, the degree of change of the threshold value can be changed before the threshold value reaches the overprogram level in the writing or erasing of the memory cell transistor, and the occurrence of overprogram bits can be suppressed in both the writing and erasing operations of the memory cell transistor. There is an effect that a semiconductor memory device can be provided.

According to the second aspect of the present invention, by setting the verify voltage to the first to n-th (n ≧ 3) verify voltages, the first and second verify voltages are respectively changed when the threshold value of the memory cell transistor changes. , Between the third and fourth verify voltages,... Every time between the (n−1) th and n-th verify voltages, at least the absolute value of the pulse voltage of the pulse generator and the pulse time. By sequentially decreasing one of them, before the threshold reaches the overprogram level in writing or erasing the memory cell transistor,
There is an effect that a non-volatile semiconductor memory device can be provided in which the degree of change of the threshold can be sequentially changed, and the occurrence of over-program bits can be suppressed in both the write and erase operations of the memory cell transistor.

According to the third aspect of the present invention, at least one of the absolute value of the pulse voltage and the pulse time by the control means is reduced for the pulse applied to the drain of the memory cell transistor, so that at the time of writing and erasing, DINOR (AND) type that applies drain voltage, NOR
And NAND type flash memories, the threshold can be controlled and the occurrence of over-program bits can be suppressed.

According to the fourth aspect of the present invention, at least one of the absolute value of the pulse voltage and the pulse time by the control means is reduced for the pulse applied to the control gate of the memory cell transistor, thereby enabling writing,
DINOR (AND) for applying gate voltage during erase
And NOR type flash memories, there is an effect that the threshold can be controlled and the occurrence of overprogram bits can be suppressed.

According to the fifth aspect of the present invention, at least one of the absolute value of the pulse voltage and the pulse time is reduced by the control means with respect to the pulse applied to the drain and the control gate of the memory cell transistor. In addition, in a DINOR (AND) type or NOR type flash memory which applies a drain and a gate voltage at the time of erasing, a threshold value can be controlled, and there is an effect that generation of an overprogram bit can be suppressed.

According to the sixth aspect of the present invention, the first step of changing the threshold value at the first change rate while verifying the change of the threshold value of the memory cell transistor; A second step of changing the threshold value at a second change rate that is slower than the first change rate while verifying a change in the threshold value in response to the input between the second verify voltages. A nonvolatile semiconductor memory capable of changing the rate of change of the threshold before the threshold reaches the overprogram level in the writing or erasing of the memory cell transistor and suppressing the occurrence of overprogram bits in both the writing and erasing operations of the memory cell transistor. There is an effect that a threshold control method for the device can be provided.

According to the seventh aspect of the present invention, the threshold values are respectively between the first and second verify voltages, between the third and fourth verify voltages,... (N-1) and n-th. , By changing the threshold change rate gradually to a gradual change rate every time the verify voltage changes, the threshold change rate is changed before the threshold reaches the over-program level in writing and erasing of the memory cell transistor. Thus, there is an effect that a method of controlling a threshold value of a nonvolatile semiconductor memory device capable of suppressing occurrence of overprogram bits in both writing and erasing operations of a memory cell transistor can be provided.

According to the eighth aspect of the present invention, the change rate of the threshold value is changed by reducing at least one of the absolute value of the writing or erasing pulse voltage and the pulse time. Also, there is an effect that it is possible to provide a threshold control method for a nonvolatile semiconductor memory device that can change the rate of change of the threshold and can suppress the occurrence of overprogram bits in both the write and erase operations of the memory cell transistor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a nonvolatile semiconductor memory device according to first to third embodiments of the present invention.

FIG. 2 is a flowchart illustrating an operation procedure of a threshold control method for the nonvolatile semiconductor memory device according to the first to third embodiments of the present invention.

FIG. 3 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 10 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 11 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 12 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 13 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 14 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 15 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 16 is a graph showing a change in threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 17 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 18 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 19 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 20 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 21 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 22 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 23 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 24 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 25 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 26 is a graph showing a change in a threshold value of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 27 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 28 is a graph showing a change in threshold value of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 29 is a diagram showing an application sequence of a drain voltage and a gate voltage of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 30 is a graph showing a change in threshold value of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 31 is a diagram showing a gate voltage application sequence of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 32 is a graph illustrating a change in a threshold value of the nonvolatile semiconductor memory device according to the third embodiment of the present invention.

FIG. 33 is a diagram showing a gate voltage application sequence of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 34 is a graph showing a change in threshold value of the nonvolatile semiconductor memory device according to the third embodiment of the present invention.

FIG. 35 is a diagram showing a gate voltage application sequence of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 36 is a graph showing a change in threshold value of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 37 is a diagram showing a gate voltage application sequence of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 38 is a graph showing a change in threshold value of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 39 is a diagram showing a gate voltage application sequence of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 40 is a graph showing a change in threshold value of the nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.

FIG. 41 is a cross-sectional view illustrating a write operation of a conventional DINOR type nonvolatile semiconductor memory device.

FIG. 42 is a graph showing a change in a threshold value of a conventional nonvolatile semiconductor memory device.

FIG. 43 is a graph showing a change in threshold value of a conventional nonvolatile semiconductor memory device.

FIG. 44 is a cross-sectional view illustrating a write operation of a conventional NOR type nonvolatile semiconductor memory device.

FIG. 45 is a cross-sectional view illustrating a write operation of a conventional NAND-type nonvolatile semiconductor memory device.

[Explanation of symbols]

1 mode control circuit, 2 sequence controller, 3
Variable write / erase verify voltage generator, 4 variable write / erase pulse generator, 5 column decoder (sense amplifier), 6 memory cell array, 7 row decoder.

Claims (8)

[Claims] 1. A non-volatile semiconductor memory device having a memory cell array and storing information by changing a threshold value of a memory transistor in the memory cell array, wherein a pulse for changing the threshold value of the memory cell transistor is provided. A verifying voltage generator that generates a verifying voltage for verifying a change in a threshold value of the memory cell transistor due to the pulse, wherein the pulse has at least one of a pulse voltage and a pulse time that is variable. In addition, the verify voltage includes at least first and second verify voltages, and when the threshold value of the memory cell transistor changes, in response to the threshold value falling between the first and second verify voltages. The absolute value of the pulse voltage in the pulse generator, A non-volatile semiconductor storage device, further comprising control means for reducing at least one of the storage time. 2. The method according to claim 1, wherein the verifying voltages are first to n-th (n ≧ n)
3) the control means includes: when the threshold value of the memory cell transistor changes, when the threshold value is between the first and second verify voltages,
During the second and third verify voltages, the (n-
1) The non-volatile memory according to claim 1, wherein at least one of the absolute value of the pulse voltage and the pulse time in the pulse generator is sequentially decreased in response to the n-th verify voltage every time. Semiconductor storage device. 3. The nonvolatile memory according to claim 1, wherein at least one of the absolute value of the pulse voltage and the pulse time by the control unit is decreased for the pulse applied to the drain of the memory cell transistor. Semiconductor storage device. 4. The non-volatile memory according to claim 1, wherein at least one of the absolute value of the pulse voltage and the pulse time by the control unit is decreased for the pulse applied to the control gate of the memory cell transistor. Semiconductor memory device. 5. The method according to claim 1, wherein at least one of the absolute value of the pulse voltage and the pulse time by the control unit is reduced for the pulse applied to the drain and the control gate of the memory cell transistor. Nonvolatile semiconductor memory device. 6. A method of controlling a threshold value of a nonvolatile semiconductor memory device having a memory cell array and storing information by changing a threshold value of a memory cell transistor in the memory cell array, comprising: A first step of changing the threshold value at a first rate of change while verifying, and responding to the threshold value having entered between a first verify voltage and a second verify voltage in the first step. A second step of changing the threshold value at a second change rate that is gentler than the first change rate while verifying the change of the threshold value. 7. The method according to claim 6, wherein the threshold value is between the first and second verify voltages, between the second and third verify voltages,.
-1) changing the threshold while gradually changing the threshold change rate to a gradual change rate in response to the nth verify voltage (n ≧ 3). 7. The threshold value control method for a nonvolatile semiconductor memory device according to claim 6, wherein 8. Changing the change rate of the threshold value of the memory cell transistor reduces at least one of an absolute value of a pulse voltage and a pulse time of a pulse applied to the memory cell transistor to change the threshold value. 8. The method of controlling a threshold value of a nonvolatile semiconductor memory device according to claim 6, wherein