JP2000030448A - 同期型半導体記憶装置 - Google Patents

同期型半導体記憶装置

Info

Publication number
JP2000030448A
JP2000030448A JP10200655A JP20065598A JP2000030448A JP 2000030448 A JP2000030448 A JP 2000030448A JP 10200655 A JP10200655 A JP 10200655A JP 20065598 A JP20065598 A JP 20065598A JP 2000030448 A JP2000030448 A JP 2000030448A
Authority
JP
Japan
Prior art keywords
signal
control signal
memory
block
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10200655A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000030448A5 (enExample
Inventor
Takeshi Araki
岳史 荒木
Kenichi Yasuda
憲一 安田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10200655A priority Critical patent/JP2000030448A/ja
Priority to US09/225,450 priority patent/US6052331A/en
Publication of JP2000030448A publication Critical patent/JP2000030448A/ja
Publication of JP2000030448A5 publication Critical patent/JP2000030448A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
JP10200655A 1998-07-15 1998-07-15 同期型半導体記憶装置 Pending JP2000030448A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10200655A JP2000030448A (ja) 1998-07-15 1998-07-15 同期型半導体記憶装置
US09/225,450 US6052331A (en) 1998-07-15 1999-01-06 Synchronous semiconductor device allowing reduction in chip area by sharing delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10200655A JP2000030448A (ja) 1998-07-15 1998-07-15 同期型半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2000030448A true JP2000030448A (ja) 2000-01-28
JP2000030448A5 JP2000030448A5 (enExample) 2005-10-20

Family

ID=16428029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10200655A Pending JP2000030448A (ja) 1998-07-15 1998-07-15 同期型半導体記憶装置

Country Status (2)

Country Link
US (1) US6052331A (enExample)
JP (1) JP2000030448A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030057949A (ko) * 2001-12-29 2003-07-07 삼성전자주식회사 정밀한 동작점 설정이 가능한 입출력 감지 증폭기를구비하는 동기식 디램 반도체 장치
JP2007265548A (ja) * 2006-03-29 2007-10-11 Elpida Memory Inc 積層メモリ

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000067577A (ja) 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2001067866A (ja) 1999-08-30 2001-03-16 Mitsubishi Electric Corp 同期型半導体記憶装置
KR100336787B1 (ko) * 2000-01-07 2002-05-16 박종섭 배선을 줄일 수 있는 반도체 메모리 회로 배치
KR100387719B1 (ko) * 2000-12-29 2003-06-18 주식회사 하이닉스반도체 반도체 메모리 장치 및 그의 메모리 셀 블록 활성화 제어방법
US6661721B2 (en) * 2001-12-13 2003-12-09 Infineon Technologies Ag Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits
DE10319158A1 (de) * 2003-04-29 2004-11-25 Infineon Technologies Ag Vorrichtung zum flexiblen Deaktivieren von Wortleitungen von dynamischen Speicherbausteinen und Verfahren hierfür
US7752364B2 (en) * 2006-12-06 2010-07-06 Mosaid Technologies Incorporated Apparatus and method for communicating with semiconductor devices of a serial interconnection
US7865756B2 (en) * 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
WO2009062280A1 (en) * 2007-11-15 2009-05-22 Mosaid Technologies Incorporated Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
US8467486B2 (en) * 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US8145925B2 (en) * 2007-12-21 2012-03-27 Mosaid Technologies Incorporated Non-volatile semiconductor memory device with power saving feature
US8291248B2 (en) 2007-12-21 2012-10-16 Mosaid Technologies Incorporated Non-volatile semiconductor memory device with power saving feature
JP2013097843A (ja) 2011-11-02 2013-05-20 Toshiba Corp 半導体記憶装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
US5384726A (en) * 1993-03-18 1995-01-24 Fujitsu Limited Semiconductor memory device having a capability for controlled activation of sense amplifiers
JP3304531B2 (ja) * 1993-08-24 2002-07-22 富士通株式会社 半導体記憶装置
JPH08221981A (ja) * 1994-12-15 1996-08-30 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH09223389A (ja) * 1996-02-15 1997-08-26 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH10283779A (ja) * 1997-04-09 1998-10-23 Mitsubishi Electric Corp 同期型半導体記憶装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030057949A (ko) * 2001-12-29 2003-07-07 삼성전자주식회사 정밀한 동작점 설정이 가능한 입출력 감지 증폭기를구비하는 동기식 디램 반도체 장치
JP2007265548A (ja) * 2006-03-29 2007-10-11 Elpida Memory Inc 積層メモリ

Also Published As

Publication number Publication date
US6052331A (en) 2000-04-18

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