JP2000026841A - Method for abrasion of semiconductor substrate and preparation of semiconductor equipment - Google Patents

Method for abrasion of semiconductor substrate and preparation of semiconductor equipment

Info

Publication number
JP2000026841A
JP2000026841A JP10200581A JP20058198A JP2000026841A JP 2000026841 A JP2000026841 A JP 2000026841A JP 10200581 A JP10200581 A JP 10200581A JP 20058198 A JP20058198 A JP 20058198A JP 2000026841 A JP2000026841 A JP 2000026841A
Authority
JP
Japan
Prior art keywords
polishing
abrasive
polished
alumina
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10200581A
Other languages
Japanese (ja)
Inventor
Katsumi Yamamoto
克美 山本
Atsushi Shigeta
厚 重田
Nobuhiro Kato
信広 加藤
Yoji Kashiwabara
洋史 柏原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP10200581A priority Critical patent/JP2000026841A/en
Priority to KR1019990028520A priority patent/KR20000011718A/en
Publication of JP2000026841A publication Critical patent/JP2000026841A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09GPOLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00Polishing compositions
    • C09G1/02Polishing compositions containing abrasives or grinding agents
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09KMATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00Materials not provided for elsewhere
    • C09K3/14Anti-slip materials; Abrasives
    • C09K3/1454Abrasive powders, suspensions and pastes for polishing
    • C09K3/1463Aqueous liquid suspensions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation

Abstract

PROBLEM TO BE SOLVED: To decrease a defect arising on semiconductor substrate, retain an abrasion speed level so that productibity is not harmed and enable stable abrasion treatment by using an abrasive in which an alumina content of corundum structure crystal contained in an abrasive particle thereof is controlled in a specific range. SOLUTION: An abrasive in which an alumina content of corundum structure crystal is controlled in a range of 4-16% is used. An abrasion area is arranged on an abrasion stationary board, a substance to be abraded having an area to be abraded is holding in a holding section at a site oppsite to the abrasion area, the abrasive contained a controlled abrasive particle is supplied on the abrasion area, pressure is applied to between the holding section and the abrasion stationary board, and the abrasion area and the area to be abraded is slided therebetween to abrade the substance to be abraded. The abrasive is a liquid abrasive comprising a mixture of the abrasive particle, an oxidizing agent and pure water. The alumina is used as the abrasive particle. As the oxidizing agent, e.g. ferric nitrate is used.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の研磨
方法および製造方法に係り、特に化学・機械的研磨(C
MP)技術を用いた半導体ウエハの研磨方法およびそれ
を用いた半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for polishing a semiconductor device and a method for manufacturing the same, and more particularly to a method for polishing a semiconductor device by chemical mechanical polishing (C
The present invention relates to a method for polishing a semiconductor wafer using the MP) technique and a method for manufacturing a semiconductor device using the same.

【0002】[0002]

【従来の技術】現在の超々大規模集積回路(ULSI)
では、トランジスタおよび他の半導体素子を縮小して実
装密度を高める傾向にある。このため、種々の微細加工
技術が研究・開発されており、デザインルールにおいて
は既にサブミクロンのオーダーとなっている。
2. Description of the Related Art Today's ultra-large-scale integrated circuits (ULSI)
Then, there is a tendency to increase the packing density by reducing the size of transistors and other semiconductor elements. For this reason, various microfabrication techniques have been researched and developed, and the design rules are already on the order of submicron.

【0003】そのような厳しい微細化の要求を満たすた
めに開発されている技術の一つにCMPがある。このC
MPは、半導体装置の製造工程において、例えば埋め込
み金属配線形成、層間絶縁膜の平坦化、プラグ形成、埋
め込み素子分離、埋め込みキャパシタ形成等を行う際に
必須となる技術である。
[0003] CMP is one of the technologies that have been developed to satisfy such strict requirements for miniaturization. This C
MP is a technology that is indispensable in the process of manufacturing a semiconductor device, for example, when forming a buried metal wiring, flattening an interlayer insulating film, forming a plug, separating a buried element, forming a buried capacitor, and the like.

【0004】このCMP技術は、研磨粒子を含む研磨剤
(研磨液)を研磨面の上に供給し、被研磨面を有する基
板を研磨面に押圧しながら摺動させることにより、基板
上の被研磨膜を化学・機械的に研磨するものである。こ
の時の研磨粒子には種々の材料が用いられるが、金属配
線形成およびプラグ形成等にはアルミナを主成分とする
ものが使われることが多い。
In this CMP technique, an abrasive (polishing liquid) containing abrasive particles is supplied onto a polishing surface, and a substrate having a surface to be polished is slid while being pressed against the polishing surface, whereby the substrate is polished. A polishing film is chemically and mechanically polished. Various materials are used for the abrasive particles at this time, but those mainly composed of alumina are often used for forming metal wiring and plugs.

【0005】図7(a)〜(c)は、CMP技術を用い
た埋め込み金属配線形成工程を示す断面図である。ま
ず、図7(a)に示すように、半導体基板上に絶縁膜1
1を形成し、その上に通常のフォトリソグラフィー法お
よびエッチング法を用いて配線溝を形成する。次いで、
PVD(物理的堆積)法もしくはCVD(化学気相成
長)法により金属膜12を形成した後、研磨処理を行
い、埋め込み金属配線を形成する。
FIGS. 7A to 7C are cross-sectional views showing a step of forming a buried metal wiring using the CMP technique. First, as shown in FIG. 7A, an insulating film 1 is formed on a semiconductor substrate.
1 is formed thereon, and a wiring groove is formed thereon by using ordinary photolithography and etching. Then
After the metal film 12 is formed by a PVD (physical deposition) method or a CVD (chemical vapor deposition) method, a polishing process is performed to form a buried metal wiring.

【0006】ここで、絶縁膜上まで研磨処理が行われた
場合の断面形状を図7(b)に示しており、研磨後の表
面状態の一例を図7(c)に示している。被研磨膜の研
磨量および被研磨面の表面状態は、研磨中の押圧力、基
板と研磨面との摺動速度、研磨剤の種類および供給量、
研磨時間、研磨面の状態等に依存するが、その変数の多
くは研磨装置により制御されている。
FIG. 7B shows a cross-sectional shape when the polishing process is performed on the insulating film, and FIG. 7C shows an example of the surface state after polishing. The polishing amount of the film to be polished and the surface state of the surface to be polished are the pressing force during polishing, the sliding speed between the substrate and the polished surface, the type and supply amount of the abrasive,
Although it depends on the polishing time, the state of the polishing surface, and the like, many of the variables are controlled by the polishing apparatus.

【0007】また、研磨剤中の研磨粒子や化学薬品等の
含有量を一定に保つためには、正確な秤量および化学成
分の定量分析等により制御されているが、実際には研磨
により、図7(c)中に示すようなスクラッチ(欠陥)
13が基板に発生してしまう。
In order to keep the content of abrasive particles and chemicals in the polishing agent constant, it is controlled by accurate weighing and quantitative analysis of chemical components. Scratch (defect) as shown in 7 (c)
13 are generated on the substrate.

【0008】ここで生じる欠陥13は、基板内部にダメ
ージを与える他に、研磨工程の後に続く半導体製造工程
との組合せにより、例えば図8(a)、(b)に示すよ
うな製品不良を引き起こす原因となる。
[0008] The defect 13 caused here causes damage to the inside of the substrate and causes a product defect as shown in FIGS. 8A and 8B, for example, in combination with a semiconductor manufacturing process following the polishing process. Cause.

【0009】即ち、図8(a)に示すように、前記金属
配線12の形成後に層間絶縁膜14を形成し、その上に
通常のフォトリソグラフィー法およびエッチング法を用
いて下層の金属配線膜までの貫通穴を形成する。
That is, as shown in FIG. 8A, an interlayer insulating film 14 is formed after the formation of the metal wiring 12, and a lower metal wiring film is formed thereon by using ordinary photolithography and etching. Is formed.

【0010】次いで、PVD法もしくはCVD法により
プラグ形成用の金属膜を形成した後、研磨処理を行いプ
ラグ15を形成する。この際、プラグ形成用の金属膜の
うちで前記金属配線の形成工程にて発生したスクラッチ
箇所の上方に対応する一部15aが研磨処理にて除去さ
れずに残留してしまう。
Next, after a metal film for forming a plug is formed by a PVD method or a CVD method, a polishing process is performed to form a plug 15. At this time, a portion 15a of the metal film for forming the plug, which corresponds to the portion above the scratch generated in the step of forming the metal wiring, remains without being removed by the polishing process.

【0011】従って、図8(b)に示すように、前記プ
ラグ15の形成後に上層の金属配線17を形成すると、
配線間ショートが発生する。因みに、従来の研磨方法で
用いた研磨剤のロットと製品不良(欠陥数)との関係は
例えば図9に示すようになり、研磨剤のロットにより欠
陥数が変動してしまうこと、製品不良を多く引き起こし
ていることが分かる。
Therefore, as shown in FIG. 8B, when the upper metal wiring 17 is formed after the formation of the plug 15,
Short circuit between wirings occurs. Incidentally, the relationship between the lot of the abrasive used in the conventional polishing method and the product defect (the number of defects) is, for example, as shown in FIG. 9, and the number of defects varies depending on the lot of the abrasive. You can see that it is causing a lot.

【0012】[0012]

【発明が解決しようとする課題】上記したように従来の
半導体装置の研磨方法および製造方法は、安定した研磨
処理ができず、研磨剤のロットにより欠陥数が変動し、
製品不良を多く引き起こすという問題があった。
As described above, the conventional method for polishing and manufacturing a semiconductor device cannot perform a stable polishing process, and the number of defects varies depending on the lot of the polishing agent.
There was a problem that many product defects were caused.

【0013】本発明は上記の問題点を解決すべくなされ
たもので、半導体基板上に発生する欠陥を低減し、且
つ、生産性を損わない程度の研磨速度を維持し、安定し
た研磨処理が可能になる半導体装置の研磨方法を提供す
ることを目的とする。また、本発明の他の目的は、生産
性を損なわない程度に研磨速度を維持しつつ欠陥の発生
を抑制し得る半導体装置の製造方法製造方法を提供する
ことにある。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is intended to reduce defects occurring on a semiconductor substrate, maintain a polishing rate that does not impair productivity, and perform a stable polishing process. It is an object of the present invention to provide a method for polishing a semiconductor device, which enables the polishing. Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing the occurrence of defects while maintaining a polishing rate to such an extent that productivity is not impaired.

【0014】[0014]

【課題を解決するための手段】本発明の半導体基板の研
磨方法は、半導体基板の研磨工程に使用される研磨粒子
を含む研磨剤として、前記研磨粒子中に含まれるコラン
ダム型結晶であるアルミナが4%以上16%以下である
ように管理されたものを用いることを特徴とする。
According to the method for polishing a semiconductor substrate of the present invention, as a polishing agent containing abrasive particles used in a polishing step of a semiconductor substrate, alumina which is a corundum type crystal contained in the polishing particles is used. It is characterized in that a material managed so as to be 4% or more and 16% or less is used.

【0015】本発明の半導体基板の研磨方法は、研磨定
盤上に研磨面を設け、この研磨面と対向した位置に設け
られた保持部に被研磨面を有する被研磨物を保持する工
程と、前記研磨面の上に研磨粒子を含む研磨剤を供給
し、前記保持部と前記研磨定盤との間に圧力をかけて前
記研磨面と前記被研磨面とを摺動させることにより前記
被研磨物を研磨する工程とを具備し、前記研磨剤とし
て、前記研磨粒子中に含まれるコランダム型結晶である
アルミナが4%以上16%以下であるように管理された
ものを用いることを特徴とする。
The method for polishing a semiconductor substrate according to the present invention comprises the steps of: providing a polished surface on a polishing platen; and holding an object to be polished having a surface to be polished on a holding portion provided at a position facing the polished surface. A polishing agent containing abrasive particles is supplied onto the polishing surface, and pressure is applied between the holding portion and the polishing platen to slide the polishing surface and the surface to be polished. Polishing the polished material, and using, as the abrasive, one controlled so that alumina, which is a corundum type crystal contained in the abrasive particles, is at least 4% and at most 16%. I do.

【0016】本発明の半導体装置の製造方法は、半導体
基板上に被研磨膜を形成する工程と、前記被研磨膜の少
なくとも一部を、研磨粒子中に含まれるコランダム型結
晶であるアルミナが4%以上16%以下であるように管
理された研磨剤により研磨する工程とを具備することを
特徴とする。
According to the method of manufacturing a semiconductor device of the present invention, a step of forming a film to be polished on a semiconductor substrate, and at least a part of the film to be polished is made of alumina, which is a corundum type crystal contained in polishing particles, of 4%. % By using an abrasive controlled to be at least 16%.

【0017】[0017]

【発明の実施の形態】本発明者らは、研磨粒子中に含ま
れるコランダム型結晶であるアルミナ(α−アルミナ)
の含有量に対する基板上の欠陥と被研磨膜の研磨速度と
の関係から、生産性を損わない程度の研磨速度を維持し
つつ欠陥の発生を抑制し、安定した研磨を行えることを
見出し、この知見に基づいて本発明をするに至った。
BEST MODE FOR CARRYING OUT THE INVENTION The inventors of the present invention have proposed alumina (α-alumina) which is a corundum type crystal contained in abrasive particles.
From the relationship between the defect rate on the substrate and the polishing rate of the film to be polished with respect to the content of, the occurrence of defects is suppressed while maintaining the polishing rate so as not to impair productivity, and it was found that stable polishing can be performed. The present invention has been made based on this finding.

【0018】以下、図面を参照して本発明の実施の形態
を詳細に説明する。 <半導体装置の研磨方法の第1実施例>研磨方法の第1
実施例では、研磨剤として、研磨粒子、酸化剤、純水を
混合した研磨液を用いた。酸化剤としては硝酸第二鉄
を、研磨粒子としてはアルミナを使用し、アルミナ粒子
中に含まれるコランダム型結晶であるアルミナの含有量
を変えることで数種類の研磨剤を作成した。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. <First Embodiment of Polishing Method for Semiconductor Device> First Embodiment of Polishing Method
In the example, a polishing liquid in which abrasive particles, an oxidizing agent, and pure water were mixed was used as the polishing agent. Ferric nitrate was used as an oxidizing agent and alumina was used as abrasive particles, and several types of abrasives were prepared by changing the content of alumina, which is a corundum crystal contained in the alumina particles.

【0019】また、被研磨膜としては二種類用意した。
図1(a)は、第1の被研磨膜を示しており、シリコン
基板31上にCVD法により酸化珪素膜32を形成した
ものである。
Two types of films to be polished were prepared.
FIG. 1A shows a first film to be polished, in which a silicon oxide film 32 is formed on a silicon substrate 31 by a CVD method.

【0020】図1(b)は、第2の被研磨膜を示してお
り、シリコン基板41上にCVD法により酸化珪素膜4
2を形成した後、さらにPVD法によりバリアメタル
(Barrier Metal )43を形成し、その上にCVD法に
よりタングステン膜44を形成したものである。
FIG. 1B shows a second film to be polished, and a silicon oxide film 4 is formed on a silicon substrate 41 by a CVD method.
2, a barrier metal (Barrier Metal) 43 is further formed by a PVD method, and a tungsten film 44 is formed thereon by a CVD method.

【0021】また、研磨装置としては、例えば図2に示
すような通常の研磨装置を用いた。図2に示す研磨装置
は、回転可能な研磨定盤51と、研磨定盤51上に貼付
された研磨布52と、研磨定盤51の上方に配置されて
いる回転可能な真空チャックホルダ53と、研磨定盤5
1の上方に配置されているダイヤモンド粒子が電着され
た回転可能なプレート54と、研磨剤撹拌機能を有する
研磨剤タンク(図示せず)に接続され、研磨剤吐出部が
研磨布52近傍まで延出した研磨剤供給用配管55とか
ら構成されている。
As the polishing apparatus, for example, an ordinary polishing apparatus as shown in FIG. 2 was used. The polishing apparatus shown in FIG. 2 includes a rotatable polishing table 51, a polishing cloth 52 stuck on the polishing table 51, and a rotatable vacuum chuck holder 53 disposed above the polishing table 51. , Polishing table 5
1 is connected to a rotatable plate 54 on which diamond particles are electrodeposited and a polishing tank (not shown) having a polishing agent stirring function, and a polishing agent discharge portion is brought to the vicinity of the polishing cloth 52. And an extended abrasive supply pipe 55.

【0022】上記研磨剤供給用配管55は、研磨剤の供
給量を制御する手段を備えている。被研磨膜50は、前
記研磨布52に被研磨面が対向するように前記真空チャ
ックホルダ53に真空チャックされる。被研磨膜50が
研磨布52に当接するときの圧力は、圧縮空気により任
意に制御できるようになっている。
The abrasive supply pipe 55 has a means for controlling the supply amount of the abrasive. The film to be polished 50 is vacuum-chucked to the vacuum chuck holder 53 so that the surface to be polished faces the polishing cloth 52. The pressure at which the film-to-be-polished 50 contacts the polishing pad 52 can be arbitrarily controlled by compressed air.

【0023】前記各研磨剤毎に、それを用いて前記酸化
珪素膜32の研磨、前記タングステン膜44の研磨を行
った。この場合、前記研磨装置の研磨布52としては通
常使用されているもの(例えばポリウレタン)を用い
た。そして、研磨布52の再生は研磨後に行い、ダイヤ
モンドが電着されているプレート54により行った。
The polishing of the silicon oxide film 32 and the polishing of the tungsten film 44 were performed using the respective polishing agents. In this case, a commonly used polishing cloth (for example, polyurethane) was used as the polishing cloth 52 of the polishing apparatus. Regeneration of the polishing cloth 52 was performed after polishing, and was performed using a plate 54 on which diamond was electrodeposited.

【0024】また、研磨の際の押圧力や研磨剤の供給
量、基板50と研磨定盤51の相対回転速度について
は、通常の条件(例えば、研磨圧力200gf/cm
2 、研磨定盤51および真空チャックホルダ53の回転
数50rpm、研磨剤供給量200ml/min)を採
用した。
The pressing force during polishing, the supply amount of the abrasive, and the relative rotation speed between the substrate 50 and the polishing platen 51 are determined under normal conditions (for example, a polishing pressure of 200 gf / cm.
2. The rotation speed of the polishing platen 51 and the vacuum chuck holder 53 was 50 rpm, and the abrasive supply amount was 200 ml / min.

【0025】なお、研磨粒子の平均粒径は、0.01〜
5.0μmであることが望ましい。この理由は、研磨粒
子の平均粒径が0.01μm未満であると研磨速度が低
くなりすぎ、5.0μmを超えると被研磨膜の欠陥の原
因になるからである。
The average particle size of the abrasive particles is from 0.01 to
Desirably, it is 5.0 μm. The reason is that if the average particle size of the abrasive particles is less than 0.01 μm, the polishing rate becomes too low, and if the average particle size exceeds 5.0 μm, it causes defects of the film to be polished.

【0026】上記したような研磨条件で一定時間研磨を
行った後、酸化珪素膜32上およびタングステン膜44
上の欠陥数、酸化珪素膜32およびタングステン膜44
の残膜量を測定し、研磨前後の膜厚差から酸化珪素膜3
2およびタングステン膜44の研磨速度を算出した。
After polishing for a certain period of time under the above-described polishing conditions, the silicon oxide film 32 and the tungsten film 44 are polished.
Number of defects, silicon oxide film 32 and tungsten film 44
Of the silicon oxide film 3 was determined from the difference in film thickness before and after polishing.
2 and the polishing rate of the tungsten film 44 were calculated.

【0027】この場合、欠陥数の測定には画像処理方式
の測定器を用い、酸化珪素膜32の膜厚の測定には光干
渉式膜厚測定器を用い、タングステン膜44の膜厚の算
出にはシート抵抗測定器を用いた。
In this case, an image processing type measuring device is used for measuring the number of defects, and a light interference type film thickness measuring device is used for measuring the film thickness of the silicon oxide film 32, and the film thickness of the tungsten film 44 is calculated. , A sheet resistance measuring instrument was used.

【0028】図3(a)は、研磨方法の第1実施例に係
わる研磨粒子中に含まれるコランダム型結晶であるアル
ミナ( α−アルミナ) の含有量に対する基板上の欠陥数
の関係を示した。
FIG. 3 (a) shows the relationship between the number of defects on the substrate and the content of alumina (α-alumina), which is a corundum type crystal, contained in abrasive particles according to the first embodiment of the polishing method. .

【0029】図3(b)は、研磨方法の第1実施例に係
わる研磨粒子中に含まれるコランダム型結晶であるアル
ミナ( α−アルミナ) の含有量に対する被研磨膜の研磨
速度の関係を示した。
FIG. 3 (b) shows the relationship between the polishing rate of the film to be polished and the content of alumina (α-alumina) which is a corundum type crystal contained in the polishing particles according to the first embodiment of the polishing method. Was.

【0030】図3(a)に示すように、α―アルミナの
含有量が高いほど欠陥数が多くなる傾向にあり、4%〜
16%では少ない数で安定していることが分かる。ま
た、図3(b)に示すように、α―アルミナの含有量が
高いほど酸化珪素膜32およびタングステン膜44の研
磨速度も速くなる傾向にあるが、4%〜16%では酸化
珪素膜32に対するタングステン膜44の研磨速度比は
十分に大きく、且つ、安定していることが分かる。
As shown in FIG. 3A, as the content of α-alumina increases, the number of defects tends to increase.
It can be seen that a small number is stable at 16%. As shown in FIG. 3B, the polishing rate of the silicon oxide film 32 and the tungsten film 44 tends to be higher as the content of α-alumina is higher. It can be understood that the polishing rate ratio of the tungsten film 44 to the polishing rate is sufficiently large and stable.

【0031】これらのことから、研磨粒子中のα―アル
ミナの含有量を4%〜16%に管理することにより、生
産性を損わない程度のタングステン膜Wの研磨速度を維
持しつつ欠陥の発生を抑制できることが分かる。
From these facts, by controlling the content of α-alumina in the abrasive particles to 4% to 16%, it is possible to maintain the polishing rate of the tungsten film W to the extent that productivity is not impaired while maintaining the polishing rate of defects. It can be seen that generation can be suppressed.

【0032】<半導体装置の製造方法の第1実施例>次
に、実際に埋め込み金属配線を形成する時の研磨工程に
前記研磨方法の第1実施例を適用した結果について、図
4(a)、(b)および図5を参照しながら詳細に説明
する。
<First Embodiment of Manufacturing Method of Semiconductor Device> Next, FIG. 4A shows the result of applying the first embodiment of the polishing method to the polishing step when actually forming the buried metal wiring. , (B) and FIG. 5 will be described in detail.

【0033】図4(a)は、被研磨膜を示しており、シ
リコン基板71上に酸化珪素膜72を形成し、その上に
通常のフォトリソグラフィー法およびエッチング法を用
いて配線溝を形成した後、PVD法によりバリアメタル
73を形成し、さらにCVD法によりタングステン膜7
4を形成したものである。
FIG. 4 (a) shows a film to be polished. A silicon oxide film 72 is formed on a silicon substrate 71, and a wiring groove is formed thereon by using a usual photolithography method and an etching method. Thereafter, a barrier metal 73 is formed by a PVD method, and a tungsten film 7 is formed by a CVD method.
4 is formed.

【0034】このような被研磨膜に対して、図2に示し
た研磨装置を用いて、図4(b)に示すように、酸化珪
素膜72上まで研磨を行った。この時の研磨処理は、前
記研磨方法の第1実施例と同様の研磨条件を用いた。ま
た、研磨後の欠陥測定は画像処理方式の測定器を用い
た。
The film to be polished was polished up to the silicon oxide film 72 as shown in FIG. 4B using the polishing apparatus shown in FIG. The polishing process at this time used the same polishing conditions as in the first embodiment of the polishing method. The measurement of defects after polishing was performed using an image processing type measuring instrument.

【0035】図5は、半導体装置の製造に際して、前記
研磨方法の第1実施例を適用する前(従来)と適用後
(本実施例)における研磨剤ロットと製品欠陥数との関
係を示した。
FIG. 5 shows the relationship between the abrasive lot and the number of product defects before (conventional) and after (this embodiment) the first embodiment of the polishing method is applied in the manufacture of a semiconductor device. .

【0036】この図5から、研磨粒子に含まれるα―ア
ルミナの含有量を管理することにより、欠陥の発生を抑
制できることが分かる。即ち、半導体装置の製造方法の
第1実施例によれば、アルミナ粒子を含む研磨剤を用い
て半導体基板上に成膜した膜を研磨する際、研磨粒子中
に含まれるコランダム型結晶であるアルミナの含有量を
4%以上16%以下に管理した研磨剤を使用することに
より、基板への欠陥数の発生を抑制(低減)できるとと
もに、生産性を損なわない程度に被研磨膜の研磨速度を
維持することができる。
FIG. 5 shows that the occurrence of defects can be suppressed by controlling the content of α-alumina contained in the abrasive particles. That is, according to the first embodiment of the method for manufacturing a semiconductor device, when polishing a film formed on a semiconductor substrate using an abrasive containing alumina particles, the alumina which is a corundum type crystal contained in the abrasive particles is used. The use of an abrasive whose content is controlled to 4% or more and 16% or less can suppress (reduce) the number of defects on the substrate and reduce the polishing rate of the film to be polished to such an extent that productivity is not impaired. Can be maintained.

【0037】しかも、金属配線形成およびプラグ形成等
の金属膜を研磨し、絶縁膜で研磨を停止させる研磨工程
では、絶縁膜に対する金属膜の研磨速度比が十分に大き
く、且つ安定であることが望まれるが、本発明によれ
ば、速度比の十分大きい安定な研磨が行える。
In addition, in the polishing step of polishing the metal film such as the formation of the metal wiring and the plug and stopping the polishing at the insulating film, the polishing rate ratio of the metal film to the insulating film must be sufficiently large and stable. Although desired, according to the present invention, stable polishing with a sufficiently large speed ratio can be performed.

【0038】図6は、上記各実施例で使用されるα―ア
ルミナ(α―Al23 )(コランダム型)の結晶構造
を示している。図中、白丸は酸素原子であり、黒丸はア
ルミニウム原子である。
FIG. 6 shows the crystal structure of α-alumina (α-Al 2 O 3 ) (corundum type) used in each of the above embodiments. In the figure, open circles are oxygen atoms, and black circles are aluminum atoms.

【0039】アルミナの中ではα―アルミナが一番の硬
いので、このα―アルミナの量を少なくすることで基板
表面に発生する傷を少なくすることができる。また、γ
―アルミナが成長していきα―アルミナとなるので、α
―アルミナは粒径が大きく、α―アルミナの量を少なく
することで基板表面に大きな傷が入り難くなる。この結
果、α―アルミナの量を少なくすることで欠陥の発生を
抑制することができる。
Since α-alumina is the hardest of the aluminas, reducing the amount of α-alumina can reduce scratches generated on the substrate surface. Also, γ
-As alumina grows and becomes α-alumina, α
-Alumina has a large particle size, and by reducing the amount of α-alumina, large scratches are unlikely to be formed on the substrate surface. As a result, the occurrence of defects can be suppressed by reducing the amount of α-alumina.

【0040】なお、本発明は上述した実施例に限定され
るものではない。例えば、基板の材料としては、シリコ
ン、石英、サファイア、Al23 、III〜V族化合物
等を用いることができる。
The present invention is not limited to the embodiment described above. For example, as the material of the substrate may be a silicon, quartz, sapphire, Al 2 O 3, the III~V compound like.

【0041】研磨剤中の酸化剤としては、上記実施例の
硝酸第二鉄に限らず、他の酸化剤を用いた研磨にも応用
できる。また、被研磨膜としては、上記実施例では酸化
珪素膜およびタングステン膜を用いた場合について説明
したが、SiO2 、α−Si、ポリSi、SiON、S
iOF、BPSG(Boron-Phospho-Silicata Glass)、
PSG(Phospho-Silicata Glass)、SiN、Si3
4 、Si、Al、W、Ag、Cu、Ti、TiN、A
u、Pt、Ru、AlCu、AlSiCu等を主として
含む膜を用いることができる。また、研磨装置も上述し
た実施例に限定されない。
The oxidizing agent in the polishing agent is not limited to the ferric nitrate of the above embodiment, but can be applied to polishing using another oxidizing agent. In the above embodiment, the case where a silicon oxide film and a tungsten film are used as the film to be polished has been described. However, SiO 2 , α-Si, poly Si, SiON, S
iOF, BPSG (Boron-Phospho-Silicata Glass),
PSG (Phospho-Silicata Glass), SiN, Si 3 N
4 , Si, Al, W, Ag, Cu, Ti, TiN, A
A film mainly containing u, Pt, Ru, AlCu, AlSiCu, or the like can be used. Further, the polishing apparatus is not limited to the embodiment described above.

【0042】[0042]

【発明の効果】上述したように本発明によれば、研磨粒
子中に含まれるコランダム型結晶であるアルミナ含有量
を管理した研磨剤を使用することにより、半導体基板上
に発生する欠陥を低減し、且つ、生産性を損わない程度
の研磨速度を維持し、安定した研磨処理が可能になる半
導体装置の研磨方法および生産性を損なわない程度に研
磨速度を維持しつつ欠陥の発生を抑制し得る半導体装置
の製造方法を提供することができる。
As described above, according to the present invention, defects generated on a semiconductor substrate can be reduced by using an abrasive whose alumina content, which is a corundum type crystal contained in abrasive particles, is controlled. In addition, a polishing method for a semiconductor device capable of maintaining a polishing rate that does not impair productivity and performing a stable polishing process, and suppressing occurrence of defects while maintaining the polishing rate so as not to impair productivity. It is possible to provide a method for manufacturing a semiconductor device to be obtained.

【0043】即ち、請求項1記載の研磨方法では、半導
体基板の研磨工程において使用される研磨粒子を含む研
磨剤として、研磨粒子中に含まれるコランダム型結晶で
あるアルミナが4%以上16%以下であるものを用いる
ことを特徴とする。
That is, in the polishing method according to the first aspect, the abrasive containing the abrasive particles used in the polishing step of the semiconductor substrate contains 4% to 16% of alumina, which is a corundum type crystal, contained in the abrasive particles. Is used.

【0044】このように研磨粒子中に含まれるコランダ
ム型結晶であるアルミナ含有量を管理した研磨剤を使用
することにより、安定した研磨処理が可能になる。請求
項2記載の研磨方法では、研磨定盤上に研磨面を設け、
この研磨面と対向した位置に設けられた保持部に被研磨
面を有する被研磨物を保持する工程と、前記研磨面の上
に研磨粒子を含む研磨剤を供給し、前記保持部と前記研
磨定盤との間に圧力をかけて前記研磨面と前記被研磨面
とを摺動させることにより前記被研磨物を研磨する工程
とを具備し、前記研磨粒子中に含まれるコランダム型結
晶であるアルミナが4%以上16%以下である前記研磨
剤を使用することを特徴とする。
By using the abrasive whose content of alumina, which is a corundum type crystal contained in the abrasive particles, is controlled in this manner, a stable polishing treatment can be performed. In the polishing method according to claim 2, a polishing surface is provided on a polishing platen,
A step of holding an object to be polished having a surface to be polished on a holding portion provided at a position facing the polishing surface, and supplying an abrasive containing abrasive particles onto the polishing surface, Polishing the object to be polished by applying pressure between the platen and sliding the surface to be polished and the surface to be polished, the corundum crystal contained in the abrasive particles. It is characterized by using the above-mentioned abrasive whose alumina is 4% or more and 16% or less.

【0045】このように研磨粒子中に含まれるコランダ
ム型結晶であるアルミナ含有量を管理した研磨剤を使用
することにより、安定した研磨処理が可能になる。請求
項4記載の製造方法では、半導体基板上に被研磨膜を形
成する工程と、前記被研磨膜の少なくとも一部を、研磨
粒子中に含まれるコランダム型結晶であるアルミナが4
%以上16%以下である研磨剤により研磨する工程とを
具備することを特徴とする。
By using an abrasive whose content of alumina, which is a corundum type crystal contained in the abrasive particles, is controlled in this manner, a stable polishing treatment can be performed. In the manufacturing method according to the fourth aspect, a step of forming a film to be polished on the semiconductor substrate, and at least a part of the film to be polished is made of a corundum type crystal alumina contained in abrasive particles of 4%.
% By polishing with an abrasive of not less than 16% and not more than 16%.

【0046】このように研磨粒子中に含まれるコランダ
ム型結晶であるアルミナ含有量を管理した研磨剤を使用
することにより、生産性を損なわない程度に研磨速度を
維持しつつ欠陥の発生を抑制し得る半導体装置を製造す
ることが可能になる。
As described above, by using the abrasive whose alumina content, which is a corundum type crystal contained in the abrasive particles, is controlled, the generation of defects can be suppressed while maintaining the polishing rate to such an extent that productivity is not impaired. The resulting semiconductor device can be manufactured.

【0047】請求項5記載の製造方法では、表面に凹凸
を有する半導体基板に被研磨膜を形成する工程と、前記
被研磨膜を研磨粒子中に含まれるコランダム型結晶であ
るアルミナが4%以上16%以下である研磨剤により研
磨して平坦化する工程とを具備することを特徴とする。
In the manufacturing method according to the fifth aspect, the step of forming a film to be polished on the semiconductor substrate having irregularities on the surface, and the step of forming the film to be polished by using at least 4% of alumina, which is a corundum type crystal contained in the polishing particles. Polishing with an abrasive that is 16% or less for flattening.

【0048】このように研磨粒子中に含まれるコランダ
ム型結晶であるアルミナ含有量を管理した研磨剤を使用
することにより、生産性を損なわない程度に研磨速度を
維持しつつ欠陥の発生を抑制し得る半導体装置を製造す
ることが可能になる。
As described above, the use of the abrasive whose alumina content, which is a corundum type crystal contained in the abrasive particles, is controlled allows the generation of defects to be suppressed while maintaining the polishing rate to such an extent that productivity is not impaired. The resulting semiconductor device can be manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の研磨方法の第1実施例で
使用された二種類の被研磨膜を示す断面図。
FIG. 1 is a sectional view showing two types of films to be polished used in a first embodiment of a method for polishing a semiconductor device according to the present invention.

【図2】本発明の半導体装置の研磨方法の第1実施例で
使用された研磨装置を概略的に示す構成説明図。
FIG. 2 is a configuration explanatory view schematically showing a polishing apparatus used in a first embodiment of a method of polishing a semiconductor device according to the present invention.

【図3】本発明の半導体装置の研磨方法の第1実施例で
係わる研磨粒子中に含まれるコランダム型結晶であるア
ルミナ( α−アルミナ) の含有量に対する基板上の欠陥
数、被研磨膜の研磨速度との関係を示す図。
FIG. 3 shows the number of defects on a substrate with respect to the content of alumina (α-alumina), which is a corundum type crystal, contained in polishing particles according to the first embodiment of the method for polishing a semiconductor device of the present invention, The figure which shows the relationship with a polishing rate.

【図4】本発明の半導体装置の製造方法の第1実施例で
使用された被研磨膜を示す断面図。
FIG. 4 is a sectional view showing a film to be polished used in the first embodiment of the method of manufacturing a semiconductor device according to the present invention.

【図5】本発明の半導体装置の製造方法の第1実施例お
よび従来例の製造方法における研磨剤ロットと製品欠陥
数との関係を対比して示す図。
FIG. 5 is a diagram showing a comparison between the relationship between the abrasive lot and the number of product defects in the first embodiment of the semiconductor device manufacturing method of the present invention and the conventional manufacturing method.

【図6】本発明の各実施例で使用されるα―アルミナの
結晶構造を示す図。
FIG. 6 is a view showing a crystal structure of α-alumina used in each example of the present invention.

【図7】CMP技術を用いた埋め込み金属配線形成工程
を示す断面図および斜視図。
7A and 7B are a cross-sectional view and a perspective view showing a buried metal wiring forming step using the CMP technique.

【図8】従来の半導体装置の研磨方法を用いた製造方法
における製品不良の一例を説明するために示す断面図。
FIG. 8 is a cross-sectional view illustrating an example of a product defect in a manufacturing method using a conventional semiconductor device polishing method.

【図9】従来の半導体装置の研磨方法で用いた研磨剤の
ロットと製品不良(欠陥数)との関係を示す図。
FIG. 9 is a diagram showing a relationship between a lot of abrasive used in a conventional method of polishing a semiconductor device and a product defect (the number of defects).

【符号の説明】[Explanation of symbols]

50…被研磨膜、 51…研磨定盤、 52…研磨布、 53…真空チャックホルダ、 54…プレート、 55…研磨剤供給用配管。 50: film to be polished, 51: polishing platen, 52: polishing cloth, 53: vacuum chuck holder, 54: plate, 55: piping for supplying abrasive.

フロントページの続き (72)発明者 加藤 信広 三重県四日市市山之一色町800番地 株式 会社東芝四日市工場内 (72)発明者 柏原 洋史 三重県四日市市山之一色町800番地 株式 会社東芝四日市工場内Continued on the front page (72) Inventor Nobuhiro Kato 800 Yamano Isshiki-cho, Yokkaichi-shi, Mie Prefecture Inside the Toshiba Yokkaichi Plant Co., Ltd.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の研磨工程に使用される研磨
粒子を含む研磨剤として、前記研磨粒子中に含まれるコ
ランダム型結晶であるアルミナが4%以上16%以下で
あるように管理されたものを用いることを特徴とする半
導体基板の研磨方法。
1. A polishing agent containing abrasive particles used in a polishing step of a semiconductor substrate, which is controlled so that alumina which is a corundum type crystal contained in the abrasive particles is 4% or more and 16% or less. A method for polishing a semiconductor substrate, characterized by using:
【請求項2】 研磨定盤上に研磨面を設け、この研磨面
と対向した位置に設けられた保持部に被研磨面を有する
被研磨物を保持する工程と、 前記研磨面の上に研磨粒子を含む研磨剤を供給し、前記
保持部と前記研磨定盤との間に圧力をかけて前記研磨面
と前記被研磨面とを摺動させることにより前記被研磨物
を研磨する工程とを具備し、 前記研磨剤として、前記研磨粒子中に含まれるコランダ
ム型結晶であるアルミナが4%以上16%以下であるよ
うに管理されたものを用いることを特徴とする半導体基
板の研磨方法。
2. A step of providing a polishing surface on a polishing platen, and holding an object to be polished having a surface to be polished on a holding portion provided at a position facing the polishing surface; Supplying an abrasive containing particles, and polishing the workpiece by applying pressure between the holding portion and the polishing platen to slide the polishing surface and the surface to be polished. A method for polishing a semiconductor substrate, comprising using, as the polishing agent, one controlled so that alumina, which is a corundum crystal contained in the polishing particles, is at least 4% and at most 16%.
【請求項3】 請求項1または2記載の半導体基板の研
磨方法において、 前記研磨剤中の前記研磨粒子はアルミナを主成分とする
ことを特徴とする半導体基板の研磨方法。
3. The method for polishing a semiconductor substrate according to claim 1, wherein the polishing particles in the polishing slurry contain alumina as a main component.
【請求項4】 半導体基板上に被研磨膜を形成する工程
と、 前記被研磨膜の少なくとも一部を、研磨粒子中に含まれ
るコランダム型結晶であるアルミナが4%以上16%以
下であるように管理された研磨剤により研磨する工程と
を具備することを特徴とする半導体装置の製造方法。
4. A step of forming a film to be polished on a semiconductor substrate, wherein at least a part of the film to be polished contains 4% to 16% of alumina which is a corundum type crystal contained in abrasive particles. Polishing with a polishing agent controlled in accordance with the above method.
【請求項5】 表面に凹凸を有する半導体基板に被研磨
膜を形成する工程と、 前記被研磨膜を、研磨粒子中に含まれるコランダム型結
晶であるアルミナが4%以上16%以下であるように管
理された研磨剤により研磨して平坦化する工程とを具備
することを特徴とする半導体装置の製造方法。
5. A step of forming a film to be polished on a semiconductor substrate having irregularities on the surface, wherein the film to be polished is such that alumina, which is a corundum type crystal contained in abrasive particles, is 4% or more and 16% or less. Polishing by a polishing agent controlled in step (1) and flattening.
【請求項6】 請求項5記載の半導体装置の製造方法に
おいて、 前記被研磨膜は金属積層膜および珪素含有膜であること
を特徴とする半導体装置の製造方法。
6. The method of manufacturing a semiconductor device according to claim 5, wherein the film to be polished is a metal laminated film and a silicon-containing film.
【請求項7】 請求項4乃至6のいずれか1項に記載の
半導体装置の製造方法において、 前記研磨剤中の前記研磨粒子はアルミナを主成分とする
ことを特徴とする半導体装置の製造方法。
7. The method of manufacturing a semiconductor device according to claim 4, wherein said abrasive particles in said abrasive mainly comprise alumina. .
JP10200581A 1998-07-15 1998-07-15 Method for abrasion of semiconductor substrate and preparation of semiconductor equipment Pending JP2000026841A (en)

Priority Applications (2)

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KR1019990028520A KR20000011718A (en) 1998-07-15 1999-07-14 A method of polishing semiconductor substrate and a method of making semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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KR (1) KR20000011718A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005205542A (en) * 2004-01-22 2005-08-04 Noritake Co Ltd Sapphire polishing grinding wheel and sapphire polishing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100525076B1 (en) * 2002-12-10 2005-11-02 매그나칩 반도체 유한회사 slurry for chemical mechanical polishing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005205542A (en) * 2004-01-22 2005-08-04 Noritake Co Ltd Sapphire polishing grinding wheel and sapphire polishing method

Also Published As

Publication number Publication date
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