JP2000022499A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a capacity required for a waveform memory by applying an address generated by an address generator to the waveform memory and outputting the filtered result corresponding to an input data stream from a digital/analog(D/A) converter. SOLUTION: The 32-bit data of input data are converted into parallel data by a serial/parallel(S/P) converter 11a. The respective converted data of preceding 16 bits and following 16 bits become high-order addresses corresponding to waveform memories 21b and 21a. As low-order addresses, both the 2-bit outputs of a counter 12a are applied. The previously found filtered result is written in the waveform memories 21b and 21a. Every time the input data are converted by the S/P converter 11a, the counter 12a counts four clocks and values 0 to 3 are outputted. The outputs of the waveform memories 21a and 21b are added by an adder, the least significant bit is cut and the most significant bit is applied to a D/A converter 30 as a carry output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter used for band limitation in a communication baseband signal generator, and more particularly to an improvement for reducing the scale of hardware.

[0002]

2. Description of the Related Art A communication baseband generator is positioned as a communication reference signal generator, and high-purity waveform generation is required. In wireless communication, usable frequencies are particularly tight, and it is necessary to reduce the occupied frequency bandwidth of signals as much as possible. Filters are used to reduce the frequency bandwidth occupied by signals within a range where there is no problem in information transmission, but digital filters are difficult to achieve with analog filters for strict requirements for attenuation and flatness within the band. Is used.

Further, in order to use a communication baseband generator as a general-purpose reference signal generator, it is necessary for the digital filter to be able to faithfully reproduce a filter shape defined by various standards. In addition, the filter constant needs to be variable in order to be able to cope with a new standard that will occur in the future. For this reason, digital filters used in communication baseband signal generators are required to have particularly high accuracy and variability in filter shape.

Conventionally, a digital processor has used a digital processor (DSP) that performs a product-sum operation in real time in order to obtain a highly accurate filter result. However, the processing speed of the DSP has reached its limit in order to cope with the increasing data communication.

The applicant of the present invention solves this problem by using a digital filter as disclosed in Japanese Patent Application No. 9-231909.
Has been proposed. This "digital filter" is shown in FIG.
As shown in FIG. 2, an address generator 10 for generating an address based on an input data sequence, and a waveform memory 2 in which filter processing results corresponding to the data sequence are stored in advance.
0 and a digital-to-analog converter (DA converter) 30 for converting the output of the waveform memory 20 into an analog signal.

The address generator 10 comprises a serial-to-parallel converter 11, a counter 12 and a frequency divider 13. The serial-input data is converted into parallel data by the serial-to-parallel converter 11, and the upper address of the waveform memory 20 is stored. Give as. On the other hand, the counter 12 for counting the reference clock is used for oversampling (here, 8 oversampling), and its 3-bit output is given to the waveform memory 20 as a lower address.

The frequency divider 13 divides the reference clock (in this case, １ ／ frequency division), and supplies this to the serial / parallel converter 11 as a timing clock.

The waveform memory 20 stores data obtained as follows. That is, an input data sequence (here, 15 bits) is generated by a computer or the like (not shown), and this is oversampled by eight. The root data is
Convolution operation of Nyquist filter and window function,
The data obtained by this calculation (here, data in the case of 8 oversampling and a symbol interference length of 15) is stored in the waveform memory 20.

The same processing is performed for the other input data, and the result of the filter processing is stored in the waveform memory 20. As a result, eight data can be sequentially output from the waveform memory 20 for certain input data.

According to such a configuration, a filtering result corresponding to the input data sequence is read out from the waveform memory 20. Therefore, the processing speed is much higher than that of a conventional digital filter that performs a convolution operation in real time.

[0011]

By the way, in the above-mentioned digital filter, a high-precision operation result can be obtained at high speed, but when the symbol interference length becomes large, a necessary waveform memory (usually RAM is used) 20 is required. Capacity doubles. When a very high-precision filter (symbol interference length is about 32) is realized, for example, when 4 oversamples (the output of the counter 12 is 2 bits and the frequency division by the frequency divider 13 is 1/4), There has been a problem that a memory having a large capacity of 2 ³² words oversampling, that is, 16 G words (however, data required for one output point is one word) is required.

The present invention solves the above problems,
It is an object of the present invention to realize a digital filter capable of reducing the capacity required for a waveform memory by dividing the operation process into a process to be performed in advance and a process to be performed at the time of execution by focusing on the linearity of the convolution operation process.

[0013]

According to a first aspect of the present invention, there is provided a digital filter which divides an input data sequence and generates an address based on each data. A plurality of waveform memories in which filter processing results corresponding to the respective divided data strings are stored in advance, an adder for adding the outputs of the plurality of waveform memories, and a digital / analog conversion for converting the output of the adder into an analog signal And an address generated by the address generator is given to the waveform memory, so that a filter result corresponding to the input data sequence is output from the digital-to-analog converter.

According to such a configuration, focusing on the linearity of the convolution operation processing used in the digital filter processing, the filter processing result corresponding to each data string obtained by dividing the input data string is previously stored in each waveform memory. It is stored, and at the time of execution, a filter processing result corresponding to the input data sequence can be obtained only by adding the output from the waveform memory. Therefore, the capacity of the waveform memory is much smaller than that of the related art, and a digital filter having a long symbol interference length can be easily realized.

Further, the digital filter according to claim 4 is
A serial / parallel converter that outputs the preceding one bit of the input data string, converts the remaining bits into parallel data, and outputs it as an address, a counter that counts a reference clock, and a serial / parallel converter that divides the reference clock to divide the serial clock. A frequency divider used as a timing clock for the parallel converter, a first data inverting circuit for inverting and outputting the remaining bit data according to the preceding 1-bit data, and half of all combinations of the data sequence And a second memory for inverting the output of the waveform memory in accordance with the preceding 1-bit data.
A data inverting circuit, and a digital-to-analog converter for converting the output of the second data inverting circuit into an analog signal, wherein the output of the first data inverting circuit is an upper bit and the output of the counter is an lower bit. Is supplied to the waveform memory, and a filter processing result corresponding to the input data string is obtained from the digital-to-analog converter.

According to such a configuration, it is only necessary to store in advance the filter processing result for the data of the remaining bits other than the preceding one bit of the input data string in the waveform memory, and the capacity of the waveform memory is reduced. Can be reduced by half.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of a digital filter according to the present invention. According to the present invention, an address generator 10a, a waveform memory unit 20a, a DA converter 3
It is composed of 0.

The address generator 10a comprises a serial / parallel converter 11a of 32 stages, a counter 12a for counting a reference clock and outputting it with 2 bits, and a quarter frequency divider 13a for dividing the clock by 1/4. I have. The serial / parallel converter 11a separates and outputs the preceding 16-bit and succeeding 16-bit parallel data of the 32-bit input data string.

The waveform memory section 20a is divided into first and second waveform memories 21a and 21b, and each of the waveform memories stores a filter processing result corresponding to a data string (which is an address of a waveform memory access). Is stored. To the first waveform memory 21a, a value obtained by adding the subsequent 16-bit data of the serial / parallel converter 11a and the 2-bit data of the counter 12 is given as an address.
The sum of the preceding 16-bit data of the serial / parallel converter 11a and the 2-bit data of the counter 12 is given as an address to the waveform memory 21b. In this embodiment, 256K words are sufficient for each waveform memory.

The adder 22 is a 16-bit full adder in this case, and includes first and second waveform memories 21a and 21a.
The output of each 16 bits of 1b is added. The output is input to the DA converter 30, but the lower one bit is discarded and the most significant bit is used as a carry output.

The data stored in the divided waveform memory is as follows. Now, the input data sequence is x (n), the output data sequence is y (n), and the impulse response sequence of the filter is h (n).
Then

(Equation 1) It is expressed as

The above equation (1) is divided as follows using linearity. y (n) = y ₁ (n) + y ₂ (n)

(Equation 2)

Therefore, y ₁ (−2), y ₁ (−1), y ₁
The four words (0), y ₁ (1) are written to the first waveform memory 21a for all combinations of x (n),
On the other hand, y ₂ (−2), y ₂ (−1), y ₂ (0), y
₂ Write the four words (1) into the second waveform memory 2b for all combinations of x (n). Note that x
(N) assumes binary data, and the combination of x (n) is 2 to the (symbol interference length / 2) power.

As described above, in the present invention, y1 (n), y2
(N) is calculated in advance and the waveform memories 21a and 21b are calculated.
Respectively. At the time of executing the filter processing, the adder 22 calculates y ₁ (n) + y ₂ (n).

The operation in such a configuration will be described below. The 32-bit data of the serial input data is converted into parallel data by the serial / parallel converter 11a. At this time,
Each of the preceding 16 bits and the succeeding 16 bits of converted data is an upper address for the waveform memories 21b and 21a. As the lower address, a 2-bit output of the counter 12a (because of 4 oversampling) is given together.

The filter processing results obtained as described above are written in the waveform memories 21b and 21a. Each time the serial / parallel converter 11a converts the input data,
The counter 12a counts four clocks and outputs values of 0 to 3. While the lower address given to the waveform memory changes from 0 to 3, the output of the serial / parallel converter 11a, which is the upper address, does not change.

Therefore, y ₁ is obtained from the waveform memory 21a.
(−2), y ₁ (−1), y ₁ (0), y ₁ (1) are sequentially output, and at the same time, y ₂ (−) is output from the waveform memory 21b.
2), y ₂ (−1), y ₂ (0), y ₂ (1) are sequentially output. The two outputs are added by the adder 22, the least significant bit is discarded, and the most significant bit is supplied to the DA converter 30 as a carry output, converted into an analog signal and output from the output terminal.

The present invention is not limited to the embodiment. For example, the waveform memory is not limited to two divisions, but can be divided into more divisions. Further, the number of oversampling is not limited to four.

According to the above-described configuration, the waveform memory can be greatly reduced (16 G words → 256 K words × 2), and a digital filter having a very long symbol interference length (about 32) can be obtained. It can be easily realized. If the digital filter has a symbol interference length of about 16, 1K at 4 oversampling
Only a memory capacity of words × 2 is required, and it can be incorporated into the communication device IC.

Next, the second invention will be described. Now, in the conventional digital filter shown in FIG. 5, as shown in FIG. 6, the serial-to-parallel converter is a serial-to-parallel converter 11b having 16 stages, and has a 16-bit output.
It is assumed that a is 1/4 frequency division, the counter 12a is a 2-bit counter, the symbol interference length is 16, the oversampling number is 4, and the resolution of the DA converter 30 is 16 bits.

According to such a configuration, the waveform memory 20b
Requires a capacity of 256K words. When the symbol interference length is increased, the required capacity of the waveform memory is doubled, resulting in a problem that the capacity is increased.

Here, paying attention to the symmetry of the output data string of the digital filter processing in the voltage direction, and adopting a method of storing only data on one side in the waveform memory,
The required amount of waveform memory is reduced by half. The details will be described below with reference to FIGS.

In FIG. 2, a waveform memory section 20c includes a first data inversion circuit 23 for inverting and outputting the output of the serial / parallel converter 11b, and a first data inversion circuit 23.
And the 16-bit data from the waveform memory 21c are inverted with respect to the preceding 1-bit data output from the serial / parallel converter 11b. And a second data inverting circuit 24.

The data stored in advance in the waveform memory 21c is as follows. Now, let the input data string be x
(N), the output data sequence is y (n), and the impulse response sequence of the filter is h (n).

(Equation 3) It is expressed as

Here, y (-2), y (-1), y
The combination of (0) and y (1) is only x (n), and when the symbol interference length is 16, x
(N) is a set of 16 sets each having 4 sets of 0s or 1s, which is a combination of 2 to the 16th power.

Here, all combinations of x (n) are divided into halves based on the data of x (31).

The waveform memory 2 is calculated in advance for 2 15 power combinations where x (31) is 0.
1c. Normally, since the input data 0 and 1 are assigned to binary values symmetrical in the voltage direction, the following equation is established.

(Equation 4)

When x (31) is 1, the memory data obtained by inverting the logic of the remaining 15 data using the above equation is read, and the data is used after being inverted in the voltage direction.

FIG. 3 shows the structure of the first data inverting circuit 23. The 15 exclusive OR gates (XOR gates) are commonly provided from the preceding 1-bit output from the serial / parallel converter 11b, and the remaining 15-bit outputs are input to the respective XOR gates. Only when the preceding 1-bit data is 1, the remaining 15-bit data is inverted and output. The output of this XOR gate becomes the upper address for the waveform memory 21c.

FIG. 4 shows the structure of the second data inverting circuit 24. This circuit comprises 16 XOR gates. The preceding 1-bit output from the serial / parallel converter 11b is commonly input, and the 16-bit output from the waveform memory 21c is input to each gate. The bit output is input to the DA converter 30. Only when the preceding 1-bit output is 1, the output of the 16-bit DA converter 30 is inverted and output.

According to such a configuration, only the data on one side needs to be stored in the waveform memory 21c due to the symmetry in the voltage direction of the output data sequence of the digital filter processing, and the required capacity of the waveform memory 21c is reduced. It can be reduced to half of the conventional one.

It should be noted that the foregoing description has been directed to specific preferred embodiments for the purpose of illustration and illustration of the invention. Therefore, the present invention is not limited to the above-described embodiment, and includes many more modifications without departing from the spirit thereof.
This includes deformation.

For example, the number of oversamplings and the symbol interference length are not limited to those in the embodiment, but can be set to arbitrary values.

[0044]

As described above, according to the first aspect of the present invention, the number of waveform memories can be greatly reduced. For example, in the case of a 32-bit serial input, 8 oversampling, and a symbol interference length of 32, the conventional filter shown in FIG. 5 requires 16 G words, but the present invention requires only 256 K words × 2.

From the above effects, it can be seen that a filter having a very long symbol interference length can be easily realized with a small waveform memory. Also, if the filter has a symbol interference length of about 16, only a waveform memory of 1K words × 2 is required at the time of 4 oversampling.
It can also be incorporated in the inside, and the effect is large in practical use.

According to the fifth aspect of the present invention, only the data on one side needs to be stored in the waveform memory 21c because of the symmetry in the voltage direction of the output data sequence of the digital filter processing, so that the output is relatively simple. With a simple circuit, the required capacity of the waveform memory can be reduced to half of the conventional one.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a digital filter according to the present invention.

FIG. 2 is a configuration diagram showing another embodiment of the digital filter according to the present invention.

FIG. 3 is a configuration diagram of a first data inversion circuit.

FIG. 4 is a configuration diagram of a second data inversion circuit.

FIG. 5 is a configuration diagram illustrating an example of a conventional digital filter.

FIG. 6 is a configuration diagram showing another example of a conventional digital filter.

[Explanation of symbols]

 10a Address generator 11a, 11b Serial / parallel converter 12a Counter 13a Frequency divider 20a, 20c Waveform memory unit 21a First waveform memory 21b Second waveform memory 21c Waveform memory 22 Adder 23 First data inversion circuit 24 First 2 data inverting circuit 30 DA converter

Claims (5)

[Claims] An address generator that divides an input data sequence and generates an address based on each data; a plurality of waveform memories in which filter processing results corresponding to each of the divided data sequences are stored in advance; An adder for adding the outputs of the plurality of waveform memories; and a digital-to-analog converter for converting the outputs of the adders into analog signals. A digital filter configured to output a filter result corresponding to the digital filter from the digital / analog converter. 2. An address generator comprising: a serial / parallel converter for converting a divided input data sequence into parallel data; a counter for counting a reference clock; and a serial / parallel converter for dividing the reference clock. A frequency divider which is used as a timing clock of the device, wherein each output of the serial / parallel converter is provided to the plurality of waveform memories as an upper bit of an address and an output of the counter is provided as a lower bit of an address. The digital filter according to claim 1, wherein: 3. The digital filter according to claim 2, wherein said frequency divider is configured to divide a clock by １ ／, and said input data sequence is oversampled by four. 4. A serial / parallel converter for outputting the preceding one bit of an input data string, converting the remaining bits into parallel data and outputting it as an address, a counter for counting a reference clock, and a counter for dividing the reference clock. A frequency divider that is a timing clock of the serial / parallel converter; a first data inverting circuit that inverts and outputs the remaining bit data according to the preceding 1-bit data; A waveform memory in which filter processing results for half of all combinations are stored in advance, a second data inverting circuit for inverting an output of the waveform memory according to the preceding 1-bit data, and a second data inverting circuit. A digital-to-analog converter for converting the output of the circuit from analog to analog. It gives an address to the output of the data and the lower bits in said waveform memory, a digital filter, wherein the input data filtering result corresponding to the column was configured as obtained from the digital-to-analog converter. 5. The digital frequency divider according to claim 4, wherein said frequency divider is configured to divide said reference clock by 、, and said input data sequence is oversampled by four. filter.