CN114675815A - Method for realizing automatic generation of CIC filter code based on python - Google Patents

Method for realizing automatic generation of CIC filter code based on python Download PDF

Info

Publication number
CN114675815A
CN114675815A CN202210394707.XA CN202210394707A CN114675815A CN 114675815 A CN114675815 A CN 114675815A CN 202210394707 A CN202210394707 A CN 202210394707A CN 114675815 A CN114675815 A CN 114675815A
Authority
CN
China
Prior art keywords
module
rtl
path
function
bit width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210394707.XA
Other languages
Chinese (zh)
Inventor
万书芹
高敏
邵杰
卓琳
蒋颖丹
王祖锦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 58 Research Institute
Original Assignee
CETC 58 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 58 Research Institute filed Critical CETC 58 Research Institute
Priority to CN202210394707.XA priority Critical patent/CN114675815A/en
Publication of CN114675815A publication Critical patent/CN114675815A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/31—Programming languages or programming paradigms
    • G06F8/315—Object-oriented languages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0671—Cascaded integrator-comb [CIC] filters

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a method for realizing automatic generation of CIC filter codes based on python, and belongs to the field of digital down conversion. Establishing a graphical interface by using a script written by a python language, initializing each index information list of the CIC filter, and inputting corresponding each index information of the CIC in a popup window according to the content of a label; automatically generating RTL codes of all sub-modules, instantiated RTL codes of modules and RTL codes of a top module through the acquired index information; the resulting result is checked for problems. The script written by the python language can correctly receive graphical interface information, automatically generate RTL codes of all sub-modules of the CIC filter according to information parameters, perform modular instantiation processing on repeated sub-modules, and generate top-level files capable of being correctly connected. The invention uses simple and understandable python language to compile the RTL code automatic generation script of the CIC filter, and the parameter information of the CIC filter can be changed by modifying the graphic interface dialog box, thereby greatly reducing the workload and improving the working efficiency.

Description

Method for realizing automatic generation of CIC filter code based on python
Technical Field
The invention relates to the technical field of digital down conversion, in particular to a method for automatically generating CIC filter codes based on python.
Background
In the digital down-conversion technology, a signal is mixed with a carrier signal generated by an oscillator, and the center frequency spectrum of the mixed signal is shifted to a low frequency. Then, a decimation filter is used for filtering out the high-frequency signals, and finally, low-speed baseband data is output, so that the decimation filter is crucial to a digital down-conversion circuit.
The CIC filter has the characteristics of no multiplier, no coefficient memory, less occupied resources, simplicity in implementation, high speed and the like, so that the CIC filter is suitable for a digital down-conversion circuit with a high sampling rate in a software radio communication system. In the prior art, a multi-stage cascaded CIC decimation filter is adopted, as shown in fig. 1, and includes an integration unit, a decimation unit and a comb unit. Due to the overflow problem of the integral unit, the data bit width of the whole system is all represented by the formula Bmax＝Nlog2 DM+BinAnd the calculated maximum bit width not only increases the use amount of hardware, but also greatly increases the power loss. In addition, for the extractor with a fixed extraction ratio, the extractor cannot adapt to different extraction environments, the output bandwidth is single, the hardware consumption of a next-stage module is increased, and the power consumption of the whole system is increased. Therefore, in order to adapt to different signal bandwidths and reduce power consumption and design area, the CIC decimation filter based on the nibble serial algorithm, which can dynamically realize any integer multiple decimation function, is very important.
The principle of adopting a half-byte serial algorithm is that an input signal is sequentially split into signals with the same multi-bit word length from MSB to LSB for serial output, and output data are serially crossed or multiplexed in a high-speed channel. The half byte serial algorithm is to divide the input signal into signals with the same 4-bit width for serial output, and reduces the operation logic and storage logic units by the multiplexing technology, thereby reducing the cost and improving the use efficiency of system resources.
At present, the required RTL codes of the CIC decimation filter are all completed in a manual mode, namely, the codes are manually knocked, so that heavy workload is brought, project schedule is greatly influenced, and code errors can occur, which are defects in the prior art.
Disclosure of Invention
The invention aims to provide a method for automatically generating a CIC filter code based on python, which is used for solving the problems of insufficient manually designed codes, high error rate and low working efficiency.
In order to solve the technical problem, the invention provides a method for realizing automatic generation of CIC filter codes based on python, which comprises the following steps:
running a python script, inputting corresponding parameter information in a popped graphical window according to a prompt, and storing the collected parameter information through a list;
processing the parameter information in the list, and automatically generating RTL codes of all sub-modules, instantiated RTL codes of modules and RTL codes of a top module;
and checking whether the generated checking result has a problem.
Optionally, the python script generates the graphical window by introducing a tkater library, and indicates parameter information including an input bit width, a decimation multiple, a delay factor, a cascade number, and an output bit width, which is input to the CIC filter, according to the window.
Optionally, the python script automatically generates each sub-module RTL code, module instantiation RTL code, and top-level module RTL code in the CIC filter according to verilog syntax specification.
Optionally, the python script is divided into six functions:
a first function generates a graphical interface;
the second function completes the definition of interface bit width;
the third function automatically generates RTL codes of port definition, I/O description and internal signal description parts according to verilog syntax specification;
the fourth function automatically generates RTL codes of different frequency division clocks according to verilog syntax specification;
automatically generating a modular instantiated RTL code by a fifth function according to verilog syntax specification;
and the sixth function completes the scheduling management of each function and automatically generates the RTL code fixed by each module in the CIC filter.
Optionally, the first function generates a graphical window by introducing a tkater library; the input port bit width B of the corresponding CIC filter is input according to the label Lable indication in the windowinDecimation factor D, delay factor M, cascade number N and output bit width BoutAnd information is acquired by using a get () function and stored in the list index.
Optionally, the second function utilizes formula Bmax＝Nlog2 DM+BinAnd Bmin＝BmaxAnd 4, calculating to obtain the maximum bit width B of the port of the whole CIC filtermaxAnd minimum bit width BminStoring the data into a list, wherein N is the number of cascade, D is the extraction multiple, and BinIs the input port bit width; if the maximum bit width is not an integer multiple of 4, the calculated value maximum bit width is expanded to be closest to an integer multiple of 4 of the value.
Optionally, the third function automatically generates an RTL code of the port portion according to verilog syntax specification, and first, each module starts with a keyword module, defines a port name, and puts an I/O description into a port list; the signal with the input/output and internal signal bit width of 1 is positioned in a list, the signal with the bit width larger than 1 is positioned in a dictionary embedded in the list, the name indexes of signal variables are respectively bus _ name, bus _ max and bus _ min, and the values are respectively the maximum value and the minimum value of the signal name and the signal bit width; the internal reg and wire type signal definition is completed, the maximum value and the minimum value of the signal character and the signal bit width are obtained through a built-in function len (max), and the RTL code writing format is adjusted according to the maximum length.
Optionally, the fourth function obtains different frequency division multiples through operation according to the obtained decimation multiple D, stores the frequency division multiples by using a list, and generates a corresponding counter by using the frequency division multiples as a count value; generating a value or an interval of a clock turning point when the counter counts according to the clock requirement, and registering by using a list; generating low-frequency clocks with different duty ratios and different frequency division multiples through a counter; the frequency division clock module generates signals comprising: an enable signal en _ itg required by the integrator module, a sampling clock clk _ decimate required by the decimator module, a sampling clock clk _ comb and an enable signal en _ comb required by the comb filter, and a sampling clock clk _ parallel _ serial required by the serial-parallel conversion module; wherein: en _ itg is a 4 division of clk, clk _ comb is a D division of clk, clk _ decimate, en _ comb, and clk _ parallel _ to _ serial are all a 4 x D division of clk, and the duty cycle and phase are the same.
Optionally, the fifth function extracts the required module interface information, generates a module instantiation RTL code, separates the characters in the extracted file into a character string list according to rows, assigns a variable to the character string list, precompiles a regular expression containing the interface information, searches the regular expression in each row by using a for loop, if the regular expression is found, proceeds to the next step, searches the regular expression in each row by using a for loop, separates the searched character strings into individual character strings according to spaces or commas, extracts the interface information according to the subscript, and completes the module instantiation by defining the module name and the link signal.
Optionally, the sixth function defines, according to a standard verilog syntax, the expressions of a basic module name, a port list, an input/output port, and an internal signal in the CIC filter, and a fixed logical function description and an end symbol, and simultaneously completes the scheduling of the first function, the second function, the third function, the fourth function, and the fifth function, and finally completes the generation of the RTL code of each module, the module instantiation, and the top module in the CIC filter; the method comprises the following steps:
calling a first function to generate a graphical interface;
calling a second function to obtain the maximum bit width and the minimum bit width of the signal bus;
obtaining a path of a current python script by using an os.getcwd () function, obtaining a directory of the current script by using an os.path.diameter () function, creating a new rtl folder below the directory, and storing the directory path by using a variable path _ rtl;
defining module names, including: the device comprises a clock generation module, a coding module, an integrator module comprising one output port, an integrator module comprising four output ports, an extractor module, a comb filter module, a cascade integrator module, a cascade comb filter module and a top module; the specific path of the RTL code file of each module in the path _ RTL directory is the 11 variables of path _ RTL symbol variable plus each module name plus symbol ". v", and is stored into path _ RTL _ clk _ gen, path _ RTL _ code, path _ RTL _ itg _ one, path _ RTL _ itg _ four, path _ RTL _ deletion, path _ RTL _ comb, path _ RTL _ parallel _ to _ serial, path _ RTL _ cascade _ integrators, path _ RTL _ cascade _ bs, and path _ RTL _ top _ cic, respectively;
information defining a clock generation module, comprising: the method comprises the steps that a module name, input and output signals and internal signals are called, a third function and a fourth function are called to automatically generate RTL codes of a port part under a path _ RTL _ clk _ gen, and simultaneously, RTL codes of a logic function part are automatically generated under the path according to standard verilog syntax, wherein the logic function is that a sampling frequency division clock required by each module is generated through a counter;
information defining an encoding module, comprising: calling a third function to automatically generate an RTL code of a port part under a path by using a module name, input and output signals and internal signals, and simultaneously automatically generating the RTL code of a logic function part under the path according to a standard verilog syntax, wherein the logic function firstly generates a counter clk _ cnt with a count value of 0-3, expands the bit width of the acquired data to the maximum bit width when the counter value is 0, keeps the data unchanged when the counter value is 1, 2 and 3, and splits the data with the expanded bit width into 4 output with consistent width from MSB to LSB when the counter value is 0, 1, 2 and 3, wherein the bit width is the minimum bit width;
information defining an integrator module having an output port, comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ itg _ one path, and automatically generating an RTL code of a logic function part under the path according to a standard verilog syntax, wherein the logic function is y (n) ═ x (n) + y (n-1), and the coding module expands the bit width of input data and splits the bit width of the input data into 4 bits of consistent data from MSB to LSB, so that the logic function is converted into y (n) ═ x (n) + y (n-4); because the input signal is formed by every 4 data to form a complete data, the carry signal generated by each addition operation needs to be delayed by one clk clock period, the clk clock period is used as an addend to participate in the next addition operation, the carry signal generated by the last data in every four data is set to zero through the enable signal en _ itg, and finally the carry signal is output as y (n-4);
information defining an integrator module having four output ports, comprising: calling a third function to automatically generate RTL codes of port parts under a path _ RTL _ itg _ four path by using the module name, the input and output signals and the internal signals; automatically generating RTL codes of a logic function part under the path according to a standard verilog syntax, wherein the logic function is y (n) ═ x (n) + y (n-1), and the logic function is converted into y (n) ═ x (n) + y (n-4) because the coding module expands the bit width of input data and splits the bit width of the input data into 4 bits of data with consistent bit width from MSB to LSB; because the input signal is that every 4 data constitute a complete data, the carry signal generated by the addition operation needs to be delayed by one clk clock period, and the clk clock period is used as an addend to participate in the next addition operation, and the carry signal generated by the last data in every four data is set to zero through the enable signal en _ itg, and finally the four outputs are y (n-1), y (n-2), y (n-3) and y (n-4) respectively;
information defining a decimator module, comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ specification path by using the module name, the input and output signals and the internal signal; automatically generating RTL codes of a logic function part under the path according to standard verilog syntax, wherein the logic function is to perform down sampling on four paths of signals output by an integrator module comprising four output ports through a frequency division clock clk _ destination generated by a clock generation module, generate a counter with a count value of 0-4 x D, convert the four paths of sampling signals into one path of signals through the value of the corresponding counter and output the signals, and finally complete the D-time extraction function;
information defining a comb filter module comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ comb path by using the module name, the input and output signals and the internal signal; under the path, the RTL code of the logic function part is automatically generated according to the standard verilog syntax, wherein the logic function is y (n) ═ x (n) — x (n-4), and the encoding module expands the bit width of the input data and splits the bit width of the input data into 4 bits of consistent data from MSB to LSB in sequence. And the input signal constitutes a complete data every 4 data, so the logic function is converted into y (n) x (n-4); because the input data is in a binary complement form, subtraction is converted into addition through inversion, wherein every 4 data form complete data, so a carry signal generated by the addition needs to be delayed by one clock clk _ comb period backwards to be used as an addend to participate in the next addition, and the carry signal generated by the last data in every four data is set to be 1 by using an enable signal en _ comb;
information defining a serial-to-parallel conversion module, comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ parallel _ to _ serial path by using the module name, the input and output signals and the internal signal; automatically generating RTL codes of a logic function part under the path according to standard verilog syntax, wherein the logic function is to sample input data by using a sampling clock clk _ comb of a comb filter module to obtain sampling signals respectively delayed by 1, 2, 3 and 4 clock clk _ comb periods; sampling and recombining sampling signals respectively delayed by 1, 2, 3 and 4 clock clk _ comb periods through a frequency division clock clk _ parallel _ to _ serial generated by a clock generation module to obtain data after serial-parallel conversion, and intercepting the data to reserve effective bit output with the same size as the acquired output bit width;
information defining a cascaded integrator module, comprising: calling a third function and a fifth function to automatically generate an RTL code of a port part and a module instantiation under a path _ RTL _ cascade _ integers path by using the module name, the input and output signals and the internal signal; determining the calling times of the module instantiation functions according to the cascade number N, instantiating an integrator comprising four output ports if the cascade number is equal to 1, and instantiating N-1 integrators comprising one output port and an integrator comprising four output ports if the cascade number is not equal to 1;
information defining a cascaded comb filter module, comprising: calling a third function and a fifth function to automatically generate port part and module instantiated RTL codes under a path _ RTL _ cascade _ comb path by the aid of the module name, input and output signals and internal signals; performing modular instantiation on the comb filter according to the cascade number N;
information defining a top module, comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ top _ cic path by using the module name, the input and output signals and the internal signal; and calling a fifth function to instantiate the clock generation module, the coding module, the cascade integrator, the extractor, the cascade comb filter and the serial-parallel conversion module.
In the method for realizing automatic generation of CIC filter codes based on python, a python script is operated, corresponding parameter information is input in a popped graphical window according to prompts, and the collected parameter information is stored in a list; processing the parameter information in the list, and automatically generating RTL codes of all sub-modules, instantiated RTL codes of modules and RTL codes of a top module; checking whether the generated checking result has a problem; in addition, the Python language is simple and easy to understand, and in the text of "Python language programming characteristics and applications", the Python language also shows the characteristics of low learning difficulty, simple and clear grammar, easy understanding and the like. Therefore, the invention uses python language to compile the CIC filter RTL code automatic generation script, and the parameter information of the CIC filter can be changed by modifying the graphic interface dialog box, thereby being easily understood and applied by technicians in the field, greatly reducing the workload and improving the working efficiency.
Drawings
FIG. 1 is a schematic diagram of a multi-stage CIC filter structure;
FIG. 2 is a flow chart of a method for automatically generating CIC filter codes based on python according to the present invention;
FIG. 3 is a schematic diagram of a structure of a programmable CIC decimation filter based on a nibble algorithm;
FIG. 4 is a graphical interface diagram;
FIG. 5 is a CIC decimation filter simulation;
fig. 6 is a waveform diagram of a CIC decimation filter simulation.
Detailed Description
The following describes in detail a method for implementing automatic generation of CIC filter codes based on python according to the present invention with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, a method for implementing automatic generation of CIC filter codes based on python includes the following steps:
s1, running a python script, and respectively storing input data, extraction multiples, delay factors, cascade numbers and output bit widths of the CIC filter shown in the figure 2 in a popped graphical window according to prompts;
s2, processing the list parameters, and automatically generating RTL codes of each module, each module instantiation and each top module;
and S3, checking whether the generated checking result has a problem or not.
The python script is mainly divided into six functions:
the first function is used for generating a graphical interface;
the second function is used for completing the definition of interface bit width;
the third function is used for automatically generating RTL codes of port definition, I/O description and internal signal description parts according to verilog syntax specification;
the fourth function is used for automatically generating RTL codes of different frequency division clocks according to verilog syntax specification;
the fifth function is used for automatically generating a modular instantiated RTL code according to verilog grammar specification;
the sixth function is used for completing the scheduling management of each function and automatically generating the RTL code fixed by each module of the CIC filter;
operating the instance on a script-completed basis;
automatically generating an input data bit width B with an extraction multiple D of 2 according to design requirements in22, the cascade number N is 4, the delay factor M is 1, and the output data bit width BoutThe RTL code of the CIC filter is 22, wherein the CIC filter is implemented by a nibble serial algorithm, and as shown in fig. 3, the structure diagram of the whole programmable CIC decimation filter based on the nibble algorithm can effectively reduce power consumption and reduce design area.
After the script is operated, the sixth function calls the first function to generate a graphical window, the data word length is input in the window 22, the extraction multiple is 2, the delay factor is 1, the cascade number is 4, and the output bit width is 22, and as shown in fig. 4, a button automatic RTL code generation is clicked;
immediately calling a second function to generate a maximum bit width 28 and a minimum bit width 7 of the signal;
obtaining a path of a current python script by using an os.getcwd () function, obtaining a directory of the current script by using an os.path.diameter () function, creating a new rtl folder below the directory, and storing the directory path by using a variable path _ rtl.
Defining module names, wherein: a clock generation module name clk _ gen, an encoding module name code, an integrator name itg _ one _ out containing one output port, an integrator name itg _ four _ out containing four output ports, a decimator name resolution, a comb name comb, a cascade integrator name cascade _ integers, a cascade comb name cascade _ comb, a top module name top _ cic; the specific path of the RTL code file of each module in the path _ RTL directory is that the path _ RTL symbol variable plus the name of each module plus the symbol ". v" is stored in 11 variables of path _ RTL _ clk _ gen, path _ RTL _ code, path _ RTL _ itg _ one, path _ RTL _ itg _ four, path _ RTL _ decision, path _ RTL _ comb, path _ RTL _ parallel _ to _ serial, path _ RTL _ cascade _ integrators, path _ RTL _ cascade _ bs, and path _ RTL _ top _ cic respectively;
information defining a clock generation module, comprising: module names clk _ gen, input clock clk, input reset signal rst _ n, output clock signals clk, clk _ dec, clk _ comb, and clk _ partial 2sil, output enable signals en _ itg and en _ comb; wherein the internal signal reg type includes: clk _ temp, clk _ comb _ temp, clk _ parallel _ to _ serial _ temp, en _ itg _ temp, en _ comb _ temp, clk _ cnt1, [1:0] clk _ cnt2, and [2:0] clk _ cnt3, calling a third function to automatically generate a port part RTL code under the path _ RTL _ clk _ gen path, and calling a fourth function to generate counters clk _ cnt1, clk _ cnt2, and clk _ cnt3, which count from 0 to 1, 3, and 7, respectively; when the count value of the counter clk _ cnt1 is 0, the clock clk _ comb _ temp is inverted to generate a clock clk _ comb; when the counter clk _ cnt2 is equal to 3, the clock en _ itg _ temp is inverted to generate an enable signal en _ itg; when the value of the counter clk _ cnt3 is 1-2, the clock en _ comb _ temp is inverted to generate an enable signal en _ comb, a clock signal clk _ decimate and clk _ partial 2 sil;
information defining an encoding module, comprising: module name code, input clock clk, input reset signal rst _ n, input data [21:0] din, output data [6:0] dout; the internal signal reg type includes: [1:0] clk _ cnt and [21:0] din _ d1, wire type [27:0] din _ wid _ exten _ d1, call the third function to automatically generate the RTL code of the port part under the path _ RTL _ code; simultaneously, automatically generating an RTL code of a logic function part under the path according to a standard verilog grammar, wherein the logic function firstly generates a counter clk _ cnt with a count value of 0-3, when the counter value is 0, expanding the acquired data bit width 22 to the maximum bit width 28, when the counter value is 1, 2 and 3, keeping the data unchanged, and when the counter value is 1, 2 and 3, splitting the data din _ wid _ exten _ d1 with the expanded bit width into 4 output signals dout with consistent bit width from MSB to LSB;
information defining an integrator module having an output port, comprising: a module name itg _ one _ out, an input clock clk, an input enable signal en _ itg, an input reset signal rst _ n, input data [6:0] din, output data [6:0] dout; the internal signal reg type includes: [6:0] sum _ d1, [6:0] sum _ d2, [6:0] sum _ d3, [6:0] sum _ d4 and msb _ sum _ nxt _ d1, the wire type comprising: 0, sub _ nxt and co _ sub _ nxt, calling a third function to automatically generate RTL codes of the port part under the path _ RTL _ itg _ one path; under the path, according to a standard verilog grammar, automatically generating an RTL code of a logic function part, wherein the logic function is y (n) (n) (+ y (n-4)), corresponding to sum _ nxt ═ din + sum _ d4+ co _ sum _ nxt, wherein sum _ d1, sum _ d2, sum _ d3 and sum _ d4 are obtained by delaying a clk sampling sum _ nxt signal by one, two, three and four cycles respectively, and since an input signal is formed by 4 data, a complete data, a carry signal sum _ nxt [7] generated by the addition operation needs to be delayed by one clock cycle, the next addition operation is performed as an addition number, enabling signals en _ itg and msb _ sum _ nxt _ d1 are combined with logic, the carry signal generated by the last data in every four data is set to zero, and the final output signal sum _ 4;
information defining an integrator module having four output ports, comprising: module name itg _ one _ out, input clock clk, input enable signal en _ itg, input reset signal rst _ n, input data [6:0] din; the output data includes: [6:0] dout _ d1, [6:0] dout _ d2, [6:0] dout _ d3, and [6:0] dout _ d 4; the internal signal reg type includes: [6:0] sum _ d1, [6:0] sum _ d2, [6:0] sum _ d3, [6:0] sum _ d4 and msb _ sum _ nxt _ d1, the wire type comprising: 0, sub _ nxt and co _ sub _ nxt, calling a third function to automatically generate RTL codes of the port part under a path _ RTL _ itg _ four path; under the path, the RTL code of the logic function part is automatically generated according to the standard verilog grammar, wherein the logic function is y (n) (n) (+ y (n-4)), corresponding to sum _ nxt ═ din + sum _ d4+ co _ sum _ nxt, wherein sum _ d1, sum _ d2, sum _ d3 and sum _ d4 are obtained by delaying the clk sampling sum _ nxt signal by one, two, three and four cycles respectively, as the input signals are every 4 data to form a complete data, the carry signal sum _ nxt [7] generated by the addition operation needs to be delayed by one clock cycle, the carry signal sum _ nxt [7] is added as an addend, the enable signal en _ itg and the msb _ sum _ nxt _ d1 are combined with logic, the carry signal generated by the last data in each four data is set to zero, and finally the carry signals sum _ 387 _ 12, sum _ 12 and sum _ 12 are output as addend, sum _ 38725 and sum _ 12 are output as addend, addend _ 12 _ d _ 38725 and sum _ 12 are output as addend, respectively, sum _ d2, sum _ d3, and sum _ d 4;
information defining an extractor module, comprising: the module name resolution, the input clock includes: clk and clk _ Decimate, and an input reset signal rst _ n, and the output data comprises: [6:0] din1, [6:0] din2, [6:0] din3, and [6:0] din4, the output data including: [6:0] dout; the internal signal reg type includes: [6:0] din1_ d1, [6:0] din1_ d2, [6:0] din1_ d3, [6:0] din1_ d4, [6:0] dout _ temp and [2:0] clk _ cnt, calling a third function to automatically generate RTL code of the port part under the path _ RTL _ settlement path; automatically generating RTL codes of a logic function part under the path according to standard verilog grammar, wherein the logic function is to respectively perform down-sampling on four input signals din1, din2, din3 and din4 through a frequency division clock clk _ decimate generated by a clock generation module to output 4 signals din1_ d1, din1_ d2, din1_ d3 and din1_ d4, generate a counter with a count value of 0-7 by using clk, and convert the four sampling signals into one signal output dout through the value of the corresponding counter;
information defining a comb filter module comprising: the method comprises the steps of obtaining a module name comb, an input clock clk _ comb, an input enable signal en _ comb, an input reset signal rst _ n and input data [6:0] din; output data [6:0] dout; the internal signal reg type includes: [6:0] din _ n _ d1, [6:0] din _ n _ d2, [6:0] din _ n _ d3, [6:0] din _ n _ d4 and msb _ sub _ nxt _ d1, the wire type includes: 0 sub _ nxt and co _ sub _ nxt, calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ comb path; under the path, the RTL code of the logic function portion is automatically generated according to a standard verilog syntax, wherein the logic function is y (n) ═ x (n) (-x (n-4), corresponding to sub _ nxt ═ din + din _ n _ d4+ co _ sub _ nxt, since the input data is in a binary complement form, the subtraction can be converted into addition by inverting, the data obtained after clk _ comb sampling din inverting is delayed by one, two, three and four cycles respectively to obtain din _ n _ d1, din _ n _ d2, din _ n _ d3 and din _ n _ d4 signals, wherein every 4 data form one complete data, so the carry signal generated by the addition operation needs to be delayed by one clock clk _ b cycle, and the carry signal generated by the enable signal en _ b for the last data in every four data is set to be 1; under the path, automatically generating an RTL code of a logic function part according to a standard verilog grammar, wherein the logic function is y (n) ((n)) + y (n-4), and corresponds to sum _ nxt ═ din + sum _ d4+ co _ sum _ nxt, wherein sum _ d1, sum _ d2, sum _ d3 and sum _ d4 are obtained by delaying a clk sampling sum _ nxt signal by one, two, three and four periods respectively, and since an input signal is formed by 4 data, a complete data, a carry signal sub _ comb clock period needs to be delayed backwards for one cycle, the carry signal sub [7] generated by the addition operation is used as an addend to participate in the next addition operation, an enable signal en _ b and a msb _ comb _ nxt _ d1 are made into logic or not participate in the addition operation, and finally the carry signal generated by the last data in every four data is output;
information defining a serial-to-parallel conversion module, comprising: the module name parallel _ to _ serial, the input clock comprises: clk _ comb and clk _ partial 2 sil; input reset signal rst _ n, input data [6:0]]din; output data [21:0]]dout; the internal signal reg type includes: [6:0]din_d1、[6:0]din_d2、[6:0]din_d3、[6:0]din_d4、[6:0]dout_temp1、[6:0]dout_temp2、[6:0]dout _ temp3 and [6:0]]dout _ temp4, wire type [27:0]]dout _ temp, calling a third function to automatically generate an RTL code of the port part under a path _ RTL _ parallel _ to _ serial path; automatically generating RTL codes of a logic function part under the path according to standard verilog grammar, wherein the logic function is to sample input data din by using a sampling clock clk _ comb to obtain sampling signals respectively delayed by 1, 2, 3 and 4 clock cycles, sample four paths of data din _ d1, din _ d2, din _ d3 and din _ d4 by using a frequency division clock clk _ parallel 2sil, splice the four paths of sampled data into data dout _ temp with 28-bit width, truncate the bit width of the output data dout to 22-bit width, and truncate the bit width of the output data to 22-bit width by using a truncation formula BLSB＝Nlog2 DM+Bin-BoutCalculating discard BLSBLess significant bits of length while preserving the output bit width B required by the final stageoutThe most significant bits of the same length, according to D being 2, N being 4, M being 1, Bin，BoutTo 22, calculate BLSBIs 4, so dout _ temp [25:4 ]]+dout_temp[3]；
Information defining a cascaded integrator module, comprising: module names cascade _ integrators, an input clock clk, an input enable signal en _ itg, an input reset signal rst _ n, and input data [6:0] din; the output data includes: [6:0] dout _ d1, [6:0] dout _ d2, [6:0] dout _ d3, and [6:0] dout _ d 4; the internal signal wire type includes: (7: 0) itg1_ sum _ nxt _ d4, [7:0] itg2_ sum _ nxt _ d4 and [7:0] itg3_ sum _ nxt _ d4, and calling a third function to automatically generate RTL code of the port part under the path _ RTL _ cassette _ integrators path; calling a fifth function to automatically generate an RTL code of a module instantiation part under the path, instantiating an integrator module comprising one output port three times and then instantiating an integrator module comprising four output ports once because N is equal to 4;
information defining a cascaded comb filter module, comprising: the module name cascade _ comb, an input clock clk _ comb, an input enable signal en _ comb, an input reset signal rst _ n and input data [6:0] din; the output data includes: [6:0] dout; the internal signal wire type includes: [7:0] comb1_ sub _ nxt, [7:0] comb2_ sub _ nxt and [7:0] comb3_ sub _ nxt, calling a third function to automatically generate RTL code of a port part under a path _ RTL _ cassette _ comb path; calling a fifth function to automatically generate an RTL code of a module instantiation part under the path, and instantiating the four-time comb filter module because N is equal to 4;
information defining a top module, comprising: module name top _ cic, input clock clk, input reset signal rst _ n, input data [21:0] din; the output data includes: [21:0] dout; the internal signal wire type includes: en _ itg, clk _ comb, en _ comb, clk _ dec, clk _ par 2sil, input and output variables dout _ split, itg4_ sum _ nxt _ d1, itg4_ sum _ nxt _ d2, itg4_ sum _ nxt _ d3, itg4_ sum _ nxt _ d4, dout _ decimate and dout _ comb, and calling a third function to automatically generate RTL code of the port part under the path _ RTL _ top _ cic; calling a fifth function to automatically generate RTL codes of a clock generation module, a coding module, a cascade integrator module, an extractor module, a cascade comb filter module and a serial-parallel conversion module in the path;
the final report is checked for syntax errors.
And after the checking result is correct, returning to the main directory, wherein an RTL folder appears under the directory, and the RTL folder generates complete RTL codes containing CIC filters, including all sub-modules, module instantiations and top modules.
Simulation by giving excitation to the generated RTL code, where the input data is represented by a frequency FSClock sample acquisition of/4. The final simulation results are shown in fig. 5 and fig. 6, and it can be seen that the CIC decimation filter realizes 2 times down-sampling and filtering functions.
The above description is only for the purpose of describing the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are intended to fall within the scope of the appended claims.

Claims (10)

1. A method for realizing automatic generation of CIC filter codes based on python is characterized by comprising the following steps:
running a python script, inputting corresponding parameter information in a popped graphical window according to prompts, and storing the collected parameter information through a list;
processing the parameter information in the list, and automatically generating RTL codes of all sub-modules, instantiated RTL codes of modules and RTL codes of a top module;
and checking whether the generated checking result has a problem.
2. The method for implementing automatic generation of CIC filter codes based on python as claimed in claim 1, wherein the python script generates the graphical window by introducing a tkater library, and indicates parameter information including input bit width, decimation factor, delay factor, cascade number and output bit width input to the CIC filter according to the window.
3. The method for realizing automatic generation of CIC filter codes based on python as claimed in claim 2, wherein the python script automatically generates each sub-module RTL code, module instantized RTL code and top-level module RTL code in the CIC filter according to verilog syntax specification.
4. A method for implementing automatic generation of CIC filter code based on python as claimed in claim 3 wherein the python script is divided into six functions:
a first function generates a graphical interface;
the second function completes the definition of interface bit width;
the third function automatically generates RTL codes of port definition, I/O description and internal signal description parts according to verilog syntax specification;
the fourth function automatically generates RTL codes of different frequency division clocks according to verilog syntax specification;
automatically generating a modular instantiated RTL code by a fifth function according to verilog syntax specification;
and the sixth function completes the scheduling management of each function and automatically generates the RTL code fixed by each module in the CIC filter.
5. The method for implementing CIC filter code automatic generation based on python as claimed in claim 4, wherein the first function produces a graphical window by introducing a tkater library; the input port bit width B of the corresponding CIC filter is input according to the label Lable indication in the windowinDecimation factor D, delay factor M, cascade number N and output bit width BoutAnd information is acquired by using a get () function and stored in the list index.
6. The method of claim 5 for implementing automatic generation of CIC filter code based on python, wherein the second function utilizes formula Bmax＝Nlog2 DM+BinAnd Bmin＝BmaxAnd 4, calculating to obtain the maximum bit width B of the port of the whole CIC filtermaxAnd minimum bit width BminStoring the data into a list, wherein N is the number of cascade, D is the extraction multiple, and BinIs the input port bit width; if the maximum bit width is not an integer multiple of 4, then the calculated value maximum bit width is extended to be the closest integer multiple of 4 to the value.
7. The method of claim 6, wherein the third function automatically generates RTL codes for port parts according to verilog syntax specification, first each module starts with a keyword module, defines port names, and puts I/O descriptions into port lists; the signal with the input/output and internal signal bit width of 1 is positioned in a list, the signal with the bit width larger than 1 is positioned in a dictionary embedded in the list, the name indexes of signal variables are respectively bus _ name, bus _ max and bus _ min, and the values are respectively the maximum value and the minimum value of the signal name and the signal bit width; the internal reg and wire type signal definition is completed, the maximum value and the minimum value of the signal character and the signal bit width are obtained through a built-in function len (max), and the RTL code writing format is adjusted according to the maximum length.
8. The method for implementing automatic generation of CIC filter codes based on python according to claim 7, wherein the fourth function obtains different division multiples by operation according to the obtained decimation multiple D, stores the division multiples by using a list, and generates a corresponding counter by using the division multiples as a count value; generating a value or an interval of a clock turnover point when a counter counts according to clock requirements, utilizing a list to register, and generating low-frequency clocks with different duty ratios and different frequency division multiples through the counter; the frequency division clock module generates signals comprising: an enable signal en _ itg required by the integrator module, a sampling clock clk _ decimate required by the decimator module, a sampling clock clk _ comb and an enable signal en _ comb required by the comb filter, and a sampling clock clk _ parallel _ serial required by the serial-parallel conversion module; wherein: en _ itg is a 4 division of clk, clk _ comb is a D division of clk, clk _ decimate, en _ comb, and clk _ parallel _ to _ serial are all a 4 x D division of clk, and the duty cycle and phase are the same.
9. The method for realizing automatic generation of CIC filter codes according to claim 8, wherein the fifth function extracts required module interface information, generates modular instantiated RTL codes, extracts characters in a file, separates the characters into a character string list by rows, assigns a variable to the character string list, pre-compiles a regular expression containing interface information, searches the regular expression in each row by a for loop, if the regular expression is found, proceeds to the next step, searches the regular expression in each row by a for loop, separates the searched character string into individual character strings by spaces or commas, extracts interface information according to subscripts, and completes modular instantiation by defining module names and link signals.
10. The method for realizing automatic generation of CIC filter codes based on python as claimed in claim 9, wherein the sixth function defines the basic module names, port lists, input/output ports and internal signals in the CIC filter, and fixed logic function descriptions and end symbols according to a standard verilog syntax, and completes the scheduling of the first function, the second function, the third function, the fourth function and the fifth function at the same time, and finally completes the generation of each module, module instantiation and top module RTL codes in the CIC filter; the method comprises the following steps:
calling a first function to generate a graphical interface;
calling a second function to obtain the maximum bit width and the minimum bit width of the signal bus;
obtaining a path of a current python script by using an os.getcwd () function, obtaining a directory of the current script by using an os.path.diameter () function, creating a new rtl folder below the directory, and storing the directory path by using a variable path _ rtl;
defining module names, including: the device comprises a clock generation module, a coding module, an integrator module comprising one output port, an integrator module comprising four output ports, an extractor module, a comb filter module, a cascade integrator module, a cascade comb filter module and a top module; the specific path of the RTL code file of each module in the path _ RTL directory is the 11 variables of path _ RTL symbol variable plus each module name plus symbol ". v", and is stored into path _ RTL _ clk _ gen, path _ RTL _ code, path _ RTL _ itg _ one, path _ RTL _ itg _ four, path _ RTL _ deletion, path _ RTL _ comb, path _ RTL _ parallel _ to _ serial, path _ RTL _ cascade _ integrators, path _ RTL _ cascade _ bs, and path _ RTL _ top _ cic, respectively;
information defining a clock generation module, comprising: the method comprises the steps that a module name, input and output signals and internal signals are called, a third function and a fourth function are called to automatically generate RTL codes of a port part under a path _ RTL _ clk _ gen, and simultaneously, RTL codes of a logic function part are automatically generated under the path according to standard verilog syntax, wherein the logic function is that a sampling frequency division clock required by each module is generated through a counter;
information defining an encoding module, comprising: calling a third function to automatically generate an RTL code of a port part under a path by using a module name, input and output signals and internal signals, and simultaneously automatically generating the RTL code of a logic function part under the path according to a standard verilog syntax, wherein the logic function firstly generates a counter clk _ cnt with a count value of 0-3, expands the bit width of the acquired data to the maximum bit width when the counter value is 0, keeps the data unchanged when the counter value is 1, 2 and 3, and splits the data with the expanded bit width into 4 output with consistent width from MSB to LSB when the counter value is 0, 1, 2 and 3, wherein the bit width is the minimum bit width;
information defining an integrator module having an output port, comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ itg _ one path, and automatically generating an RTL code of a logic function part under the path according to a standard verilog syntax, wherein the logic function is y (n) ═ x (n) + y (n-1), and the coding module expands the bit width of input data and splits the bit width of the input data into 4 bits of consistent data from MSB to LSB, so that the logic function is converted into y (n) ═ x (n) + y (n-4); because the input signal is formed by every 4 data to form a complete data, the carry signal generated by each addition operation needs to be delayed by one clk clock period, the clk clock period is used as an addend to participate in the next addition operation, the carry signal generated by the last data in every four data is set to zero through the enable signal en _ itg, and finally the carry signal is output as y (n-4);
information defining an integrator module having four output ports, comprising: calling a third function to automatically generate RTL codes of port parts under a path _ RTL _ itg _ four path by using the module name, the input and output signals and the internal signals; automatically generating RTL codes of a logic function part under the path according to a standard verilog syntax, wherein the logic function is y (n) ═ x (n) + y (n-1), and the logic function is converted into y (n) ═ x (n) + y (n-4) because the coding module expands the bit width of input data and splits the bit width of the input data into 4 bits of data with consistent bit width from MSB to LSB; because the input signal is that every 4 data constitute a complete data, the carry signal generated by the addition operation needs to be delayed by one clk clock period, and the clk clock period is used as an addend to participate in the next addition operation, and the carry signal generated by the last data in every four data is set to zero through the enable signal en _ itg, and finally the four outputs are y (n-1), y (n-2), y (n-3) and y (n-4) respectively;
information defining a decimator module, comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ specification path by using the module name, the input and output signals and the internal signal; automatically generating RTL codes of a logic function part under the path according to standard verilog syntax, wherein the logic function is to perform down sampling on four paths of signals output by an integrator module comprising four output ports through a frequency division clock clk _ destination generated by a clock generation module, generate a counter with a count value of 0-4 x D, convert the four paths of sampling signals into one path of signals through the value of the corresponding counter and output the signals, and finally complete the D-time extraction function;
information defining a comb filter module comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ comb path by using the module name, the input and output signals and the internal signal; under the path, the RTL code of a logic function part is automatically generated according to the standard verilog syntax, wherein the logic function is y (n) ═ x (n) — x (n-4), and the coding module expands the bit width of the input data and splits the bit width of the input data into 4 bits of data with consistent bit width from MSB to LSB; and the input signal constitutes a complete data every 4 data, so the logic function is converted into y (n) x (n-4); because the input data is in a binary complement form, subtraction is converted into addition through inversion, wherein every 4 data form complete data, so a carry signal generated by the addition needs to be delayed by one clock clk _ comb period backwards to be used as an addend to participate in the next addition, and the carry signal generated by the last data in every four data is set to be 1 by using an enable signal en _ comb;
information defining a serial-to-parallel conversion module, comprising: a third function is called to automatically generate an RTL code of a port part under a path _ RTL _ parallel _ to _ serial path by the aid of the module name, the input and output signals and the internal signal; automatically generating an RTL code of a logic function part under the path according to a standard verilog syntax, wherein the logic function is to sample input data by using a sampling clock clk _ comb of the comb filter module to obtain sampling signals respectively delayed by 1, 2, 3 and 4 clock clk _ comb periods; sampling and recombining sampling signals respectively delayed by 1, 2, 3 and 4 clock clk _ comb periods through a frequency division clock clk _ parallel _ to _ serial generated by a clock generation module to obtain data after serial-parallel conversion, and intercepting the data to reserve effective bit output with the same size as the acquired output bit width;
information defining a cascaded integrator module, comprising: calling a third function and a fifth function to automatically generate an RTL code of a port part and a module instantiation under a path _ RTL _ cascade _ integers path by using the module name, the input and output signals and the internal signal; determining the calling times of the module instantiation functions according to the cascade number N, instantiating an integrator comprising four output ports if the cascade number is equal to 1, and instantiating N-1 integrators comprising one output port and an integrator comprising four output ports if the cascade number is not equal to 1;
information defining a cascaded comb filter module, comprising: calling a third function and a fifth function to automatically generate port part and module instantiated RTL codes under a path _ RTL _ cascade _ comb path by the aid of the module name, input and output signals and internal signals; performing modular instantiation on the comb filter according to the cascade number N;
information defining a top module, comprising: calling a third function to automatically generate an RTL code of a port part under a path _ RTL _ top _ cic path by using the module name, the input and output signals and the internal signal; and calling a fifth function to instantiate the clock generation module, the coding module, the cascade integrator, the extractor, the cascade comb filter and the serial-parallel conversion module.
CN202210394707.XA 2022-04-15 2022-04-15 Method for realizing automatic generation of CIC filter code based on python Pending CN114675815A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210394707.XA CN114675815A (en) 2022-04-15 2022-04-15 Method for realizing automatic generation of CIC filter code based on python

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210394707.XA CN114675815A (en) 2022-04-15 2022-04-15 Method for realizing automatic generation of CIC filter code based on python

Publications (1)

Publication Number Publication Date
CN114675815A true CN114675815A (en) 2022-06-28

Family

ID=82079097

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210394707.XA Pending CN114675815A (en) 2022-04-15 2022-04-15 Method for realizing automatic generation of CIC filter code based on python

Country Status (1)

Country Link
CN (1) CN114675815A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116384295A (en) * 2023-06-02 2023-07-04 深圳市航顺芯片技术研发有限公司 Top file generation method and device, computer equipment and storage medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116384295A (en) * 2023-06-02 2023-07-04 深圳市航顺芯片技术研发有限公司 Top file generation method and device, computer equipment and storage medium
CN116384295B (en) * 2023-06-02 2023-09-22 深圳市航顺芯片技术研发有限公司 Top file generation method and device, computer equipment and storage medium

Similar Documents

Publication Publication Date Title
CN103269212B (en) Low cost low-power consumption Multilevel FIR filter implementation method able to programme
CN1413326A (en) Method and apparatus for saturated multiplication and accumulation in application specific signal processor
CN114675815A (en) Method for realizing automatic generation of CIC filter code based on python
US20130063287A1 (en) Decoding encoded data
CN105262462B (en) A kind of digital delay implementation method and circuit for integrated circuit
CN109655644A (en) A kind of method and apparatus reducing any wave signal output jitter
CN102982205A (en) Fixed polarity conversion method for design of digital circuit
CN102025377A (en) Improved cascaded integral comb interpolation filter
CN111045349A (en) Dynamic framing method of telemetering mining and editing device
CN111125976B (en) Automatic generation method of RTL model
CN105634439A (en) Design method of asynchronous shaping filter
WO2022253214A1 (en) Quantum state information processing system, quantum measurement and control system and quantum computer
CN115695589A (en) Method, system, device and medium for automatically generating CAN message analysis code
US3716843A (en) Modular signal processor
US20210165043A1 (en) Method of testing electronic circuits and corresponding circuit
CN111988018B (en) Automatic generation method for RTL model of half-band interpolation filter
CN107704656A (en) The design and implementation methods for being parameterized into mode filter based on FPGA
CN113572478A (en) Sigma-Delta type DAC digital processing method, device, computer equipment and storage medium
CN102868404A (en) Analog-to-digital (AD) conversion method based on cosine algorithm and Gray code
CN116781041B (en) Multi-rate conversion filter with high resource utilization rate
CN110635780A (en) Variable-rate baseband pulse shaping filter implementation method based on FPGA and filter
Anderson et al. Architecture and construction of a hardware sequential encoder for speech
CN109274460A (en) A kind of multi-bit parallel structure serially offsets interpretation method and device
CN109635393B (en) Distributed algorithm-based sigma-delta modulator design method and system
Watson e-Science in the Cloud with CARMEN

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination