JP2000022457A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate pluralities of circuits by a single power supply without forming an internal power supply circuit to adjust a gate voltage of each circuit with respect to the semiconductor device formed by integrating pluralities of the circuits including nonlinear circuits and linear circuits. SOLUTION: Pluralities of circuit sections 1-1-1-n being components of a semiconductor integrated circuit are provided respectively with pluralities of transistors(TRs) 2-1-2-n each having a different threshold voltage and each threshold voltage of pluralities of the TRs is set so that pluralities of the circuit sections are operated at respective operating points based on a voltage outputted from a single power supply 5. Preferably, the voltage from the single power supply is directly applied to each of pluralities of the circuit sections without an internal power supply circuit to adjust the voltage from the single power supply in the inside of the semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which various circuits including a non-linear circuit and a linear circuit are integrated. In recent communication systems, etc., the use of higher frequency bands, the use of microwave bands, and the use of microwave and millimeter band frequencies such as millimeter wave radars for automobiles have led to the use of nonlinear circuits such as multipliers. It has been demanded to provide a semiconductor device capable of relatively increasing the operating frequency by using a semiconductor device.

[0002] As a semiconductor integrated circuit constituting a semiconductor device of this type, in particular, an MMIC in which an active element such as a transistor and a passive element such as a microstrip line for impedance matching are integrally formed.
(Monolithic Microwave Integrated Circuit) has attracted attention recently because it can be manufactured at a small size and at low cost, has stable performance and mass productivity.

[0003]

2. Description of the Related Art First, a conventional structure of a semiconductor device including a semiconductor integrated circuit such as an MMIC as described above will be described with reference to FIGS. FIG. 7 is a block diagram showing the configuration of a first conventional semiconductor device, and FIG.
3 is a graph showing gate voltage versus drain current characteristics of a transistor used in the semiconductor device of the first conventional example. However, here, for simplicity of description, a semiconductor composed of a semiconductor integrated circuit in which two or more circuits having different operating points, for example, a first circuit 110 and a second circuit 120 are integrally formed. The device will be exemplified.

In the semiconductor integrated circuit shown in FIG. 7, a transistor functioning as an active element for operating each of the first circuit 110 and the second circuit 120 is provided. These transistors are usually formed simultaneously by the same manufacturing process in order to simplify the manufacturing process of the semiconductor integrated circuit. Therefore, the transistors 130 and 140 having the same characteristics are formed in the first circuit 110 and the second circuit 120. However, when the first circuit 110 is a non-linear circuit and the second circuit 120 is a linear circuit, the operating points of these circuits are different from each other, so that the gate voltages at which the transistors 130 and 140 operate also differ. .

[0005] These transistors 130 having the same characteristics,
Each of the 140 is typically a junction-type field effect transistor (normally, F
ET), and shows characteristics of the gate voltage Vg versus the drain current Id as shown by the curve in FIG.
In FIG. 8, Vth indicates a threshold voltage (threshold voltage) of the gate voltage Vg when the drain current Id of the FET becomes zero.

Further, in FIG. 8, a is the first circuit 1
10 indicates an operating point, and Va indicates a transistor 130 necessary for operating the first circuit 110 at the operating point a.
3 shows the gate voltage. On the other hand, b indicates the operating point of the second circuit 120, and Vb indicates the transistor 1 necessary for operating the second circuit 120 at the operating point b.
40 shows a gate voltage of 40. As is apparent from the figure, the gate voltage V of the transistor 130 in the nonlinear circuit
a needs to be set near the threshold voltage Vth, and the gate voltage Vb of the transistor 140 in the linear circuit is required.
Lower value.

Therefore, in the first conventional semiconductor device, as shown in FIG. 7, a first power supply 150 for supplying the gate voltage Va of the transistor 130 in the first circuit 110 and a second power supply 150 are provided. Transistor 14 in circuit 120
Second power supply 160 for supplying a gate voltage Vb of 0
And must be prepared separately. That is, in the semiconductor device of the first conventional example, in a semiconductor integrated circuit in which two circuits having different operating points are formed integrally,
In order to supply different gate voltages to the transistors in the circuit, it was necessary to add two power supplies.

FIG. 9 is a block diagram showing the configuration of a second conventional semiconductor device which has been devised to address the above-mentioned disadvantages. However, also in this case, for the sake of simplicity, the first circuits 1 having different operating points are used.
A semiconductor device including a semiconductor integrated circuit in which the second circuit 120 and the second circuit 120 are integrally formed is exemplified. The characteristics of the transistors 130 and 140 in the first and second circuits 110 and 120 are the same as those shown in the graph of FIG.

In the semiconductor integrated circuit shown in FIG. 9, the transistor 1 in the first and second circuits 110 and 120
Instead of providing two power supplies separately for each of the power supplies 30 and 140, only a single common power supply 170 is provided. However, in this case, an internal power supply voltage for adjusting the voltage Vc output from the common power supply 170 to generate gate voltages Va and Vb for driving the transistors 130 and 140, respectively, inside the semiconductor integrated circuit. It becomes necessary to newly form the generation circuit 180.

[0010]

As described above, in a semiconductor device comprising a semiconductor integrated circuit in which two or more circuits having different operating points are integrally formed, it is necessary to operate the circuit at these operating points. Since the gate voltages required for the respective circuits are different from each other, it is necessary to add two or more power supply circuits for supplying these gate voltages to the transistors in the circuit as in the first conventional example. . In such a configuration, power supplies are required by the number of circuits constituting the semiconductor integrated circuit, and it is difficult to reduce the size of the semiconductor device.

On the other hand, when only one common power supply is provided for all the circuits constituting the semiconductor integrated circuit as in the second conventional example, the voltage of the common power supply is adjusted to adjust the voltage of the common power supply. It has been necessary to form an internal power supply circuit such as an internal power supply voltage generation circuit for generating a gate voltage of a number corresponding to the number of semiconductor devices in a semiconductor integrated circuit. In such a configuration, unnecessary power consumption occurs in the internal power supply circuit, which causes an increase in power consumption, and also causes a problem that the number of manufacturing processes for forming the internal power supply circuit dedicated to the semiconductor integrated circuit increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and does not require an extra internal power supply circuit in a semiconductor integrated circuit in which a plurality of circuits having different operating points are integrally formed. It is an object of the present invention to provide a semiconductor device capable of operating a plurality of circuits in an integrated circuit with a single power supply.

[0013]

FIG. 1 is a block diagram showing the principle configuration of the present invention. However, here, a simplified configuration of a semiconductor device in which a plurality of circuit portions (1-1 to 1-n, n is a positive integer of 2 or more) is integrally shown. In this case, the configuration of the plurality of circuit units in FIG.
In order to clarify that the configuration is different from the configuration of FIGS. 7 and 9, the expression “plurality of circuit units” is used.

To solve the above problems, the present invention provides:
As illustrated in FIG. 1, a plurality of circuit units having different operating points (for example, a first circuit unit to an n-th circuit unit 1-1 to 1-
n) in an integrated circuit, a plurality of transistors having different threshold voltages (for example, first transistor to
N-th transistors 2-1 to 2-n) are provided, and the plurality of circuit units operate at the operating points based on the voltage Vgx output from the single power supply 5, respectively. It is configured to set each threshold voltage.

Preferably, in the semiconductor device of the present invention, the output from the single power supply 5 is provided without providing an internal power supply circuit for adjusting the voltage Vgx output from the single power supply 5 inside the semiconductor device. The voltage Vgx is directly supplied to each of the plurality of circuit units. further,
Preferably, in the semiconductor device of the present invention, the single power supply 5
Is used as a gate voltage for operating each of the plurality of circuit units at the operating point.

In a preferred embodiment of the present invention, a plurality of circuit units including at least one non-linear circuit and at least one linear circuit (for example, a first circuit unit to an n-th circuit unit)
In a semiconductor device in which the circuit units 1-1 to 1-n are integrated circuits, a plurality of transistors (for example,
First transistor to n-th transistor 2-1 to 2-
n), and the threshold voltage of each of the plurality of transistors is set so that each of the plurality of circuit units operates based on the voltage output from the single power supply 5.

FIG. 2 is a graph for explaining the principle of the present invention. However, here, in order to compare with the gate voltage-drain current characteristics (see FIG. 8) of the transistor used in the above-described conventional semiconductor device, two transistors (first transistor) among a plurality of FETs are used. The gate voltage-drain current characteristics of 2-1 and the second transistor 2-2) will be representatively shown.

In FIG. 2, a solid line indicates a first circuit unit 1-.
1 shows a gate voltage-drain current characteristic of the first transistor 2-1 having a threshold voltage Vth1 used in the first circuit unit 1, and a broken line indicates a threshold voltage used in the first circuit unit 1-1. 13 shows the gate voltage-drain current characteristics of the second transistor 2-2 at Vth2. As is clear from the gate voltage-drain current characteristics of FIG. 2, in the semiconductor device of the present invention, two types of threshold voltages different from each other are provided for the first circuit portion 1-1 and the second circuit portion 1-2. Uses transistors.

More specifically, in the present invention, as shown in FIG. 2, the threshold voltage Vth1 of the first transistor 2-1 provided in the first circuit section 1-1 is increased by the second circuit section. The threshold voltage Vth2 of the second transistor 2-2 provided in 1-2 is changed. As a result, the gate voltage versus drain current characteristic as shown by the solid line is obtained for the first transistor 2-1 and the gate voltage versus drain current characteristic as shown by the broken line for the second transistor 2-2. Drain current characteristics are obtained.
In this case, for the gate voltage Va of the first transistor 2-1 required for operating the first circuit unit 1-1 at the operating point a, the operating point a of the first circuit unit 1-1 The threshold voltage Vth1 of the first transistor 2-1 and the second transistor 2 are set so that the operating point b of the second circuit unit 2-2 is aligned.
-2 threshold voltage Vth2 is set. Further, by setting the voltage Vgx output from the single power supply 5 to the gate voltage Va (that is, setting Va = Vgx), the voltage Vgx output from the single power supply 5 is changed to the first transistor 2- It can be used as a common gate voltage Va of the first and second transistors 2-2.

As the plurality of transistors as described above,
If an FET such as a HEMT (High Electron Mobility Transistor) is used, Ga
It should be noted that by simply changing the thickness of the supply layer of the two-dimensional electron gas of As (gallium arsenide), a plurality of transistors having different threshold voltages can be manufactured by a simple manufacturing process.

In summary, in the semiconductor device of the present invention, by setting the threshold voltages of a plurality of transistors provided in a plurality of circuits having different operating points to appropriate values, each of these transistors can be controlled. Since it is not necessary to provide an internal power supply circuit for generating the gate voltage to be supplied in the semiconductor integrated circuit, an unnecessary manufacturing process for forming the internal power supply circuit is reduced, and an unnecessary increase in power consumption is suppressed. Is done.

Thus, according to the present invention, in a semiconductor device in which a plurality of circuits having different operating points are integrated, an integrated power supply circuit for adjusting a gate voltage is not formed inside the semiconductor device. Can be used to operate the plurality of circuits.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention (hereinafter referred to as examples) will be described below with reference to the accompanying drawings (FIGS. 3 to 6). FIG. 3 is a block diagram showing a configuration of a basic embodiment based on the principle of the present invention, and FIG. 4 is a graph showing gate voltage versus drain current characteristics of the two FETs in FIG. Hereinafter, the same components as those described above will be denoted by the same reference numerals.

In the basic embodiment shown in FIG. 3, as a plurality of circuit sections (see FIG. 1) having different operating points, a non-linear circuit 10 to which an arbitrary input signal (IN) is inputted;
A linear circuit 20 for generating a corresponding output signal (OUT)
Are provided. In each of the nonlinear circuit 10 and the linear circuit 20, a transistor made of HEMT or the like is provided. In the nonlinear circuit 10, the first F
ET3 is used as a transistor having nonlinear characteristics, and the second FET 4 is used as a transistor having linear characteristics in the linear circuit 20.

Further, in FIG. 3, the first FET 3 and the second F3 are used as the aforementioned single power supply 5 (see FIG. 1).
A gate voltage supply power supply 50 for supplying a common voltage Vgx to ET4 is provided. The gate voltage supply power supply 50 includes a first FE necessary for operating the nonlinear circuit 10 and the linear circuit 20 at respective operating points.
A common voltage Vgx is output as the gate voltage (Va) of T3 and the first FET 4.

FIG. 4 shows typical characteristics of the gate voltage Vg and the drain current Id of the first FET 3 in the nonlinear circuit 10 and the second FET 4 in the linear circuit 20. In FIG. 4, the pinch-off voltage (ie, threshold voltage) Vpo1 of the first FET 3 and the pinch-off voltage Vpo2 of the second FET 4 are set to different values (here, Vpo1> Vpo2). When the above FET is formed using HEMT, two Fs having different threshold voltages are used.
When the ET is formed, the threshold voltage of the FET can be easily changed by changing the thickness of the GaAs two-dimensional electron gas supply layer, that is, the distance between the gate electrode and the two-dimensional electron gas. is there. Regarding the manufacturing process of the FET, only the step of making the thickness under the gate electrode of the first FET 3 smaller is added, and the second FET is added.
4 can be set to a value smaller than the pinch-off voltage Vpo1 of the first FET 3.

More specifically, as shown in FIG. 4, the operating point a of the nonlinear circuit 10 is near the pinch-off voltage Vpo1 of the first FET 3, and
The operating point b of 0 is near where the transconductance gm (gm = δId / δVg) of the second FET 4 is maximized. As described above, the pinch-off voltage Vpo1 of the second FET 4 is compared with the pinch-off voltage Vpo1 of the first FET 3.
By changing po2, the gate voltage vs. drain current characteristic as shown by the solid line is obtained for the first FET 3, and the gate voltage vs. drain current characteristic as shown by the broken line for the second FET4. Is to be obtained.

In this case, the gate voltage V of the first FET 3 necessary for operating the nonlinear circuit 10 at the operating point a is
a, the pinch-off voltage Vpo1 of the first FET 3 and the pinch-off voltage Vpo of the second FET 4 are set so that the operating point a of the nonlinear circuit 10 and the operating point b of the linear circuit 20 are aligned.
Set 2. Furthermore, by setting the voltage Vgx output from the gate voltage supply power supply 50 (FIG. 3), which is a single power supply, to the gate voltage Va (that is, Va).
= Vgx), and the voltage Vgx output from the gate voltage supply power supply 50 is changed to the first FET 3 and the second FET 3
Can be used as a common gate voltage Va of the FET4.

In the above-described basic embodiment, the configuration of the semiconductor device in which transistors having different threshold voltages are used for two types of circuits composed of a combination of a nonlinear circuit and a linear circuit has been described. Other arbitrary circuit combinations that are different from each other are possible. Further, the semiconductor integrated circuit of the present invention can be realized by using transistors having different threshold voltages for three or more types of circuits having different operating points.

FIG. 5 is a circuit diagram showing a configuration of a first specific example of the present invention. Here, the multiplier 11 and the gain amplifier 21 are used as the nonlinear circuit and the linear circuit shown in FIG. 3, respectively, and the multiplier 11 and the gain amplifier 21 are integrated into an integrated circuit.
An embodiment in which an IC is configured will be described. In the first specific embodiment shown in FIG.
It has a function of multiplying the operating frequency of the input signal IN input via the input terminal c. Meanwhile, the gain amplifier 21
Has a function of amplifying a signal input from the multiplier 11 via the capacitor 20c to a predetermined level.
The signal output from the gain amplifier 21 is
0c, and becomes the final output signal OUT.

Further, in the embodiment of FIG. 5, the matching circuit of the multiplier 11 is constituted by a short stub using the microstrip line 12 for the multiplier matching circuit and the capacitor 13, and the matching circuit also serves as a power supply circuit. I have. More specifically, the gate voltage power supply circuit of the FET 30 for the input matching circuit and the multiplier is constituted by the microstrip line 12 for the multiplier matching circuit and the capacitor 13, and the microstrip line 14 for the multiplier matching circuit and the capacitor 1
5 constitutes a drain voltage power supply circuit of the output matching circuit / multiplier FET 30.

Similarly, the matching circuit of the gain amplifier 21 is
It is composed of a short stub using a microstrip line 22 for a multiplier matching circuit and a capacitor 23, and the matching circuit also serves as a power supply circuit. More specifically, a gain amplifier matching circuit microstrip line 22 and a capacitor 23 constitute a gate voltage power supply circuit of an input matching circuit and gain amplifier FET 40, and a gain amplifier matching circuit microstrip line 24 and a capacitor 25. , FE for output matching circuit and gain amplifier
This constitutes a drain voltage power supply circuit of T40.

The multiplier matching circuit microstrip lines 12 and 14 constituting the gate voltage power supply circuit and the drain voltage power supply circuit in the multiplier 11 are connected to the ground potential via capacitors 13 and 15, respectively. Further, the voltage Vgx output from the gate voltage supply power supply (see FIG. 3) is supplied to the gate of the matching circuit / multiplier FET 30 via the multiplier matching device microstrip line 12 of the gate voltage power supply circuit. Further, the drain voltage Vd is supplied to the drain of the matching circuit / multiplier FET 30 via the multiplier matching circuit microstrip line 14 of the drain voltage power supply circuit.

On the other hand, a microstrip line 22 for a gain amplifier matching circuit constituting a gate voltage power supply circuit and a drain voltage power supply circuit in the gain amplifier 21,
24 is connected to the ground potential via capacitors 23 and 25, respectively. Further, a gate voltage (here, voltage Vgx) shared with the multiplier 11 is supplied to the gate of the matching circuit / gain amplifier FET 40 via the gain amplifier matching circuit microstrip line 22 of the gate voltage power supply circuit. Furthermore, the drain voltage Vd shared with the multiplier 11 is supplied to the drain of the matching circuit / gain amplifier FET 40 via the gain amplifier matching device microstrip line 24 of the drain voltage power supply circuit.

Matching circuit and multiplier FET in multiplier 11
The gate voltage vs. drain current characteristics of the matching circuit 30 and the gain amplifier FET 40 in the gain amplifier 21 are as follows:
Each of the above-mentioned characteristics of the first FET 3 in FIG. 4 (solid line)
And the characteristic of the second FET 4 (broken line).
That is, the operating point of the multiplier 11 is near the threshold voltage of the matching circuit / multiplier FET 30, and the operating point of the gain amplifier 21 is the matching circuit / gain amplifier FET4.
The transconductance gm of 0 is near the maximum. Here, the matching circuit / multiplier FET 30 is adjusted so that the operating point of the multiplier 11 and the operating point of the gain amplifier 21 match the gate voltage of the matching circuit / multiplier FET 30.
And the threshold voltage of the matching circuit / gain amplifier FET 40 are set. Further, by setting the voltage Vgx output from the single power supply to the gate voltage, the voltage Vgx is used as a common gate voltage of the matching circuit / multiplier FET 30 and the matching circuit / gain amplifier FET 40. Can be.

FIG. 6 is a circuit diagram showing a configuration of a second specific example of the present invention. Here, the low noise amplifier 11L is used as the nonlinear circuit and the linear circuit shown in FIG.
A description will now be given of an embodiment in which an MMIC is constructed by using the low-noise amplifier 11L and the gain amplifier 21 in an integrated circuit by using the gain amplifier 21 and the gain amplifier 21, respectively. In this case, since the configuration of the gain amplifier 21 is the same as the configuration of the first specific example (see FIG. 5),
Here, a detailed description of the configuration is omitted.

In the second specific embodiment shown in FIG. 6, the matching circuit of the low-noise amplifier 11L is constituted by a short stub using a microstrip line 16 for a low-noise amplifier matching circuit and a capacitor 17, and a power supply is provided by the matching circuit. The circuit is also used. More specifically, a low noise amplifier matching circuit microstrip line 16 and a capacitor 17 constitute an input matching circuit and a gate voltage power supply circuit of a low noise amplifier FET 31, and a low noise amplifier matching circuit microstrip line 18 and a capacitor 19. , An output matching circuit and a drain voltage power supply circuit of the low noise amplifier FET 31.

Further, in FIG. 6, a source inductor 32 for low noise is formed between the source of the matching circuit / low noise amplifier FET 31 and the ground potential. The low noise amplifier matching circuit microstrip lines 16 and 18 constituting the gate voltage power supply circuit and the drain voltage power supply circuit in the low noise amplifier 11L are:
Each is connected to the ground potential via the capacitors 17 and 19.

Further, in FIG. 6, the voltage Vgx output from the power supply for gate voltage supply (see FIG. 3) is supplied to the matching circuit via the microstrip line 16 for the low noise amplifier matching device of the gate voltage power supply circuit in the low noise amplifier 11L. In addition to being supplied to the gate of the low noise amplifier FET 31, it is also supplied to the gate of the matching device / gain amplifier FET 40 via the gain amplifier matching circuit microstrip line 22 of the gate voltage power supply circuit in the gain amplifier 21. Furthermore, the drain voltage Vd is
Microstrip line 1 for low noise amplifier matching circuit of drain voltage power supply circuit in low noise amplifier 11L
8 and the drain of the matching circuit / gain amplifier FET 40 via the gain amplifier matching circuit microstrip line 24 of the drain voltage power supply circuit in the gain amplifier 21. Supplied to

The matching circuit and low noise amplifier FET 31 in the low noise amplifier 11L and the gain amplifier 21
The gate voltage vs. drain current characteristic of the matching circuit / gain amplifier FET 40 in FIG. 4 substantially corresponds to the characteristic of the first FET 3 (solid line) and the characteristic of the second FET 4 (dashed line) in FIG. . That is, the operating point in the low-noise amplifier 11L is determined by the matching circuit / low-noise amplifier F
The operating point of the gain amplifier 21 is close to the threshold voltage of the ET 31 and the matching circuit / gain amplifier FET 40.
Is near the maximum value of the mutual conductance gm. Here, the matching circuit / FET 31 for low noise amplifier is used.
The threshold voltage of the matching circuit / low noise amplifier FET 31 and the threshold voltage of the matching circuit / gain amplifier FET 40 are set so that the operating point of the low noise amplifier 11L and the operating point of the gain amplifier 21 are aligned with respect to the gate voltage. Further, by setting the voltage Vgx output from the single power supply to the gate voltage, the voltage Vgx is reduced by the matching circuit and low noise as in the case of the first embodiment (see FIG. 5). It can be used as a common gate voltage for the amplifier FET 31 and the matching circuit / gain amplifier FET 40.

In the first specific embodiment, an MMIC constituted by a combination of two types of circuits in which a multiplier is a non-linear circuit and a gain amplifier is a linear circuit is illustrated. In a typical embodiment, an MMIC constituted by a combination of a low-noise amplifier and a gain amplifier having different operating points is illustrated, but in the present invention, an MMI constituted by another arbitrary combination is used.
Various combinations of circuits used other than C or MMIC are possible.

[0042]

As described above, according to the semiconductor device of the present invention, first, the threshold voltages of a plurality of transistors provided in a plurality of circuit portions having different operating points are set to appropriate values. By doing so, the plurality of circuits can be operated using a single power supply, so that the size and cost of the semiconductor device can be reduced.

Further, according to the semiconductor device of the present invention, secondly, since it is not necessary to provide an internal power supply circuit for adjusting the voltage output from a single power supply, unnecessary manufacturing for forming the internal power supply circuit is unnecessary. The process is saved, and an unnecessary increase in power consumption is suppressed. Further, according to the semiconductor device of the present invention, thirdly, a voltage output from a single power supply can be used as a common gate voltage for a plurality of circuit units, so that the configuration of the semiconductor integrated circuit is higher than before. Is simplified, and an unnecessary increase in power consumption is suppressed.

Furthermore, according to the semiconductor device of the present invention, fourthly, a semiconductor integrated circuit composed of a combination of a non-linear circuit and a linear circuit can be operated using a single power supply, so that low power consumption is achieved. It is possible to easily realize an MMIC or the like having stable performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle configuration of the present invention.

FIG. 2 is a graph for explaining the principle of the present invention.

FIG. 3 is a block diagram showing a configuration of a basic embodiment based on the principle of the present invention.

FIG. 4 is a graph showing gate voltage versus drain current characteristics of the two FETs of FIG.

FIG. 5 is a circuit diagram showing a configuration of a first specific example of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a second specific example of the present invention.

FIG. 7 is a block diagram showing a configuration of a semiconductor device according to a first conventional example.

FIG. 8 is a graph showing gate voltage versus drain current characteristics of a transistor used in the semiconductor device of the first conventional example.

FIG. 9 is a block diagram showing a configuration of a second conventional semiconductor device.

[Explanation of symbols]

1-1 to 1-n first circuit part to n-th circuit part 2-1 to 2-n ... first transistor to n-th transistor 3 ... first FET (field effect transistor) 4 ... 2 FET 5 Single power supply 10 Nonlinear circuit 11 Multiplier 11L Low noise amplifier 12, 14 Microstrip line for multiplier matching circuit 16, 18 Microstrip line for low noise amplifier matching circuit 20 Linear circuit 21 Gain amplifiers 22, 24: Microstrip line for gain amplifier matching circuit 30: FET for matching circuit and multiplier 31: FET for matching circuit and low noise amplifier 32: Source inductor 40: FET for matching circuit and gain amplifier 50: Gate voltage supply Power supply

 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference) 5F102 FA07 GA01 GA16 GA18 GB01 GC01 GD01 GQ01 5J067 AA04 AA41 CA36 CA92 FA15 FA16 HA09 HA12 HA29 HA33 KA29 KA47 KA68 LS12 MA08 MA21 QS04 SA13 TA01 TA02 5J092 AA09 FAA CA36 HA12 HA29 HA33 KA29 KA47 KA68 MA08 MA21 SA13 TA01 TA02 VL08

Claims (6)

[Claims] 1. A semiconductor device in which a plurality of circuit units each having a different operating point are integrated into an integrated circuit, wherein a plurality of transistors each having a different threshold voltage are provided for each of the plurality of circuit units. A threshold voltage of each of the plurality of transistors so that each of the plurality of circuit units operates at the operating point based on the applied voltage. 2. A voltage output from the single power supply is applied to each of the plurality of circuit units without providing an internal power supply circuit for adjusting a voltage output from the single power supply inside the semiconductor device. 2. The method of claim 1, wherein the apparatus is configured to supply directly.
13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein a voltage output from said single power supply is used as a gate voltage for operating each of said plurality of circuit units at said operating point. 4. A semiconductor device in which a plurality of circuit units each including at least one non-linear circuit and at least one linear circuit are integrated, and a plurality of circuit units each having a different threshold voltage for each of the plurality of circuit units. A semiconductor device, comprising: a transistor; and setting a threshold voltage of each of the plurality of transistors so that each of the plurality of circuit units operates based on a voltage output from a single power supply. 5. A voltage output from the single power supply is supplied to each of the plurality of circuit units without providing an internal power supply circuit for adjusting a voltage output from the single power supply inside the semiconductor device. 5. The method of claim 4, wherein the apparatus is configured to supply directly.
13. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 4, wherein a voltage output from said single power supply is used as a gate voltage for operating each of said plurality of circuit units at said operating point.