JP2000022002A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device containing a mask ROM at low cost in a short manufacturing term while securing the high reliability and manufacturing method thereof. SOLUTION: An n layer 11a as a component of a drain of an EEPROM memory cell 41 is simultaneously formed together with the n layer 11a of another element 42b of a mask ROM 42. This n layer 11a of the element 42b is formed on the position to be a channel region on an ordinary transistor to be junctioned with an n layer 12a normally as a conductive region. Through these procedures, the element 42b and the other element 42a are formed making use of the step of EEPROM memory cell 41 so as to realize a semiconductor device equipped with the EEPROM together with the mask ROM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a so-called FLOTOX type E.
It is suitable for application to a semiconductor device in which an EPROM and a mask ROM coexist in one chip.

[0002]

2. Description of the Related Art A read-only nonvolatile memory (RO)
M), a ROM that performs programming in a wafer processing step, a so-called mask ROM, has a simpler memory cell structure than a DRAM or the like, so that it can achieve much higher integration and larger capacity, and is suitable for mass production. And it is inexpensive.

As typical programming methods for writing data in a mask ROM, there are several methods as described below. (1) Among the transistors constituting the mask ROM, the thickness of the gate insulating film of a specific transistor is changed, and the resulting difference in threshold voltage is used as a storage state. (2) Among the transistors constituting the mask ROM, threshold voltage is changed by performing ion implantation for threshold voltage control in a channel region of a specific transistor, and a difference in the threshold voltage is used as a storage state. (3) The storage state is changed depending on whether or not a contact hole is formed in the transistor constituting the mask ROM. (4) Source of transistor constituting mask ROM /
The storage state is changed depending on whether or not the drain is connected to the upper metal wiring.

[0004]

However, the above-mentioned programming method has the following problems.

The main requirements for a highly reliable and highly demanded mask ROM include that it be inexpensive and that the process from obtaining a program to completing the mask ROM be completed in a short period of time.

First, in order to provide an inexpensive mask ROM, the chip area must be reduced. (1)
In the method of (1), one contact hole is required for two memory cells due to the necessity of a NOR type structure.
In the method (1), one contact hole is inevitably required in one memory cell due to the memory cell structure, and it is difficult for both methods to sufficiently satisfy this requirement.

Next, with respect to shortening the manufacturing period of the mask ROM, a separate gate insulating film forming step is required in the method (1). Therefore, in the method (2), programming is performed before forming the gate electrode. , It takes a long time for the subsequent steps, and it is difficult for either method to sufficiently satisfy this requirement. In the case of the method (2), an attempt has been made in recent years to shorten the process time by employing high-energy ion implantation, but an expensive apparatus is required and an inexpensive mask ROM is provided. It becomes difficult.

It is an object of the present invention to provide a semiconductor device including a mask ROM at a low cost and in a short manufacturing period while maintaining high reliability, and to provide a semiconductor device manufacturing method for realizing the same. It is to be.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising first and second semiconductor elements, wherein the first semiconductor element comprises a pair of first high-concentration diffusion layers formed by joining a first low-concentration diffusion layer to a first high-concentration diffusion layer. An impurity diffusion layer, an island-shaped first conductive film pattern-formed on a first channel region formed between the pair of first impurity diffusion layers via first and second insulating films, A second conductive film patterned on the first conductive film with a third insulating film interposed therebetween, wherein the second insulating film is formed on one of the first impurity diffusion layers. The second semiconductor element is formed to be thinner than the thickness of the first insulating film, and the second semiconductor element has a second impurity diffusion having substantially the same impurity concentration as the first low concentration diffusion layer. And a third conductive film patterned on the second impurity diffusion layer with a fourth insulating film interposed therebetween.

In one embodiment of the semiconductor device according to the present invention, the second semiconductor element further includes a pair of second high-concentration diffusion layers, and the second impurity diffusion layer forms the pair of second high-concentration diffusion layers. Are bonded together, and the second impurity diffusion layer and the second high concentration diffusion layer are of the same conductivity type.

In one embodiment of the semiconductor device according to the present invention, the semiconductor device further includes a third semiconductor element, wherein the third semiconductor element includes a pair of third impurity diffusion layers and a pair of third impurity diffusion layers. A fourth conductive film patterned on a second channel region formed between the layers via a fifth insulating film, and the first conductive film bonded to at least one of the third impurity diffusion layers; And a second low concentration diffusion layer having a lower concentration than the low concentration diffusion layer.

In one embodiment of the semiconductor device of the present invention, the first semiconductor element stores one of states in which three or more predetermined values can be taken as storage information corresponding to a threshold voltage. This is a multi-valued memory cell that can be stored.

In one embodiment of the semiconductor device according to the present invention, the semiconductor device further comprises fourth and fifth semiconductor elements, wherein the fourth semiconductor element comprises a pair of fourth impurity diffusion layers and a pair of fourth impurity diffusion layers. And a fifth conductive film patterned on a third channel region formed between the impurity diffusion layers of the first and second layers with a sixth insulating film interposed therebetween.
And a sixth conductive film patterned on a fourth channel region formed between the pair of fifth impurity diffused layers via a seventh insulating film,
At least one of the fourth impurity diffusion layers includes a third low concentration diffusion layer, and at least the fourth and fifth semiconductor elements function as a multi-valued mask ROM.

A semiconductor device according to the present invention is a semiconductor device having first and second semiconductor elements, wherein the first semiconductor element includes a first impurity diffusion layer and the first impurity diffusion layer. A first pattern formed thereon with a first insulating film interposed therebetween;
Wherein the second semiconductor element has a pair of second impurity diffusion layers and a channel region formed between the pair of second impurity diffusion layers via a second insulating film. An island-shaped second conductive film patterned; and a third impurity diffusion layer joined to one of the second impurity diffusion layers, wherein the third impurity diffusion layer is formed of the second impurity diffusion layer. The first impurity diffusion layer and the third impurity diffusion layer are formed on the semiconductor substrate below the conductive film and have a lower concentration than the impurity concentration of the second impurity diffusion layer. , Have substantially the same impurity concentration.

In one embodiment of the semiconductor device according to the present invention, a third conductive film pattern-formed on the second conductive film via a dielectric film is provided, wherein the second conductive film is floating. The third conductive film functions as a gate electrode, and functions as a control gate electrode.

In a method of manufacturing a semiconductor device according to the present invention, a step of forming an element isolation structure on a semiconductor substrate to define first and second element active regions, respectively, and a part of the first element active region Forming a mask covering the semiconductor device; introducing a low-concentration impurity into a surface region of the semiconductor substrate in the first and second device active regions using the mask; A step of forming a first low-concentration diffusion layer in a portion excluding the part, and a second low-concentration diffusion layer in the second element active region; a step of removing the mask; Forming a first insulating film on the surface of the semiconductor substrate in the first element active region and forming a second insulating film on the surface of the semiconductor substrate in the second element active region And a second step on the entire surface of the semiconductor substrate. The conductive film is formed, by processing the first conductive film, the first conductive film is patterned into an island shape on the first insulating film in the first device active region,
Pattern-forming the second conductive film in a strip shape on the second insulating film in the second element active region.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the first device active region is provided only in the first element active region.
Forming a third insulating film on the conductive film pattern of
Forming a third conductive film pattern on the third insulating film only in the first element active region; and forming a high-concentration region on the surface region of the semiconductor substrate in the first and second element active regions. Forming a first high-concentration diffusion layer in the first element active region so as to be joined to the first low-concentration diffusion layer on both sides of the third conductive film pattern; Forming a second high-concentration diffusion layer to be joined to the second low-concentration diffusion layer in the second element active region.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, when introducing the low-concentration impurity into the entire surface including the first and second element active regions, the low-concentration impurity is reduced by one. Ion implantation is performed at an implantation amount of × 10 ¹³ (1 / cm ² ) or more.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, after the first conductive film is formed in the first and second element active regions and before the high concentration impurity is introduced. Forming a mask in the first element active region, and forming an impurity having a lower concentration than the low concentration impurity on at least both sides of the second conductive film pattern in the second element active region. Forming a third low-concentration diffusion layer by introducing, and forming sidewall insulating films on both side surfaces of each of the second conductive film patterns formed in a strip shape in the second element active region. And

The storage medium of the present invention stores a program for causing a computer to function as each component of the semiconductor device.

[0021]

In the semiconductor device of the present invention, for example, a semiconductor memory in which at least one of the impurity diffusion layers is formed by joining a low-concentration diffusion layer and a high-concentration diffusion layer (here, mainly FL)
An OTOX type EEPROM is assumed. ), A mask ROM including at least two types of semiconductor elements is formed at the same time as forming the low-concentration diffusion layer and the high-concentration diffusion layer.

That is, in this mask ROM, one element in which a channel region is formed by at least a pair of high-concentration diffusion layers and a low-concentration diffusion layer are formed in a portion which normally becomes a channel region, and are brought into a conductive state as needed. And a different storage state is achieved by these two types of elements. In this case, the high-concentration diffusion layer of one element (and the high-concentration diffusion layer joined to the low-concentration diffusion layer of the other element) is formed simultaneously with the high-concentration diffusion layer of the semiconductor memory, and the low-concentration diffusion layer of the other element is formed. The concentration diffusion layer is formed simultaneously with the low concentration diffusion layer of the semiconductor memory.

As described above, in the semiconductor device of the present invention, the elements constituting the mask ROM are formed in the same process with good consistency with the semiconductor memory mixed with the mask ROM, so that the number of processes is reduced. The manufacturing period is shortened, and an inexpensive and highly integrated semiconductor device is realized.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. In this embodiment, the semiconductor device is a nonvolatile semiconductor memory that retains stored data even when the connection to a power supply is cut off and is electrically erasable, and is located above a drain in a gate oxide film. FLOTOX type EEPROM in which an extremely thin tunnel oxide film is formed in a portion, and a mask R to be programmed in a wafer processing step
An example of a semiconductor device including OM will be described. In this embodiment, a main configuration of the semiconductor device will be described together with a manufacturing method thereof. FIG. 1 is a schematic plan view showing a main configuration of an EEPROM memory cell and a mask ROM which are components of the semiconductor device according to the first embodiment. FIGS. 2 and 3 are schematic cross-sectional views showing a method of manufacturing a semiconductor device in the order of steps. 2 and 3 correspond to the cross section taken along the two-dot chain line II ′ in FIG.

First, as shown in FIG. 2A, an element isolation structure for defining various element active regions on a p-type silicon semiconductor substrate 1, here a trench type element isolation structure (STI) 2 To form

Specifically, a silicon nitride film is formed on the surface of the silicon semiconductor substrate 1, and a portion of the silicon nitride film corresponding to the element isolation region is removed. Subsequently, a groove 21 is formed in the element isolation region of the silicon semiconductor substrate 1 using the silicon nitride film (and a resist film thereon) as a mask, and a silicon oxide film 22 is formed to fill the groove 21. Thereafter, the STI 2 is formed by removing the silicon nitride film. EEPR by STI2
A region 3a to be an OM device active region and a region 3 to be a device active region of a pair of semiconductor devices constituting a mask ROM
b and 3c are respectively defined.

As the element isolation structure, a field oxide film by a so-called LOCOS method or a field shield element isolation structure by a field shield element isolation method may be formed instead of STI2. For example, EE
A region 3a to be an active region of the PROM and a mask RO
It is also conceivable to define the regions 3b and 3c to be M active regions with different device isolation structures.

Next, as shown in FIG.
Then, a resist layer 23 is formed on a portion of the silicon semiconductor substrate 1 except for a portion serving as a drain of the EEPROM, and a resist layer 24 covering the entire region 3b of the silicon semiconductor substrate 1 is formed.

Subsequently, using the resist layers 23 and 24 as a mask, an n-type impurity, for example, arsenic (As) is accelerated over the entire surface of the silicon semiconductor substrate 1 at an acceleration energy of 50 to 100 keV.
The ion implantation is performed under a relatively low concentration of about 1 × 10 ¹³ to 10 ¹⁶ / cm ² . At this time, area 3
A low-concentration junction region (n region) 11 is formed on the portion to be the drain of the EEPROM in a, and a low-concentration junction region (n region) 11 is similarly formed on the entire surface of the region 3c.

Next, after the resist layers 23 and 24 are removed by an ashing process or the like, as shown in FIG. 2C, the surfaces of the element active regions 3a, 3b and 3c are subjected to thermal oxidation to obtain a film thickness. 2
A gate oxide film 4 of about 00 ° is formed.

Subsequently, a part of the gate oxide film 3 at a portion serving as a drain of the element active region 3a is removed by wet etching to expose a part of the surface of the silicon semiconductor substrate 1. Subsequently, thermal oxidation is again performed on the exposed surface of the silicon semiconductor substrate 1 to form a tunnel oxide film 5 having a thickness of about 110 °.

Next, as shown in FIG.
By a method D, a polycrystalline silicon film 31 is deposited and formed to a thickness of about 150 nm on the entire surface including over the STI 2.

Subsequently, the polycrystalline silicon film 31 is patterned by photolithography and subsequent dry etching, and an island-shaped floating gate electrode 6 is formed in the region 3a so as to include the tunnel oxide film 5, and in the regions 3b and 3c. Form band-shaped gate electrodes 13 respectively. Here, in the region 3c, the gate electrode 13 is formed on the n region 11.

Next, as shown in FIG.
A resist layer 25 is formed to cover only the gate electrodes 13 in the regions 3b and 3c as masks.
Type impurity, for example, arsenic (As) with an acceleration energy of 30
About 70 keV, dose amount of 10 ¹² to 10 ¹⁴ / cm ²
The ion implantation is performed under the condition of a lower concentration than the low concentration ion implantation described above. At this time, a low-concentration junction region (n ⁻ region) 14 is formed on both sides of the gate electrode 13 in the region 3b. Similarly, a low-concentration junction region (n ⁻ region) is formed in the region 3c, but is absorbed by the previously formed n region 12.

Next, as shown in FIG. 3B, a silicon oxide film is deposited on the entire surface by the CVD method in a state where the resist layer 25 is present, and then the entire surface of the silicon oxide film is anisotropically etched. Then, the sidewalls 15 are formed while leaving the silicon oxide film only on the side surfaces of the gate electrodes 13 in the regions 3b and 3c.

Next, after the resist layer 25 is removed by an ashing process or the like, as shown in FIG. 3C, the O layer having a three-layer structure of a silicon oxide film, a silicon nitride film and a silicon oxide film is formed.
After the NO film 7 is formed, a polycrystalline silicon film 32 is deposited to a thickness of about 150 by the low pressure CVD method so as to cover the ONO film 7.

Here, a so-called ferroelectric film may be formed instead of the ONO film 7. When this ferroelectric film is used, platinum, a titanium compound, a tungsten compound, a ruthenium compound, or the like may be used as a material of the floating gate electrode, and a conductive film such as polycrystalline silicon is provided on the lower surface of the platinum layer. To form a two-layer structure.

Examples of the ferroelectric film include PZT (lead zirconate titanate), PLZT (lead lanthanum zirconate titanate), barium titanate, palladium titanate, palladium strontium titanate thin film, and bismuth titanate. Other substances that exhibit ferroelectricity may be used. Also, instead of the ferroelectric film, for example, tantalum oxide, Ta ₂ O ₅ BSTO or the like has a relative dielectric constant of 50
The following (?) High dielectric film may be used.

Further, a silicide film such as WSi may be formed on the polycrystalline silicon film.

Subsequently, the polycrystalline silicon film 32 and the ONO
The film 7 is patterned by photolithography and subsequent dry etching to form a pattern so as to remain only in the region 3a. At this time, in the area 3a, the ONO
A strip-shaped control gate electrode 8 facing the surface of the floating gate electrode 6 via the film 7 is formed.

Next, as shown in FIG.
With the control gate electrode 8 and the gate electrodes 13 and the sidewalls 15 as masks in the regions 3b and 3c, respectively, an n-type impurity such as arsenic (As) is accelerated at an energy of about 50 to 100 keV and a dose is 1 × 10 ¹⁵ to 10 × 10 ¹⁵ . 1
Ions are implanted over the entire surface under the condition of a relatively high concentration of about 0 ¹⁶ / cm ² . At this time, in the region 3a, a high-concentration junction region (N region) 12 is formed on both sides of the control gate electrode 8 in the regions 3b and 3b.
Similarly, the high-concentration junction regions (N regions) 12 are formed on both sides of the sidewall 15 in c. Here, one N region 12 is joined to n region 11 in region 3a, each N region 12 is joined to n ⁻ region 14 in region 3b, and is joined to n region 11 in region 3b.

Next, as shown in FIG. 3E, the silicon semiconductor substrate 1 is subjected to a predetermined heat treatment to
Each of the n region 11, the N region 12, and the n ⁻ region 14 of a to 3c is activated, and the region 3a is joined to the pair of high concentration diffusion layers (N layer) 12a and one N layer 12a on the drain side. Low concentration diffusion layer (n layer) 11a is formed,
In the region 3b, a pair of high-concentration diffusion layers (N layers) 12a and low-concentration diffusion layers (n
^- layer) 14a is formed, a pair of high-concentration diffusion layer (N layer) 12a and joined between the N layer 12a becomes conductive low concentration diffusion layer in the region 3c (n layer) that 11a is formed become.

Thereafter, an interlayer insulating film covering the control gate electrode 8 and each gate electrode 13, contact holes for various continuity, bit lines and the like (both not shown) are formed, and the EEPROM and the mask are formed. A semiconductor device including a ROM is completed.

As described above, in this embodiment, the FL
N-layer 11 of memory cell 41 of OTOX type EEPROM
a (n region 11) and a pair of N layers 12a (N region 12)
Are formed at the same time as the memory cells of the mask ROM 42 are formed. That is, this mask ROM
Reference numeral 42 denotes one element 41a in which a channel region is formed by the pair of N layers 12a and the n ⁻ layer 14a joined to each N layer 12a, and the N layer 12 that joins the pair of N layers 12a.
a, which is normally formed in a portion to be a channel region and is brought into a conductive state as needed, and a different storage state is achieved by these two types of elements.

As described above, in the semiconductor device of the present invention, the respective elements 42a and 42b constituting the mask ROM 42 are formed in the same process with good consistency with the memory cells 41 of the EEPROM mixed with the mask ROM 42. The number of steps is reduced, the manufacturing period is shortened, and an inexpensive and highly integrated semiconductor device is realized.

(Modification) Hereinafter, a modification of the present embodiment will be described. Note that members and the like corresponding to the semiconductor device of the present embodiment are denoted by the same reference numerals, and description thereof is omitted.

The semiconductor device of this modification has substantially the same configuration as the semiconductor device of the present embodiment and is manufactured through almost the same steps. For example, the technology of Japanese Patent Application Laid-Open No. 8-316341 is applied. The difference is that the information stored in the mask ROM is multi-valued. FIG. 4 is a schematic cross-sectional view showing a main configuration of a mask ROM in a semiconductor device according to a modification.

Here, the mask ROM has four types of elements 51.
To 54 are provided. The element 52 has the same structure as the element 42a of the present embodiment, and the element 54 has the same structure as the element 42b of the present embodiment. The element 51 includes only a pair of high-concentration diffusion layers (N layers) 12a as impurity diffusion layers. The element 53 includes a pair of N layers 12a and a low-concentration diffusion layer bonded to each N layer 12. It comprises a layer (n-layer) 11a.

In this case, taking advantage of the fact that the elements 51 to 54 have different threshold voltages, for example, the element 5
The storage state of element 1 can correspond to “00”, the storage state of element 52 can correspond to “01”, the storage state of element 53 can correspond to “10”, and the storage state of element 54 can correspond to “11”. As a result, a 2-bit (quaternary) storage state is realized.

In order to manufacture a semiconductor device provided with this mask ROM, as in the case of this embodiment, an EEPROM is used.
Together with 41, after first forming the n region 11 (n layer 11a), the n ⁻ region 14 (n ⁻ layer 14a) and the N region 12 (N layer 12a) may be sequentially formed.

As described above, according to the modification of the present embodiment, in addition to the above-mentioned various effects achieved by the present embodiment, a multi-valued mask ROM can be easily realized, and the storage density of each memory cell can be greatly increased. Therefore, it is possible to sufficiently meet the demand for higher integration and miniaturization.

The present invention is not limited to the embodiment and its modifications. For example, not only the mask ROM but also the EEPROM can be multi-valued. Further, the density of the n-layer or the n ⁻ layer of the mask ROM may be changed, or one of the n-layers as disclosed in JP-A-8-316341. By joining with only 12 or the like, multi-leveling of 3 bits (8 values), 4 bits (16 values) or more is possible. In order to further increase the number of levels of the mask ROM, if the storage state is n bits (2 ⁿ values, n is an integer of 2 or more), 2 bits
^It is sufficient to set ⁿ kinds of threshold voltages, that is, prepare a mask ROM composed of 2 ⁿ kinds of elements. For example, when the storage state is 3 bits (8 values), eight reference voltages (threshold voltages) are stored in the storage states “000”, “001”, and “01”.
0 "," 011 "," 100 "," 101 "," 11
0 "and" 111 ", and one of the eight storage states may be specified by a predetermined determination operation at the time of reading, where the storage information is not binary data,
For example, when the information is composed of 0, 1, and 2, the storage state is set to “0”, “1”, “2”, or “00”, “0”.
1 "," 02 "," 10 "," 11 "," 12 "," 2
It is also possible to set them to 0 "," 21 ", and" 22 ". In such a case, the former will express the storage state as three values, and the latter as nine values.

Here, for example, when the above-mentioned EEPROM is a multi-valued memory capable of storing 2-bit storage information in each memory cell, a method of writing storage information will be described. First, when writing the storage information “11”, the impurity diffusion layer serving as the drain of the memory cell is set to the ground potential, the impurity diffusion layer serving as the source is opened, and about 22 V is applied to the control gate electrode 8. At this time, electrons are injected from the drain into the floating gate electrode 6 through the tunnel oxide film 5, and the threshold voltage (V _T ) shifts in the positive direction. Then, the threshold voltage of the memory cell increases to about 4V.
This storage state is set to “11”.

Next, when writing data "10", the source is opened with the drain of the memory cell at the ground potential, and about 20 V is applied to the control gate electrode 8. At this time, electrons are injected from the drain into the floating gate electrode 6 through the tunnel oxide film 5, and the threshold voltage of the memory cell becomes about 3V. This storage state is set to “10”.

Next, when writing data "01", the source is opened with the drain of the memory cell at the ground potential, and about 18 V is applied to the control gate electrode 8. At this time, electrons are injected from the drain into the floating gate electrode 6 through the tunnel oxide film 5, and the threshold voltage of the memory cell becomes about 2V. This storage state is set to “01”.

Next, when writing data "00", about 10 V is applied to the drain of the memory cell, the source is opened, and the control gate electrode 8 is set to the ground potential. At this time, the electrons injected into the floating gate electrode 6 are extracted from the drain, and the threshold voltage of the memory cell becomes about 1V. This storage state is set to “00”.

Next, in the case where the above-mentioned EEPROM is a multi-valued memory capable of storing 2-bit storage information in each memory cell, an example of each step of the reading method will be described below with reference to FIG. First, it is determined whether the upper bit of the storage information stored in the memory cell is “0” or “1”. In this case, about 5 V is applied to the source and drain and the control gate electrode 8 (Step S1),
The drain current is detected by a sense amplifier and the threshold voltage V
The magnitude relationship between _T and the threshold voltage of the comparison transistor Tr1 is determined (step S2). At this time, if the threshold voltage V _T is larger than the threshold voltage of the transistor Tr1, the upper bits are being output is determined to be "1" (step S3), and current of the transistor Tr1 is small conversely In this case, the upper bit is determined to be "0" and output (step S4).

[0058] Here, compared with the current if the threshold voltage V _T is larger than the threshold voltage of the transistor Tr1, a transistor Tr2 the similar read operation, flowing through the current and the transistor Tr2 flowing through the memory cell (Step S5), the threshold voltage _VT is
If it is smaller than the threshold voltage of r1, a similar read operation is determined using the transistor Tr3 (step S6).

[0059] In step S5, if the threshold voltage V _T in the above read operation is larger than the threshold voltage of the transistor Tr2, the lower bits of the stored information stored in the memory cell If it is "1" It is determined (step S7), and the data is read from the memory cell. At this time, the stored information is “11”. On the other hand, in step S5,
If the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr2, the lower bits of the stored information stored in the memory cell is determined to be "0" (step S
8) Read from the memory cell. At this time, the stored information is “10”.

In step S6, the threshold voltage of the transistor Tr3 is compared with the threshold voltage of the transistor Tr3. If the threshold voltage of the memory cell is large, the lower bit of the storage information stored in the memory cell is "1". Is determined (step S9), and the data is read from the memory cell. At this time,
The storage information is “01”. On the other hand, in step S6, the threshold voltage V _T is smaller than the threshold voltage of the transistor Tr3, the lower bits of the stored information stored in the memory cell is determined to be "0" (step S10) , From the memory cell. At this time, the stored information is “00”.

The program code itself for operating various devices and means for supplying the program code to a computer, such as a computer, so as to realize the functions of the semiconductor device described in the present embodiment and its modifications. A storage medium storing such a program code belongs to the category of the present invention.

In this case, the program code stored in the storage medium is read out by a predetermined storage / reproduction device, and the EEPROM operates. As a storage medium for storing such a program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, and the like can be used.

When the computer executes the supplied program code, not only the functions of the respective embodiments are realized, but also the OS (operating system) or other application running on the computer in the program code. Such a program code is also included in the present invention when the functions of each embodiment are realized in cooperation with software or the like.

Further, after the supplied program code is stored in a memory provided in a function expansion board of a computer or a function expansion unit connected to the computer, the function expansion board or the function expansion unit is specified based on the instruction of the program code. The present invention also includes a system in which a CPU or the like included in the system performs part or all of actual processing, and the processing realizes the functions of the embodiments.

[0065]

According to the present invention, while maintaining high reliability,
It is possible to provide a semiconductor device including a mask ROM at low cost and in a short manufacturing period, and to provide a semiconductor device manufacturing method for realizing the same.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a main configuration of an EEPROM memory cell and a mask ROM which are components of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 3 is a schematic cross-sectional view showing a manufacturing method of the semiconductor device according to the embodiment of the present invention in the order of steps, following FIG. 2;

FIG. 4 is a schematic plan view showing a main configuration of a mask ROM as a component of a semiconductor device in a modification of the embodiment of the present invention.

FIG. 5 is a flowchart illustrating a read operation when the EEPROM, which is a component of the semiconductor device, is multi-valued (binarized) in the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Trench type element isolation structure (STI) 3a-3c Element active region 4 Gate oxide film 5 Tunnel oxide film 6 Floating gate electrode 7 ONO film 8 Control gate electrode 11 Low concentration diffusion region (n region) 11a Low concentration Diffusion layer (n layer) 12 High concentration diffusion region (N region) 12a High concentration diffusion layer (N layer) 13 Gate electrode 14 Low concentration diffusion region (n ⁻ region) 14a Low concentration diffusion layer (n ⁻ layer) 15 Side wall Reference Signs List 16 floating gate electrode 17 ONO film 18 control gate electrode 21 groove 22 silicon oxide film 23-25 resist layer 31, 32 polycrystalline silicon film 41 EEPROM memory cell 42 mask ROM 42a one element 42b the other element 51-54 multi-valued mask ROM elements

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 F-term (Reference) 5F001 AA01 AA09 AA21 AA61 AB02 AD17 AD60 AD62 AE02 AE03 AE08 AF20 AG22 AG40 5F083 CR02 EP02 EP22 EP42 EP55 EP63 EP68 EP72 ER05 ER15 ER21 FR07 GA28 JA04 JA06 JA13 JA14 JA15 JA38 JA39 JA43 JA53 ZA05 ZA06 ZA14 ZA21

Claims (12)

[Claims] 1. A semiconductor device comprising first and second semiconductor elements, wherein the first semiconductor element is formed by joining a first high-concentration diffusion layer to a first low-concentration diffusion layer. A pair of first impurity diffusion layers, and a first impurity diffusion layer formed between the pair of first impurity diffusion layers.
An island-like first conductive film patterned on the channel region via first and second insulating films, and a pattern formed on the first conductive film via a third insulating film. A second conductive film, wherein the second insulating film has one of the first conductive films.
The second semiconductor element is formed on the impurity diffusion layer having a thickness smaller than the thickness of the first insulating film. The second semiconductor element has substantially the same impurity as the first low concentration diffusion layer. A semiconductor device, comprising: a second impurity diffusion layer having a concentration; and a third conductive film pattern-formed on the second impurity diffusion layer via a fourth insulating film. 2. The second semiconductor element further includes a pair of second high-concentration diffusion layers, wherein the pair of second high-concentration diffusion layers are joined by the second impurity diffusion layer. 2. The semiconductor device according to claim 1, wherein the second impurity diffusion layer and the second high concentration diffusion layer have the same conductivity type. 3. The semiconductor device according to claim 2, further comprising a third semiconductor element,
A fourth semiconductor element formed by patterning a pair of third impurity diffusion layers and a second channel region formed between the pair of third impurity diffusion layers via a fifth insulating film;
And a second low-concentration diffusion layer having a lower concentration than the first low-concentration diffusion layer bonded to at least one of the third impurity diffusion layers. The semiconductor device according to claim 1. 4. The multi-level memory according to claim 1, wherein the first semiconductor element is capable of storing one of states in which a predetermined value equal to or more than three values can be taken as storage information corresponding to a threshold voltage. The semiconductor device according to claim 1, wherein the semiconductor device is a cell. 5. The semiconductor device according to claim 1, further comprising a fourth semiconductor element and a fifth semiconductor element, wherein the fourth semiconductor element includes a pair of fourth impurity diffusion layers and a third impurity layer formed between the pair of fourth impurity diffusion layers.
A fifth conductive film pattern-formed on a channel region of the first through a sixth insulating film, wherein the fifth semiconductor element comprises a pair of fifth impurity diffusion layers, and a pair of fifth impurity diffusion layers. Fourth layer formed between impurity diffusion layers
A sixth conductive film patterned on a channel region of the second conductive film with a seventh insulating film interposed therebetween, and at least one of the fourth impurity diffusion layers includes a third low-concentration diffusion layer; 5. The semiconductor device according to claim 1, wherein the fourth and fifth semiconductor elements function as a multi-valued mask ROM.
The semiconductor device according to claim 1. 6. A semiconductor device comprising first and second semiconductor elements, wherein the first semiconductor element has a first impurity diffusion layer and a first impurity diffusion layer on the first impurity diffusion layer. A first conductive film patterned through an insulating film, wherein the second semiconductor element includes a pair of second impurity diffusion layers and a channel formed between the pair of second impurity diffusion layers. An island-shaped second conductive film pattern-formed on a region via a second insulating film, and a third impurity diffusion layer joined to one of the second impurity diffusion layers. The third impurity diffusion layer is formed on the semiconductor substrate below the second conductive film, and is formed at a lower concentration than the impurity concentration of the second impurity diffusion layer. The layer and the third impurity diffusion layer have substantially the same impurity concentration. The semiconductor device according to symptoms. 7. A semiconductor device comprising: a third conductive film pattern-formed on the second conductive film via a dielectric film; wherein the second conductive film functions as a floating gate electrode; The semiconductor device according to claim 6, wherein the conductive film functions as a control gate electrode. 8. A step of forming an element isolation structure on a semiconductor substrate to define first and second element active regions, respectively, and a step of forming a mask covering a part of the first element active region. Using the mask to introduce a low-concentration impurity into the surface region of the semiconductor substrate in the first and second device active regions, Forming a first low-concentration diffusion layer in the second element active region and a second low-concentration diffusion layer in the second element active region; removing the mask; and performing thermal oxidation on the semiconductor substrate. Forming a first insulating film on the surface of the semiconductor substrate in the first element active region and forming a second insulating film on the surface of the semiconductor substrate in the second element active region; Forming a first conductive film on the entire surface; Processing a conductive film, patterning the first conductive film in an island shape on the first insulating film in the first element active region, and forming the second insulating film in the second element active region; Forming a pattern of the second conductive film in a strip shape on the film. 9. A step of forming a third insulating film on the first conductive film pattern only in the first element active region, and forming the third insulating film only in the first element active region. Forming a third conductive film pattern on the film; introducing a high-concentration impurity into a surface region of the semiconductor substrate in the first and second device active regions to form a third conductive film pattern in the first device active region; A first high-concentration diffusion layer is formed so as to be joined to the first low-concentration diffusion layer on both sides of the third conductive film pattern, and the second low-concentration diffusion layer is formed in the second element active region. The method of manufacturing a semiconductor device according to claim 8, further comprising: forming a second high-concentration diffusion layer to be joined to the layer. 10. When the low-concentration impurity is introduced into the entire surface including the first and second element active regions, the low-concentration impurity is implanted in an amount of 1 × 10 ¹³ (1 / cm ² ) or more. The method for manufacturing a semiconductor device according to claim 8, wherein the ion implantation is performed. 11. After forming the first conductive film in the first and second element active regions and before introducing the high-concentration impurities, a mask is formed in the first element active region. Then, at least on both sides of the second conductive film pattern in the second element active region, a third low-concentration diffusion layer is formed by introducing a further lower-concentration impurity than the low-concentration impurity. 9. The method according to claim 8, further comprising: a step of forming sidewall insulating films on both side surfaces of each of the second conductive film patterns formed in a strip shape in the second element active region.
11. The method for manufacturing a semiconductor device according to any one of items 10 to 10. 12. A storage medium storing a program for causing a computer to function as each component of the semiconductor device according to claim 1. Description: