JP2000011027A - Method and device for supporting design - Google Patents

Abstract

PROBLEM TO BE SOLVED: To examine a reliability without dividing plural examination objects into plural times by setting a synthetic limit value being common to first and second examination factors based on first and second limit values and examining the reliability of a circuit which is expressed by means of a logical level through the use of the synthetic limit value. SOLUTION: An electromigration reference value and a hot carrier effect reference value are respectively decided (S1 and S2). The frequency limit value E of an electromigration is generated (S3). Frequency limit values E in respective waveform roundings and respective load capacities are calculated and stored as the shape of a frequency limit table E (S5). The frequency limit value H of a hot carrier effect is generated (S4). The generated frequency limit value H is also stored as the frequency limit table H (S6). The frequency limit tables E and H are synthesized (S7) and a synthetic frequency limit table M is generated (S8). The reliability is examined based on the table M.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a design support method and apparatus using a computer, and more particularly to a design support method and apparatus for verifying reliability in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, this kind of design support method is widely used for designing and synthesizing a semiconductor integrated circuit, and further verifies the reliability of the semiconductor integrated circuit from design information of the semiconductor integrated circuit. It is also used for

[0003] Methods of verifying the reliability of a semiconductor integrated circuit include a case where the electromigration of the semiconductor integrated circuit is to be verified and a case where the hot carrier effect of the semiconductor integrated circuit is to be verified. is there. Here, electromigration is a phenomenon that occurs when a current having a high current density is applied to a thin film conductor. This electromigration causes cavities to be generated in a wiring pattern, resulting in a disconnection or a short circuit between patterns. Etc. occur. On the other hand, the hot carrier effect is a phenomenon in which hot carriers are injected and trapped in an oxide film when a high electric field is applied. When the hot carrier effect occurs, a change in the threshold voltage of a transistor or a change in conductance is caused. Causes deterioration.

Therefore, these electromigration and hot carrier effects must be strictly checked and verified when designing a semiconductor integrated circuit.

Conventionally, as a method of detecting electromigration and detecting a portion where the electromigration may be a problem, Japanese Patent Application Laid-Open No.
There is a verification method described in Japanese Unexamined Patent Publication No. 293765 (hereinafter, referred to as Document 1). In the verification method described in Document 1, it is verified whether or not a peak current density of a current flowing through a verification target such as a wiring satisfies a limit value of a peak current density which is a design specification of electromigration.

On the other hand, as methods for verifying the hot carrier effect, Japanese Patent Application Laid-Open No. 9-292436 (hereinafter referred to as Document 2) and Japanese Patent Application Laid-Open No. 9-330344 (hereinafter referred to as Document 3). There is a method described in.
Among them, Literature 2 discloses a method of estimating transistor deterioration due to hot carriers and guaranteeing timing reliability until a desired life, and Literature 3 calculates output load of each cell. A method of calculating the transistor life due to hot carriers of each cell based on the calculated output load and the reliability information of each cell, comparing the calculated lifetime with a reference value, and verifying the reliability of each cell is disclosed. ing.

[0007]

Conventionally, the verification of the electromigration reference value and the verification of the hot carrier effect reference value have been performed separately. Specifically, usually, the electromigration reference value is a limit value of a current value flowing through the wiring,
The reference value of the hot carrier effect is given by the limit value of the amount of deterioration in the gate oxide film of the N-channel transistor.

The electromigration reference value and the hot carrier effect reference value relate to different targets, and have different values. Therefore, conventionally, these reference values are each converted into a completely different type of limit value parameter,
At present, verification is performed by completely different reliability verification methods.

Therefore, in the conventional verification method,
The electromigration reference value and the hot carrier effect reference value must be separately verified in two separate steps. Further, since two verification results are obtained, it is necessary to refer to each of the two verification results when a verification error is fed back to the design.

More specifically, both design criteria indicate completely different limit values. However, if any one of them has a verification error, it is necessary to correct the circuit. Performing verification twice is a major drawback in design work.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to provide a design support method and apparatus which can verify reliability without dividing a plurality of verification targets into a plurality of times.

Another object of the present invention is to provide a logic synthesis tool capable of simultaneously verifying a plurality of verification targets.

According to one aspect of the present invention, in a design support method for verifying the reliability of a circuit represented by a logic level using a computer, a first and a second method for verifying the reliability of the circuit are provided. Selecting a verification factor; setting first and second limit values associated with the first and second verification factors, respectively;
Setting a combined limit common to the first and second verification factors based on the second limit and a second limit, and using the combined limit to determine the reliability of the circuit represented by the logic level. And a verifying step.

According to another aspect of the present invention, in a logic synthesis tool for synthesizing a circuit represented by a logic level using a computer, a first and a second factors related to predetermined first and second factors are provided. A table holding the limit values of 2 and a table holding the combined limit values obtained from the first and second limit values, and verifying the circuit represented by the logic level using the combined limit values. And a means for synthesizing.

According to still another aspect of the present invention, in a layout tool for inserting a wiring and a buffer, a table storing limit values relating to different factors and a combined limit value calculated based on the different limit values are stored. A layout tool is provided, comprising: the stored table; and means for inserting the wiring and the buffer based on the synthesis limit value.

According to another aspect of the present invention, in a storage medium used for designing and verifying a circuit expressed at a logic level, a table relating to a plurality of factors used for the design and verification is provided. And a means for storing a procedure for synthesizing the plurality of factors.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Referring to FIG. 1, a design support method according to an embodiment of the present invention, that is, a verification method will be described. Here, first, the verification method according to the present invention is used as a reliability verification tool. Further, the reliability tool according to the present invention may be incorporated in a part of a logic synthesis tool in the form of a subroutine. When incorporated in a logic synthesis tool, logic synthesis is performed from a netlist described in RTL (register transfer level), and a gate level netlist is created. Then, various constraints are added to verify the logic synthesis result. In doing so, the verification method of the present invention will be used. Specifically, in the logic synthesis tool, based on the result of adding this constraint,
A report file is created, and the logic is re-synthesized or the load is adjusted in accordance with the report file.

Further, the verification method according to the present invention is characterized in that the DRC
(Design rule check), a layout tool, and the like can be used in the same manner, and in any case, it is executed as a subroutine in a part of a series of logic synthesis processing and the like.

In the present invention, the electromigration and the hot carrier effect are selected as verification targets for defining the constraint conditions. These electron migration and hot carrier effects are used to verify the lifetime of a logic-synthesized circuit, and at the time of verification, whether the logic-synthesized circuit violates these reference values, that is, It is verified whether the life corresponding to the reference value can be guaranteed.

Next, in order to facilitate understanding of the present invention,
The relationship between electromigration and hot carrier effects and aging of elements such as MOS transistors will be described. Aging of the device due to electromigration and the hot carrier effect appears as deterioration of the frequency characteristic with respect to the load, and the deterioration of the frequency is caused by the rounding of the rising and falling waveforms of the signal waveform given to the device. It is determined. In other words, the rise and fall of the signal waveform become gradual due to aging, thereby deteriorating the frequency characteristics.

Next, in order to facilitate understanding of the present invention,
The electromigration and hot carrier effect will be described. Electromigration is a phenomenon in which a wiring is deteriorated by a current flowing through the wiring to increase resistance or break. What is the hot carrier effect?
This is a phenomenon in which the element is deteriorated by a current flowing through the element such as a MOS transistor and the frequency characteristics are deteriorated. The current flowing through these wirings and elements is determined by the rise and fall of the signal waveform applied to the element, the rounding of the waveform, the load capacitance at the output of the element, and the frequency of these input / output signals.

For the above-described electromigration and hot carrier effect, first, an electron migration reference value and a hot carrier effect reference value are set. These reference values indicate limit values that can achieve desired characteristics even after aging. Here, the electron migration reference value depends on a limit value of a current value flowing through the wiring, and is represented by a time function determined by a current generated by the electromigration. In this case, the current value that determines the electromigration reference value may be the average current density of the current flowing through the wiring or the like, or may be the peak current density.

In this embodiment, the electromigration reference value is calculated by the following equation (1) and represents the time (t50) until a defective product is obtained. It is verified whether it is longer than the electromigration reference value.

[0025]

Equation 4] ^{(t50 =) ApJ n e Ea} / KT <T life (1) where, in the formula (1), Ap and n is a constant depending on the process, J current density of wiring (A / m ²⁾ And J =
I / Sa, K is Boltzmann's constant, T is the absolute temperature, I is the current (A) of the wiring, and Sa is the cross-sectional area (m ² ) of the wiring, and Ea is the activation energy;
And T _life is, for example, a life of 40 years or the like. As is clear from equation (1), the electromigration reference value depends on the current density J of the current flowing through the wiring, and if the other conditions are constant, the electromigration reference value is set smaller as the current density J increases. Will be.

On the other hand, the reference value of the hot carrier effect is based on the amount of deterioration of the gate oxide film in the transistor constituting the cell in consideration of the fact that the cell delay changes due to the characteristic deterioration due to hot carrier injection into the oxide film of the cell. Is represented by the limit value. In this case, the amount of deterioration of the gate oxide film corresponds to the cell life for hot carriers.

In the embodiment of the present invention, the hot carrier effect reference value is given by the following equation (2).

[0028]

Equation 5] ^{(Cmax =) α1xS β1 xW>} C (2) where, S is the normalized stress amount, [alpha] 1, .beta.1 is a constant depending on the process and primitive circuitry and waveform rounding, W is N-channel The width of the transistor (μm), and C is the load capacitance (pF).

As is clear from the equation (2), the hot carrier effect reference value is represented by a capacitance value corresponding to the size and signal waveform of each transistor, and the capacitance value (C) of the target transistor is determined by the capacitance value (C). It is verified whether the value is smaller than the hot carrier effect reference value. The above-mentioned normalized stress amount S is given by the following equation (3).

[0030]

The [6] _{S = (1 / τ α)} x (1 / f) x (α 2) x (e β2xT) (3) where tau _alpha, product applications, or, depending on the reliability assurance level Is a constant (time), and f is the operating frequency (H
z), α ₂ and β ₂ are process-dependent constants and T
Is the absolute temperature. As is clear from the above equation (2), in this case, as described above, the hot carrier effect reference value is defined by the capacitance.

Returning to FIG. 1, when the electromigration reference value and the hot carrier effect reference value are determined in steps 1 and 2, respectively, step 1 is replaced by step 3
, While step 2 proceeds to step 4.
In these steps 3 and 4, the circuit represented by the logic level and the circuit information level is divided into a plurality of logic blocks. In the following description, in order to distinguish between processes relating to the electromigration and the hot carrier effect, the processes and data relating to the electromigration are denoted by reference symbol E, while the processes and data relating to the hot carrier effect are denoted by reference symbol H. Shall be.

In step 3 relating to electromigration, the input and output signals of the unit frequency are changed with reference to the electromigration reference value shown in equation (1) while changing the input waveform rounding and output load capacitance of each logical block. The frequency limit value E relating to electromigration that satisfies the electromigration reference value is generated by calculating backward from the ratio with the reference value at the time. The frequency limit value E relating to the electromigration depends on the waveform rounding at the rising and falling of the signal waveform and the load capacity. The waveform rounding according to this embodiment is represented by a time Tr when the input signal transitions from a low level to a high level, or a time Tf when the input signal transitions from a high level to a low level. Here, taking an inverter constituted by a CMOS as an example, a transient current flows through one of the transistors constituting the CMOS during the above-mentioned rising and falling times,
This transient current increases as the time Tr and Tf increase, and as a result, the electromigration reference value may not be satisfied.

Next, considering the relationship between the load capacity Cload and the frequency, the larger the load capacity is, the lower the responsive maximum frequency is, and the smaller the load capacity is, the higher the maximum frequency is. For example, when the load capacitance Cload is about 0.1 pF, the maximum frequency is about 600 MHz. On the other hand, when the load capacitance Cload is increased to about 1 pF, the maximum frequency is reduced to about 100 MHz.

Considering the relationship between the waveform rounding and the frequency, and the relationship between the load capacitance Cload and the frequency, each waveform rounding (nanosecond) and the frequency limit value E at each load capacitance (pF) are calculated as follows. , And are sequentially stored in the form of a table as shown in FIG. 2 (hereinafter referred to as a frequency limit table E) (step 5). Frequency limit table E
As is clear from FIG. 5, the frequency limit value E is small (for example, 50 p) when the waveform rounding is large (for example, 10 nanoseconds) and the load capacitance is large (for example, 1.0 pF).
MHz), on the other hand, the waveform rounding is small (for example, 0.1
Nanoseconds) and a small load capacity (for example, 0.01
pF), the frequency limit value E is large (for example, 500
MHz).

On the other hand, in the step 4 relating to the hot carrier effect, the hot carrier effect reference value obtained by the equation 2 is taken into consideration, provided that the hot carrier effect does not exceed the hot carrier effect reference value represented by the capacitance value. A frequency limit value H related to the hot carrier effect is generated. Also in this case, while changing the operating frequency of each pin using the relationship between the input waveform rounding and the maximum frequency of each logic block and the relationship between the output load capacitance and the maximum frequency, each waveform rounding and each The frequency limit value H at the load capacity is calculated.

The generated frequency limit value H also depends on the waveform rounding and the load capacity.
As shown in FIG. 3, the relationship between the load capacity and the frequency limit value H is a table (hereinafter, referred to as a frequency limit table H).
And store it in a memory (step 6).

As is clear from the frequency limit table H shown in FIG. 3, the frequency limit value H also has a large waveform distortion (for example, 10 nanoseconds) like the frequency limit value E.
When the load capacity is large (for example, 1.0 pF),
When the waveform rounding is small (for example, 0.1 nanosecond) and the load capacitance is small (for example, 0.01 pF), the frequency is, for example, 300 MHz.
It becomes big.

2 and 3, both frequency limit values E and H are calculated with the waveform rounding and the load capacitance fixed at a specific value.
In addition, the change range of the load capacity is determined by using both frequency limit tables E
And H. However, it is understood that the frequency limit values E and H determined by the waveform rounding and the load capacity are different between the two tables.

However, if the frequency limit values E and H shown in both frequency tables E and H are stricter, that is, the smaller value, the conditions for both the electromigration and the hot carrier effect are satisfied. It can be seen that it can be used as a satisfactory frequency limit value.

In consideration of this, in the embodiment of the present invention shown in FIG. 1, as shown in step 7, the frequency limiting tables E and H are combined, and the combined frequency limiting tables as shown in FIG. A table M is created (step 8). Specifically, the composite frequency restriction table M is created by taking the smaller one of the frequency restriction values shown in the frequency restriction tables E and H. That is, when the waveform is rounded (10 nanoseconds) and the load capacitance (1.0 pF), the frequency limit value is set to 50 MHz in the frequency limit table E.
z, and the waveform limit (10 nanoseconds) and the load capacitance (0.01 pF), the frequency limit value (100 MHz) of the frequency limit table H is used. Similarly, when the waveform is rounded (1.0 nanosecond) and the load capacitance is (0.1 pF) and (0.01 pF), the frequency limit values (150 MHz) and (200 MHz) of the frequency limit table H are similarly set. Synthetic frequency limit table M
Value.

As described above, the reliability of each logic block is verified in the subsequent steps based on the synthesized frequency restriction table M obtained in step 8.

At the time of the above-described verification, the logic level circuit information is taken out of the memory for each logic block or net (step 9). Here, the circuit information is information representing a logic circuit based on connection relations of transistors, resistors, capacitors, and the like, model parameters, and the like in a semiconductor integrated circuit to be verified.

Next, a frequency limit value is obtained from the input waveform rounding and the output load capacity in each logic block based on the synthesized frequency limit table M obtained in step 8, and the actual frequency limit value obtained by simulation or the like is obtained. The frequency is
It is verified in step 10 whether the above-mentioned frequency limit value is satisfied. The verification result of step 10 is output in step 11.

The verification step in step 10 will be described in more detail. In verification step 10, the frequency in each logical block in which the waveform rounding and the load capacity are determined exceeds the frequency limit value shown in the frequency limit table M. Is verified. As a result of the verification, if the frequency limit is exceeded, it is determined that the circuit information of the logical block satisfies the conditions regarding electromigration and hot carriers. On the other hand,
If the frequency is equal to or less than the frequency limit value, a report file relating to the logical block is created, and logical synthesis and the like are performed again.

Next, the electromigration limit value and the hot carrier effect limit value used in the above embodiment will be described more specifically.

First, the electromigration limit value is calculated based on the limit value (Imax) of the current value of the wiring. First, the current value (I) flowing through the wiring inside and outside the logic block depends on the input waveform rounding (Trf), output load capacitance (Cload), and operating frequency (Freq) of each pin of the logic block.
It depends on. The limit value of the current value depends on the input waveform rounding (Trf), output load capacity (Cload), and operating frequency (Freq).
Can be expressed by a function Fe relating to electromigration in Expression (4).

[0047]

Imax> I = Fe (Trf, Cload, Freq) (4) Actually, based on the equation (4), a limit value of a current value with respect to each input waveform rounding, a load capacity, and a frequency is obtained. ,
Subsequently, an upper limit value of a frequency that satisfies the limit value of the current value is calculated. By obtaining the calculated upper limit value of frequency for each pin of each logic block and for each rounding of waveform and load capacitance, a two-dimensional table of rounding of input waveform and output load capacitance is obtained as shown in FIG. Can be described as the frequency limit value of Although FIG. 2 illustrates a two-dimensional table, a one-dimensional table representing the relationship between the waveform rounding (Trf) and the maximum frequency or a one-dimensional table representing the relationship between the load capacity and the maximum frequency is used. May be. Note that various expressions can be used as the specific function Fe relating to electromigration shown in Expression (4).

On the other hand, the frequency limit value representing the hot carrier effect can be calculated, for example, from the deterioration amount of the gate oxide film of the N-channel transistor described above. In general, the amount of deterioration of the gate oxide film is converted to another limit value by various approximations and used.
The integration time (Tmid) at which the potential becomes GND intermediate potential and the drain current (Id
A method of approximating the amount of deterioration from rain) is adopted. In this case, the deterioration amount related to the hot carrier can be expressed as in the following Expression 5 using the function Fh for obtaining the standard stress amount S.

[0049]

Smax> S = Fh (Tmid, Idrain) (5) Specifically, Fh ′ is obtained by dividing the ratio of the stress time by the AC bias to the stress time by the DC bias by the frequency. Can be calculated.

Further, the integration time (Tmid) is changed to the waveform rounding (Trf).
And frequency (Freq), and the drain current (Id
rain) can be expressed by the waveform rounding (Trf), the load capacity (Cload), and the frequency, so that equation (5) can be rewritten as equation (6).

[0051]

Smax> S = Fh ′ (Trf, Cload, Freq) (6) In any case, each waveform rounding Trf, each load capacitance Cload, and each frequency calculated using the equation (6) Freq
From the limit value of the standardized stress amount S obtained for, the limit value of the frequency satisfying each standardized stress amount S can be obtained.

Therefore, regarding the hot carrier effect,
A limit value of the deterioration amount of the gate oxide film can be obtained, and a frequency limit value for the input waveform rounding and the output load capacitance can be obtained in a one-dimensional or two-dimensional table for each pin of each logic block.

Furthermore, if the worst value (minimum value) of both tables is obtained by using the above-described electromigration frequency restriction table and hot carrier effect frequency restriction table, the reliability of both tables is simultaneously verified. Frequency restriction table can be created.

Although the hot carriers to be verified in the above-described embodiment have been described using an N-channel transistor as an example, they are actually hot electrons. However, in the case of a P-channel transistor, hot carriers are used. Needless to say, it is a hall. Therefore, when transistors of both channels coexist, it is necessary to prepare a table for both.

As described above, the design support method according to the present invention is used not only when it is used as a reliability verification tool, but also when it is used in a logic synthesis tool, or when the electromigration and hot carrier effect according to the present invention are used. Based on the verification result by the simultaneous verification method, the present invention can be applied to a case where a subroutine is used in a layout tool for wiring and buffer insertion. Also, the verification method of the present invention for simultaneously verifying the electromigration and the hot carrier effect may be used by being incorporated in a DRC (design rule check) flow or a logic synthesis tool.

As described above, in the present invention, the frequency limit value table E is obtained from the electromigration reference value.
On the other hand, a frequency limit table H is generated from the hot carrier effect reference value, and a frequency limit table M is synthesized so as to take the minimum value of these two frequency tables.
The reliability of the logic level circuit can be verified using the obtained frequency limit table M. Further, the above-described table and the procedure for processing the data of the table and verifying the reliability may be stored in a recording medium.

In the above-described embodiment, only the electromigration and the hot carrier having the frequency limit value as the common limit value have been described as the verification targets. However, the present invention defines the limit value and the limit value. The same applies if the factors are common to the test, and
The number of objects to be verified is not limited to two, and the present invention can be similarly applied to the case where more objects are simultaneously verified.

[0058]

According to the present invention, the frequency limit value table E obtained from the electromigration reference value and the frequency limit value table H obtained from the hot carrier effect reference value are used.
Is generated in advance, a reference value for both the electromigration and the hot carrier effect on the logic level circuit can be verified at a time. As described above, according to the present invention, the verification time can be reduced by performing the verification on a plurality of verification targets at once. In addition, since there is only one verification method, the verification result can be simplified, and the verification result can be easily fed back to the design.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a design support method according to an embodiment of the present invention.

FIG. 2 is a diagram showing a frequency limit table for electromigration used in FIG. 1;

FIG. 3 is a diagram showing a frequency limit table for hot carriers used in FIG. 1;

FIG. 4 is a diagram showing a frequency limit table synthesized using FIGS. 2 and 3;

[Explanation of symbols]

1 Step for obtaining an electromigration reference value 2 Step for obtaining a hot carrier effect reference value 3 Step for generating a frequency limit value (E) 4 Step for generating a frequency limit value (H) 5 Step for creating a frequency limit table (E) 6 Frequency limit table ( H) creation step 7 Frequency restriction table synthesis step 8 Synthetic frequency restriction table 9 Reading logic level circuit information 10 Reliability verification step 11 Verification result output step

Claims (21)

[Claims] 1. A design support method for verifying the reliability of a circuit represented by a logic level using a computer, the method comprising: selecting first and second verification factors for verifying the reliability of the circuit. Setting first and second limit values associated with the first and second verification factors, respectively; and determining first and second verification factors based on the first and second limit values. A design support method, comprising: setting a common synthesis limit value; and verifying the reliability of a circuit represented by the logic level using the synthesis limit value. 2. The design support method according to claim 1, wherein said first and second verification factors are an electromigration and a hot carrier effect, respectively. 3. The design support method according to claim 2, wherein the first and second limit values are an electromigration limit value and a hot carrier effect limit value, respectively. Method. 4. The design support method according to claim 3, wherein the first limit value is a first and second frequency limit value calculated for the electromigration and the hot carrier effect, respectively. A design support method characterized by the following. 5. The design support method according to claim 4, wherein said first and second frequency limit values are dependent on an input waveform rounding and an output load capacity. 6. The design support method according to claim 5, wherein the step of verifying the reliability of the circuit includes a step of simultaneously verifying electromigration and a hot carrier effect according to the synthesis limit value. 7. A logic synthesis tool for synthesizing a circuit represented by a logic level using a computer, wherein a first and second factors related to predetermined first and second factors are provided.
A table holding the limit values of the above, a table holding the combined limit values obtained from the first and second limit values, and using the combined limit values to verify the circuit represented by the logical level. A logic synthesizing tool comprising means for synthesizing. 8. The logic synthesis tool according to claim 7, wherein the first and second factors are an electromigration and a hot carrier effect, respectively. 9. The logic synthesis tool according to claim 8, wherein the first and second limit values are an electromigration reference value and a hot carrier effect limit value, respectively. 10. The logic according to claim 9, wherein the first limit value is a first and second frequency limit value set for the electromigration and the hot carrier effect, respectively. Synthesis tool. 11. The logic according to claim 10, wherein said first and second frequency limit values are determined using a table representing a relationship between an input waveform rounding and an output load capacity. Synthesis tool. 12. The circuit according to claim 11, wherein the means for synthesizing the circuit verifies the electromigration and the hot carrier effect simultaneously using the synthesis limit value, and executes the circuit of the logic level based on the verification result. A logic synthesis tool comprising means for synthesizing. 13. A layout tool that includes layout data for inserting wiring and a buffer, and performs layout based on the data, a table storing limit values relating to mutually different factors, and calculation based on the mutually different limit values. A layout tool comprising: a table storing a synthesis limit value; and means for verifying layout data based on the synthesis limit value, and inserting the wiring and the buffer based on the verification result. 14. The design support method according to claim 1, wherein the synthesis limit value is a limit value representing a strict condition among the plurality of limit values. 15. The method according to claim 1, further comprising the step of calculating reference values for first and second verification factors, wherein the first and second limit values are set under the limits of the respective reference values. A design support method characterized by being calculated. 16. The electro-migration and hot carrier effect according to claim 15, wherein the first and second verification factors are an electromigration and a hot carrier effect, respectively.
A design support method characterized by being represented by predetermined first and second expressions. 17. The design support method according to claim 16, wherein the first expression for the electromigration is given by the following expression (1) related to a reference lifetime (t50). [Number 1] ^{(t50 =) ApJ n e Ea} / KT <T life (1) where, in the formula (1), Ap and n is a constant depending on the process, J current density of wiring (A / m ²⁾ And J =
I / Sa, K is Boltzmann's constant, T is the absolute temperature, I is the current (A) of the wiring, and Sa is the cross-sectional area (m ² ) of the wiring, and Ea is the activation energy;
And T _life is the lifespan. 18. The design support method according to claim 16, wherein the second equation for the hot carrier effect is given by the following equation (2) relating to a maximum capacitance value Cmax. [Number 2] ^{(Cmax =) α1xS β1 xW>} C (2) where, S is the normalized stress amount, [alpha] 1, .beta.1 is a constant depending on the process and primitive circuitry and waveform rounding, W is N-channel It is the width (μm) of the transistor, and the normalized stress amount S is expressed by the following equation (3). The Equation 3] _{S = (1 / τ α)} x (1 / f) x (α 2) x (e β2xT) (3) where tau _alpha, product applications, or, depending on the reliability assurance level Is a constant (time), and f is the operating frequency (H
z), α ₂ and β ₂ are process-dependent constants and T
Is the absolute temperature. 19. The method of claim 1, wherein the first and second
Wherein the limit value is a limit value determined for each waveform rounding. 20. The design support method according to claim 19, wherein the first and second limit values are frequency limit values determined for a combination of a rounded waveform and a load capacity. 21. A storage medium used when designing and verifying a circuit represented at a logic level, comprising: a table relating to a plurality of factors used for the design and verification; and synthesizing the plurality of factors. Recording means for storing a procedure for storing the information.