JP3091568B2 - Layout design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design considering timing and electrical characteristics.

[0002]

2. Description of the Related Art As circuits become larger and smaller, malfunction of the circuits due to signal propagation delay caused by wiring capacitance becomes a problem. In particular, it is important to consider the delay of wiring that is critical in timing. Generally, an upper limit of the delay time is imposed on a wiring that is critical in terms of timing, and layout processing is performed so as to satisfy this restriction. Here, the wiring that is critical in terms of timing is generally a path formed by a chain of cells and nets connecting between flip-flops.

Conventional methods for setting delay constraints on paths include a method of setting an upper limit on the propagation delay time of a signal from the start point to the end point of the path, and a method of setting an upper limit on the delay time for each net constituting the path. A method of obtaining a slack value that is a difference between a delay time required for the entire path and a time required for the signal to actually propagate, and a method of imposing a constraint that the value is set to zero or more, and a slack value for the path It is a method of assigning to each net constituting a path.

[0004] In the method of setting an upper limit of the delay time for the entire path, it is possible to express which part of the path to optimize the delay in order to satisfy the constraint is effective for reducing the delay of the entire path. Did not. Therefore, it is difficult to efficiently optimize the timing in the layout processing, and there is a problem that processing time is unnecessarily long or a required delay time constraint cannot be satisfied.

The method of setting the upper limit constraint of the delay time for each net constituting the path also has a problem that it is not possible to specify which net has a problem in terms of the delay time when the entire path is viewed. There was a problem that it was difficult to achieve the conversion.

A method of using slack value for a path is as follows.
Although it is easy to recognize a path that is critical in terms of timing, there is a problem that it is difficult to improve the delay of any part of the path to improve the slack value of the path, which is effective in improving the delay of the entire path.

[0007] It is necessary to execute timing analysis every time the layout state changes, which is also a problem in processing time. The method of setting the slack value for each net constituting the path is basically a method of allocating the slack value for the path to each net constituting the path, so it is necessary to update the net slack value every time layout processing is performed. As with the pass slack method, there is a problem in processing time.

On the other hand, recent advances in VLSI miniaturization technology have enabled the realization of large-scale integrated circuits. Along with that, minimizing chip area, shortening processing time,
Various automatic layout systems aiming at satisfying electrical characteristics have been developed.

In the conventional layout design, in order to shorten the delay time of a signal path (hereinafter referred to as a critical path) having a small delay time margin with respect to a required specification of a maximum delay time, a net weight method and a path in automatic placement are required. There have been proposed a method of solving the constraint as an optimal problem by restricting the constraint in a quadratic or primary form with respect to the wiring length, and a method of defining a force for shaping a path and optimizing the path.

The net weight method is a method using weighting for a net (a wiring network having the same potential between logic cells), and is described in Burstein, M., and Youssef,
M., "Timing Influenced Layout Design", Proc. 22nd D
esign Automation Conf., IEEE, pp. 124-130, 1985 (Reference 1).

According to this method, a critical net is detected for each placement process, its slack value (required arrival time-actual (virtual) arrival time) is calculated, and a net corresponding to the slack value is calculated. It is characterized in that a weight is attached to the net.

[0012] As a method of solving a constraint related to a path as a second-order or first-order optimization problem, Jackson, M., Srinivasa
n, A., and Kuh, E., ”A Fast Algorithm for Performance
-Driven Placement ”, Proc. International Conferenc
e on Computer-Aided Design'90., IEEE, pp.328-331,19
90, Jackson, M., and Kuh, E., ”Performance-Driven Pla
cement of Cell Based IC's ”, Proc. 26th Design Aut
omation Conf., IEEE, pp. 370-375, 1989 (Reference 2).

In this method, a critical path is extracted in advance, and each path constraint is given as a chain of net delays.

Igarashi, M., Murakata, M., and Murofush, which use a force relaxation method to shape the shape of a path.
i, M., ”Timing Driven Placement by the Path Delay
Relaxation Force Method ”, Proc. Custom Integrated
Circuit Conf., IEEE, 1992toappear (Reference 3).

Briefly, a virtual force is applied to the cells constituting the critical path to shape the path so as to reduce the delay. In this method as well, it is necessary to extract a critical path in advance, and each path constraint is given as a chain of net delays.

If the layout design is executed by such a method, it is possible to shorten the designated net (path).

However, in these methods, nets (paths) other than the designated net (path) often become critical, and a lot of time is required to redo the layout. In addition, in a method in which a constraint is applied each time a path or a net that becomes critical appears, the chip area tends to increase.

Further, in the path constraints used in these methods, the relationship between the paths is not explicitly expressed, and such information is not used in the placement processing. It is difficult to know whether the delay as a whole can be optimized.

In logic design, a branch slack method is used as a method for extracting a critical path. This includes Ju, Y., and Saleh, R., “Incremental Techniques f
or the Identificaltionof Statically Sensitizable C
ritical Paths ”, Proc. 28th Design Automation Con
f., IEEE, pp. 541-546, 1991 (Reference 4).

The branch slack method is a method for expressing a graph composed of a connection relationship between cells and nets, in which it is easy to extract the top k (k is an arbitrary positive number) critical paths having a small delay time margin. In addition, this method is used when there is a change such as replacing the cell with a cell having a higher driving capability (only when the connection relationship between the cell and the net does not change).
In addition, new top k paths can be easily extracted. mainly,
It is used to check whether the delay time of the critical path has been reduced.

In a layout design, there has been proposed a method of reducing a delay time by replacing cells constituting a critical path by applying a branch slack method. However, an example in which the branch slack method is directly applied to a layout design is as follows. Absent.

[0022]

The conventional method of setting a path delay constraint has a problem that it is difficult to extract the most critical path in terms of timing in each processing step of the layout, and as a result, timing optimization is not sufficient. In some cases, there is a problem that the layout processing takes a very long time to achieve the optimization.

Further, the conventional method of setting a path delay constraint has a problem that it is not easy to determine which part of a path should be improved to improve the path delay. In order to ascertain, it is necessary to execute timing analysis every time layout processing is performed, and there is a problem that processing time is required.

On the other hand, in the conventional layout design method, electric characteristics are not taken into consideration at the stage of arrangement.
For this reason, when dealing with large-scale circuits, the delay time of restricted nets and paths can be reduced, but the delay time of other nets and paths tends to be long, and both processing time and chip area deteriorate. There was a problem of doing.

Further, in the conventional layout design method,
The branch slack method that can easily extract a critical path has not been applied.

The present invention has been made in view of the above-described problems, and a first object of the present invention is to provide a layout capable of setting a path delay constraint for facilitating extraction of a timing-critical path in each layout processing process. It is to provide a design method.

A second object of the present invention is to apply a branch slack method to a layout design to shorten a wiring length for a critical path when arranging cells, to sufficiently consider electrical characteristics, and to take layout design time into consideration. Is to provide a layout design method that can reduce the chip size and prevent the chip area from increasing.

[0028]

According to a first aspect of the present invention, there is provided a cell for connecting between flip-flops and between a flip-flop and I / O of a chip in a layout design of a semiconductor integrated circuit. The delay time required for a path consisting of a chain of nets is allocated to each net constituting the path, and this is set as the required time for each net, and estimated from the required time for this net and the expected wiring length of the net. The difference from the delay time is defined as the slack value of the net, and the path is divided at the branch / junction point of the path to form sub-paths. For each sub-path, the sum of the slack values of the nets constituting the sub-path is calculated as the sub-path. If there is a branch / junction point in the path, the difference in slack value between subpaths sharing the branch / junction point is Δ
There is provided a means for setting a minimum slack value among subpaths sharing a branching / merging point as a delay constraint for each subpath.

According to a second aspect of the present invention, in designing a layout of a semiconductor integrated circuit, a connection relation between logic cells constituting the semiconductor integrated circuit, an electric characteristic of each cell, and an electric connection of a wiring connecting each cell. Characteristics, and input the upper limit value of the signal propagation delay time, estimate the wiring length of each wiring, form a graph with each cell as a node and the connection relationship between cells as an edge,
A wire delay is applied to the edge, and the time required for a signal from the cell to reach the storage element at the node is determined by the time required for a signal to propagate through each edge and reach the storage element between edges output from one node. Give this time difference as information,
The signal path with the longest delay is obtained based on the graph, a partial path having a large difference in signal propagation delay time given between edges on the obtained signal path is extracted, and the extracted partial path is preferentially extracted. The cells are rearranged, each information of the graph is updated as the cells are rearranged, the signal propagation delay time is calculated based on the updated graph, and the calculated signal propagation delay time is the upper limit value input. Means for determining whether or not the condition is satisfied.

[0030]

According to the first aspect of the present invention, the delay time required for the critical path is assigned to each net constituting the critical path, and is set as the required time for each net. The difference between the required time and the delay time estimated from the expected wiring length of each net is defined as the slack value of each net.

Then, the critical path is divided at the branch / junction points to form subpaths, and the sum of the slack values of the nets constituting each subpath is defined as the slack value for this subpath. The difference between the slack values of the subpaths sharing the branching / converging point is defined as Δsubpath slack, which is used as an index for determining which subpath has a longer delay time.

Further, the minimum slack value in the subpaths sharing the branch / join point is set as a delay constraint for each subpath.

According to the second invention, a graph representation of a cell and a net by the branch slack method is obtained using input information between cells, electric characteristics of each cell, and electric characteristics of a wiring. As before, each edge of the graph has a wiring delay due to the net, each node has a maximum signal propagation time from the cell to the storage element, and each edge passes between edges coming out of the same node. The difference (branch slack) of the maximum signal propagation time at the time of occurrence is stored.

By using this to determine a partial path having a branch slack equal to or greater than the threshold value, priorities of cell movements that do not make other paths critical and do not complicate the updating of the graph are assigned. , The delay of the critical path is reduced.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

First Invention FIG. 1 is a flowchart showing a processing procedure of the first invention.

First, a net list to be subjected to layout processing and timing request information are input (step S).
1). The timing requirement information generally includes an upper limit constraint on the delay time for a path formed by a chain of cells and nets between flip-flops.

Based on this information, a path between flip-flops to be subjected to timing optimization processing is extracted.
FIG. 2 illustrates an example of a path, and illustrates three paths T1, T2, and T3 having branches at points X and Y. Here, the path delay is the sum of the internal delay of the cell (circled) and the wiring delay, and the path delay is generally given by the sum of these two delays.

Here, it is assumed that a value obtained by subtracting the cell internal delay from the path delay is a delay time requirement by a net constituting the path, and is referred to as RT1, RT2 and RT3, respectively.

Next, the request for the delay time for the net component of the extracted path is allocated to each net constituting the path, and the required time is set for each net (step S2).

The assignment of the delay time to each net is performed by, for example, a method of proportionally distributing the delay time according to the fan-out of the net. An example of how to assign a delay time to a net will be described with reference to FIG.

The path in this example is composed of three nets, net 1 is fan-out 3, net 2 is fan-out 1,
Assuming that the net 3 has a fan-out 4 and the required time for this path is 8, time 3, 1 and 4 are allocated to each net according to the fan-out.

The virtual wiring length is estimated for each net, and the expected delay time is obtained from the estimated wiring length (step S3). The virtual wiring length of the net can be estimated as a function of the fanout of the net and the chip size, and the virtual wiring length L can be obtained by the following equation, for example.

L = a * ba a = α + β · √chip size b = γ + number of fan-outs of the net The expected wiring delay of the net is calculated by multiplying the obtained virtual wiring length by the wiring delay per unit length. I do.

A slack value, which is a difference between the required time and the expected delay time, is calculated for each net constituting the path, and is set as a net slack (step S4). FIG. 4 shows an example in which net slack is assigned to each net. Δt1 in the figure
~ Δt10 is the net slack.

The path is broken down into partial paths, that is, sub-paths at the branch / merging points X and Y (step S5).

Further, for each sub-path, a sub-path slack of the same sub-path is determined from the sum of the slack values of the nets constituting the same sub-path (step S6).

The difference of the subpath slack between the subpaths sharing the branching / converging points X and Y is determined as Δsubpath slack. Then, the minimum subpath slack among the subpaths sharing the branch / confluence points X and Y is set as a constraint on the related subpath (step S7).

For a subpath having no branch / merge point, the subpath slack for the same subpath is set to the minimum subpath slack, and the Δ subpath slack is set to zero. FIG. 5 shows a setting example of the subpath slack and the Δsubpath slack.

In the figure, ΔT1 = Δt6 + Δt7 + Δt8,
ΔT2 = Δt4 + Δt5, ΔT3 = Δt9 + Δt10,
ΔT4 = Δt1 + Δt2, Δt3 is a subpath slack. Δa = ΔT1− ｛Δt3 + min (ΔT
2, ΔT3)｝, Δb = ΔT2-ΔT3, Δc = 0,
It becomes Δ sub-path slack.

By using such a path delay constraint setting method, it is possible to easily recognize a subpath having a minimum subpath slack, that is, a path having a minimum delay time margin.

When there are branch points X and Y, the timing can be efficiently optimized by focusing on the portion where the Δ subpath slack is the largest. From this, it can be said that the Δ subpath slack is an index for determining which subpath has a longer delay time.

Therefore, the sub-path with the smallest sub-path slack is preferentially processed, and if all the sub-paths have the same value, the processing is performed from the sub-path with the largest Δ sub-path slack, and the layout result that optimizes the timing efficiently is obtained. Can be obtained.

Second Invention FIGS. 6 and 7 are flowcharts showing the processing procedure of the second invention.

First, information necessary for cell arrangement in consideration of electrical characteristics is input (step S11). This is the connection relationship between cells, the electrical characteristics of each cell and each wiring, and the upper limit value of signal propagation delay (required specifications regarding timing). The electrical characteristics of each cell are the internal delay, output resistance, and input capacitance of the cell, and the electrical characteristics of the wiring are the sheet capacitance per wiring unit length (this depends on the wiring layer, wiring width, etc. ).

The signal propagation delay time is calculated as follows.

[0057]

(Equation 1) This equation will be described with reference to FIGS. F. shown in FIG. F. (Flip-flop / storage element) to F.R. F. The path up to is the target path for the calculated signal propagation delay time, and the circuit shown in (B) is the net constituting the path in (A). In (B), the input capacitance is Ci, the sheet capacitance / wiring length is C _L , the output resistance is Ro, and the delay due to 2NOR is the internal delay.

C by such nets and cells
The signal propagation delay time of the path (A) is calculated from the sum of i, C _L , Ro, and the internal delay.

The signal propagation time is compared with the given upper limit value of the delay in step S16 to confirm whether or not the electrical characteristics are satisfied.

The initial arrangement (step S12) initially gives the position of each cell. Generally, cells are often arranged at random. If the initial arrangement has not been given, in the subsequent processing, the critical path having the maximum delay is arranged from a portion where the branch slack is large (the highest priority is given to convenience).

Whether or not the initial layout is given, the wiring length is estimated by some method (step S1).
3). Although the exact wiring length cannot be known without performing wiring processing, it is usually estimated by the outermost rectangle of the cell connected to the net.

Next, a graph is represented by the branch slack method (step S14).

FIG. 9B shows an example in which the critical path of FIG. 9A is represented by a graph using the branch slack method (however, the network is actually more complicated).

In (B), each edge (straight arrow) of the graph indicates the wiring delay due to the net, each node (circle) indicates the maximum signal propagation time from the cell to the flip-flop, and The difference (branch slack) between the maximum signal propagation times when passing through each edge is labeled between the two branched edges. FIG.
The maximum signal propagation time in (B) is 30.

In order to create this graph, a net is traced in the opposite direction to the flow of a signal from a flip-flop, and delay times from a certain cell to the flip-flop are sequentially stored. At the end of this, branch slack between edges protruding from each cell is obtained, and the edges are arranged in descending order of delay when passing through the edge.

The path P1 of the maximum delay (the path in FIG. 9A) starts with the largest signal propagation time to the flip-flop in each cell, and has the largest edge of the delay when passing through it. Are sequentially traced to the flip-flop (step S1).
5).

Thereafter, it is checked whether or not the required specification of the signal propagation delay is satisfied (step S16). If not, the cell is moved (step S17).
The movement process for the path P1 will be described with reference to the flowchart in FIG.

First, labels "large" and "small" are attached to each edge in P1 according to the magnitude of branch slack (step S171). For example, a label is given depending on whether the value is above a certain threshold.

A search is made from the source side of the path to extract a partial path of the net labeled "large" (step S172).

In the extracted partial path nets, cells connected to the branch slack are moved in descending order of branch slack (step S173). The moving direction is a direction for shaping the path (see Document 3), and is a direction for reducing the wiring delay. The process of step S173 is repeated for each cell of one partial path (loop 2).

When the cell moving process for one partial path is completed, P1 is further searched to extract a sequence of nets labeled "large", and the process is repeated (loop1).

If P1 cannot be searched any longer, each value of the graph is updated (step S18), the path P1 of the maximum delay is obtained again, and the process proceeds.

As described above, according to the second invention, the critical path is expressed in the form of a graph, and the relationship with the next critical path can be easily expressed. Is the same as
There is no new critical path.

Even when the graph is updated by moving the cell position, the labels (values) of the graph elements are updated without changing the graph structure.
Processing time is short.

Further, since the cell is moved from the portion where the branch slack is large, the trouble of updating is further reduced. In addition, since the most critical path is always processed, instead of unnecessarily increasing the path constraint, the processing time can be reduced and the chip area does not increase.

[0076]

According to the layout design method of the first invention, the most critical partial path in terms of timing can be easily extracted, and the timing can be optimized efficiently. In addition, when the net delay changes due to the layout processing, the Δsubpath slack is successively updated, so that the most critical partial path in terms of timing can always be extracted.

According to the layout method of the second aspect of the present invention, since the branch slack method is applied, the wiring length for the critical path can be shortened during the placement process, and the electrical characteristics can be sufficiently taken into consideration. The time can be reduced, and an increase in chip area can be prevented.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure of the first invention.

FIG. 2 is an example of a path having a branch / merge point.

FIG. 3 is an example of a path for explaining how to assign a delay time to a net.

FIG. 4 is an example of a path in which net slack is assigned to each net.

FIG. 5 is an example of a path showing an example of setting a sub path slack.

FIG. 6 is a flowchart showing a processing procedure according to the second invention.

FIG. 7 is a flowchart showing a procedure of a cell moving process.

FIG. 8 is a circuit diagram for explaining a signal propagation time of a path.

FIG. 9 is an example of a graph representation of a path by a branch slack method.

[Explanation of symbols]

T1, T2, T3 Critical path X, Y Branching / merging point Δt1 to Δt10 Net slack ΔT1, ΔT2, ΔT3, ΔT4, Δt3 Sub path slack Δa, Δb, Δc Δ sub path slack

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-123056 (JP, A) JP-A-3-108358 (JP, A) JP-A-5-151317 (JP, A) JP-A-5-151317 109896 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (2)

(57) [Claims] In a layout design of a semiconductor integrated circuit, a delay time required for a path consisting of a chain of cells and a net connecting between flip-flops and between a flip-flop and an I / O of a chip is defined as a path. Allocated to each of the constituent nets, this is the required time for each net, the difference between the required time for this net and the delay time estimated from the expected wiring length of the net is the slack value of the net, and the path is a branch of the path. -Divide at the junction to form sub-paths, and for each sub-path, sum the slack value of the nets that make up the sub-path as the slack value for the same sub-path. If the path has a branch / merge, branch / merge The difference of the slack value between the subpaths sharing a point is defined as Δ subpath slack, and the minimum slack value in the subpath sharing the branch / merge point Layout design method and sets the delay constraints for each subpath. 2. A layout design of a semiconductor integrated circuit, comprising: a connection relation between logic cells constituting the semiconductor integrated circuit; an electric characteristic of each cell; an electric characteristic of a wiring connecting each cell;
And input the upper limit value of the signal propagation delay time, estimate the wiring length of each wiring, form a graph with each cell as a node, and the connection relation between cells as an edge, a wiring delay at the edge, and a cell at the node. The time required for the signal from the node to reach the storage element is represented by the difference between the time it takes for the signal to propagate through each edge and reach the storage element between the edges leaving one node, Find the signal path with the longest delay based on the graph, extract the partial path with a large difference in the signal propagation delay time given between the edges on the determined signal path, and give priority to the cell from the extracted partial path. , And as the cells are rearranged, each information in the graph is updated. Based on the updated graph, the signal propagation delay time is calculated,
A layout design method, comprising: determining whether the calculated signal propagation delay time satisfies the input upper limit.