JP2000010825A - Microcomputer fault monitor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To diagnose whether or not a microcomputer fault monitor system, which monitors a program run signal, functions normally without stopping the operation of a microcomputer. SOLUTION: A program run signal (p) outputted from the microcomputer 10 is switched by a gate circuit 21 in cycles T2 and the cycles of a signal outputted from the gate circuit 21 are monitored by counter circuits 28 and 29, latch circuits 30 and 31, an OR circuit 32, and an AND circuit 33. When the signal having the cycles T2 is outputted, namely, when the program run signal pr is outputted, a pulse signal is outputted as a diagnostic signal dd, but when not, an ON signal is outputted. The microcomputer 10 decides that the microcomputer 10 and a fault diagnostic part 16 operate normally when the pulse signal is outputted as the diagnostic signal dd and decides that the fault diagnostic part 16 is abnormal when the OFF signal is outputted continuously for the time longer than a specific time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention monitors a program run signal output from a microcomputer (hereinafter, referred to as a microcomputer), and detects an abnormality when the program run signal is not output for a predetermined time due to a runaway of the microcomputer. The present invention relates to a microcomputer failure monitoring system that outputs a signal, and more particularly to a microcomputer failure monitoring system that outputs different signals when a program run signal is not output from a microcomputer and when an abnormality occurs in the microcomputer failure monitoring system itself.

[0002]

2. Description of the Related Art As a conventional microcomputer failure monitoring system, a system using a watchdog timer for outputting an abnormality detection signal when a program run signal is not output for a predetermined time or longer is known. In these microcomputer failure monitoring systems, if the microcomputer operates normally and a program run signal is output, no abnormality detection signal is output, but the microcomputer failure monitoring system itself has failed. The abnormality detection signal may not be output even though the program run signal is not output.

Therefore, in these microcomputer failure monitoring systems, when the microcomputer is turned on, a program run is started and a program run signal is output, and then the output of the program run signal to the microcomputer failure monitoring system is temporarily stopped. The diagnosis of whether the function of the microcomputer failure monitoring system is normal is made based on whether an abnormality detection signal is input to the microcomputer from the microcomputer failure monitoring system within a predetermined time.

[0004]

However, it is not possible to diagnose whether the function of the microcomputer failure monitoring system is normal or not unless the program run signal is stopped. Had to be temporarily stopped. The present invention has been made in view of the above-described conventional problems, and provides a highly reliable microcomputer failure monitoring system capable of diagnosing whether or not the function of the microcomputer failure monitoring system is normal without stopping the operation of the microcomputer. The purpose is to provide.

[0005]

SUMMARY OF THE INVENTION Therefore, the present invention is a failure monitoring system for monitoring the operating state of a microcomputer by inputting a program run signal from a microcomputer to a diagnostic means, wherein the diagnostic means comprises a program run signal. Gate means for passing a part of a pulse train based on the above at a predetermined cycle timing as a reset signal, timer means for resetting by a reset signal to set a predetermined time, and generating at a predetermined time set by the timer means Check pulse generation means for generating a check pulse that is reset by a subsequent reset signal, depending on the output state of the check pulse, whether the microcomputer is operating normally, the microcomputer is faulty, or the diagnostic means is abnormal. Is identified.

The gate means outputs an N-phase reset signal by passing a part of a pulse train based on the program run signal at a timing shifted by 1 / N (N is an integer of 2 or more) of a predetermined period, The timer means counts a predetermined time for each N phase, and the confirmation pulse generation means is configured to generate a confirmation pulse for each N phase. When the state in which none of the confirmation pulses of each phase is reset continues, the microcomputer And when no confirmation pulse is output for each phase, it can be determined that the diagnostic means is abnormal.

The above-mentioned gate means is 1 / N of a predetermined period.
A timer means for inputting a pulse train based on a program run signal and N timing pulses rising at a timing shifted by (N is an integer value of 2 or more) and outputting a logical product as a reset signal; Has N counter circuits that are reset by respective reset signals output from the N AND circuits and that output a set signal when a second predetermined time has elapsed after the reset. , A confirmation pulse is generated by each set signal outputted from the N counter circuits, and the N latch circuits resetting the confirmation pulse by the subsequent reset signal, and the logical product of the outputs of the N latch circuits. An AND circuit for outputting an OR circuit and an OR circuit for outputting a logical sum.
When the ON output state from the ND circuit continues, the microcomputer may be identified as a failure, and when the OFF output state continues from the OR circuit, it may be determined as an abnormality of the diagnostic means.

[0008]

According to the present invention, when both the microcomputer and the microcomputer failure monitoring system are operating normally, a reset signal is output from the gate means at predetermined intervals. A confirmation pulse is generated every predetermined time set by the timer means, and the confirmation pulse is reset by the reset signal. Therefore, a confirmation pulse is outputted as the output of the confirmation pulse generating means at every predetermined period. On the other hand, if the microcomputer breaks down and the output of the program run signal stops, the output of the reset signal from the gate means also stops. For this reason, after a predetermined time set by the timer means has elapsed since the reset signal immediately before the stop of the program run signal is output, a confirmation pulse is generated by the confirmation pulse generation means, and once the output is turned on, Since the next reset signal is not input, the ON state is continued. In addition, when an abnormality occurs in the diagnosis unit, a reset signal or a confirmation pulse is not output in many cases, and the output of the confirmation pulse generation unit is normally in an off state.

If the output of the confirmation pulse generation means is input to, for example, a microcomputer, the microcomputer will determine that both the microcomputer and the failure monitoring system are operating normally if the confirmation pulse is output at a predetermined period. If the determination can be made, and if the OFF signal is continuously output, it is determined that an abnormality has occurred in the diagnostic means, and appropriate measures can be taken. As described above, if an abnormality occurs in the diagnosis unit, it is determined from the change in the output state of the confirmation pulse generation unit.Therefore, the operation of the microcomputer is bothersomely stopped and the microcomputer failure monitoring system is operating normally. There is no need to make a diagnosis.

Also, 1 / N of a predetermined period is supplied from the gate means.
(N is an integer of 2 or more). By outputting an N-phase reset signal at a timing shifted by each time and generating a confirmation pulse for each N phase from the confirmation pulse generator, the program run signal can be monitored more frequently. it can.

Further, N AND circuits for outputting a logical product of N timing pulses and a pulse train of a program run signal as a reset signal, N counter circuits for setting a predetermined time, and a latch for outputting a confirmation pulse A circuit, an AND circuit that outputs a logical product of the latch circuits, and an OR circuit that outputs a logical sum of the latch circuits. Then, for example, the output of the OR circuit is input to the microcomputer, and the microcomputer monitors the abnormality of the diagnostic means. The output of the AND circuit is input to the fail-safe means, and the fail-safe means takes measures such as disconnecting the controlled part from the microcomputer when the ON output state continues from the AND circuit. Thus, even when the output of the program run signal is stopped due to the microcomputer running out of control, appropriate measures can be taken.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to examples. First, the overall configuration of the present embodiment will be described with reference to FIG. In the present embodiment, the microcomputer failure monitoring system of the present invention is applied to a microcomputer for controlling an actuator. Microcomputer 10
Has a power supply terminal 1, a switch signal input terminal 2, a sensor signal input terminal 3, an ACTR control signal output terminal 4, a diagnostic signal input terminal 5, a program run signal output terminal 6, and a microcomputer reset signal input terminal 7.

The power supply terminal 1 is connected to a regulator circuit 14 for converting a voltage supplied from a battery (not shown) to a reference voltage VCC. The microcomputer 10 outputs a signal input from the switch 11 to the switch signal input terminal 2,
An ACTR control signal ac for controlling the actuator 13 is output from an ACTR control signal output terminal 4 based on a signal input from the sensor 12 to the sensor signal input terminal 3.

The ACTR control signal output terminal 4 is connected to a resistor R1
Is connected to the resistor 2 and the base of an ACTR control transistor TR1 for controlling the actuator 13. The resistor 2 is a resistor connected to reliably turn off the transistor TR1 when the ACTR control signal ac becomes high impedance.

The ACTR control signal output terminal 4 is also connected to a transistor TR2 for fail-safe control. When a fail-safe signal fs described later is turned on, the transistor TR2 outputs the ACTR control signal ac.
Irrespective of the signal level of the transistor TR1. The diagnostic signal input terminal 5 receives the diagnostic signal dd output from the failure diagnostic unit 16 of the microcomputer control unit 15. From the program run signal output terminal 6, a program run signal p, which is a pulse signal of period T1,
r is output to the failure diagnosis unit 16. The microcomputer reset signal mr is input from the NOR circuit 18 to the microcomputer reset signal input terminal 7.

The microcomputer control unit 15 includes a failure diagnosis unit 16
And a power-on-clear circuit 17 for monitoring the potential of the reference voltage VCC and outputting a power-on-clear signal cl when the voltage becomes a voltage other than a predetermined voltage, a power-on-clear signal cl and an abnormality detection signal od, and a microcomputer reset signal mr. And a microcomputer reset signal mr
, And outputs an fail-safe signal fs. The reference voltage VCC is input from the regulator circuit 14 to the microcomputer control unit 15.

Next, FIG. 2 is a diagram showing a detailed configuration of the failure diagnosis section 16. As shown in FIG. The failure diagnosis unit 16 outputs the program run signal p
diagnosing whether or not r is normally output, and performing a self-diagnosis as to whether or not the diagnostic operation is normally performed;
The diagnostic signal dd and the abnormality detection signal od are output. The edge detection circuit 20 receives the program run signal pr output from the microcomputer 10 and the clock signal CLK output from a clock circuit (not shown), detects a rising edge and a falling edge of the program run signal pr,
The edge detection signal ed is output to the gate circuit 21.

The gate circuit 21 divides the clock signal CLK and outputs a timing pulse d1 having a cycle T2 at a duty ratio of 50, and a timing pulse d.
1 and an edge detection signal ed, an AND circuit 23 that outputs a logical product as an edge detection signal e1, an inverter circuit 24 that outputs a timing pulse d2 obtained by inverting the timing pulse d1, a timing pulse d2 and an edge detection signal An AND circuit 25 receives ed and outputs a logical product as an edge detection signal e2. The edge detection signal e1 is input to the OR circuit 26, and the edge detection signal e2 is input to the OR circuit 27.

The OR circuit 26 outputs to the counter circuit 28 and the latch circuit 30 a reset signal r1 which is the logical sum of the edge detection signal e1 and the power-on-clear signal cl output from the power-on-clear circuit 17. OR circuit 27
Outputs a reset signal r2 which is a logical sum of the edge detection signal e2 and the power-on clear signal cl to the counter circuit 29 and the latch circuit 31.

The counter circuit 28 resets the count value by the reset signal r 1, counts up by the clock signal CLK, and outputs the latch set signal s 1 to the latch circuit 30 when the count value exceeds a predetermined value. . The counter circuit 29 resets the count value by the reset signal r2, counts up by the clock signal CLK, and outputs the latch set signal s2 to the latch circuit 31 when the count value becomes a predetermined value or more.

The latch circuit 30 has a latch set signal s1
, And is reset by the reset signal r1 to output the latch output signal o1 to the OR circuit 32 and the AND circuit 33. The latch circuit 31 is turned on by the latch set signal s2, is reset by the reset signal r2, and outputs the latch output signal o2 to the OR circuit 32 and the AND circuit 33. The OR circuit 32 has a latch output signal o1 and a latch output signal o2.
And outputs a diagnostic signal dd as a logical sum. AN
The D circuit 33 receives the latch output signal o1 and the latch output signal o2, and outputs an abnormality detection signal od which is a logical product.

The AND circuits 23 and 25 constitute the gate means of the present invention, and the counter circuit 28 and the counter circuit 29 constitute the timer means, and the latch circuits 30 and 3
1, the OR circuit 32 and the AND circuit 33 constitute the confirmation pulse generating means of the present invention. Further, the failure diagnosis unit 16 forms a diagnosis unit. Latch output signals o1 and o2 are confirmation pulses of the invention.

Next, the operation of the microcomputer failure monitoring system of this embodiment will be described. First, the operation when both the microcomputer 10 and the failure diagnosis unit 16 are operating normally will be described using the timing chart shown in FIG. Time S1
Then, when the power is turned on and the power supply voltage VCC changes from a low level (hereinafter referred to as L level) to a high level (hereinafter referred to as H level), it is output from the power-on clear circuit 17 and is shown in FIG. Power-on clear signal c
l is at the H level until time S2 when the operation of the microcomputer 10 is stabilized.

During the period from time S1 to time S2, NO
The input terminal of the R circuit 18 has a power-on clear signal cl
3 and the L level of the abnormality detection signal od are input, so that the microcomputer reset signal mr, which is the output shown in FIG. When the microcomputer reset signal mr is at L level, the fail-safe signal fs inverted by the inverter circuit 19 is at H level. The details of the operation of the fail-safe signal fs will be described later.

At time S2, the power-on clear signal cl
Changes to the L level, and at this time, the abnormality detection signal o
Since d is also at L level, both inputs of the NOR circuit 18 are at L level, the microcomputer reset signal mr is at H level, each circuit of the microcomputer 10 is reset, and at time S3, the program run signal output terminal of the microcomputer 10 6
From the program run signal p of the cycle T1 shown in FIG.
r is output. The failure diagnosis unit 16 also starts operating, and when the program run signal pr is input, the edge detection circuit 20 outputs an edge detection signal ed shown in (c). By detecting the edge of the program run signal pr by the edge detection circuit 20, a malfunction can be prevented even when the pulse shape and the duty ratio of the program run signal pr slightly deviate from the normal state.

From the frequency dividing circuit 22, the period T shown in FIG.
At 2, a timing pulse d1 having a duty ratio of 50 is output and input to the AND circuit 23 and the inverter circuit 24. From the inverter circuit 24, a timing pulse d2 whose cycle shown in (e) is inverted is output and input to the AND circuit 25.

From the AND circuit 23, an edge detection signal e1 shown in (f) is output and input to the OR circuit 26.
The edge detection signal e1 indicates that the timing pulse d1 is H
During the level, the pulse signal has the same time width as the edge detection signal ed, and is at the L level while the timing pulse d1 is at the L level. The OR circuit 26 outputs a reset signal r1 which is a logical sum of the power-on clear signal cl and the edge detection signal e1. Similarly, the AND circuit 25 outputs an edge detection signal e2 shown in (g) that alternately repeats the pulse signal and the L level, and the OR circuit 27 outputs a reset signal r2.

The counter circuit 28 counts up by the CLK signal, and outputs a latch set signal s1 as a pulse signal when the count value exceeds a predetermined value. When the reset signal r1 goes high, the count value is reset. That is, when the state of the reset signal r1 at the L level continues for the monitoring time T3 which is the time until the count value reaches the predetermined value, a pulse signal is output.
As shown in (h), in the latch set signal s1, since the pulse signal is output as the reset signal r1 from the time S3 to the time S5, the reset is repeated, and the count value may not exceed the predetermined value. Absent.

Since the L level state of the reset signal R1 continues after the time S5, the count is incremented, and a pulse signal is output at a time S6 after a monitoring time T3 from the time S5. At time S7, the reset signal r1 is pulsed again, so that the reset is repeated. Thereafter, similarly,
A pulse signal is output in the cycle T2. Similarly, in the latch set signal s2 shown in (i) output from the counter circuit 29, a pulse signal is output at time S4 when the L level state of the reset signal r2 has continued for the monitoring time T3 or more, and thereafter in the cycle T2. A pulse signal is output.

As shown in (j), the latch circuit 30 goes high at time S6 when the latch set signal s1 is input.
Level S7 when the reset signal r1 is input
, And thereafter, a latch output signal o1 is output which also becomes H level every cycle T2. Latch circuit 31
From the time S4, the level becomes the H level in the cycle T2 from the time S4 (k)
Is output.

The OR circuit 32 outputs a latch output signal o1
A diagnostic signal dd indicated by (l), which is a logical sum of the latch output signal o2 and the latch output signal o2, is input to the diagnostic signal input terminal 5 of the microcomputer 10. In a normal state, the diagnostic signal dd is an H-level pulse signal with a period T2 / 2. From the AND circuit 33, the latch output signal o1 and the latch output signal o
An abnormality detection signal od indicated by (m), which is a logical product of 2, is output to the NOR circuit 18. In a normal state, both the latch output signal o1 and the latch output signal o2 are at H level.
Since the level does not reach the level, the abnormality detection signal od goes to the L level.

After time S2, the power-on clear signal c
Since l is at the L level, if the abnormality detection signal od is at the L level, the microcomputer reset signal mr shown in FIG.
Level, so that the fail-safe signal fs becomes L level, and the fail-safe operation is not performed. When the signal input from the diagnostic signal input terminal 5 is a pulse signal having a period T2 / 2, the microcomputer 10
0 and the failure diagnosis unit 16 are both determined to be operating normally.

Next, the operation when the microcomputer 10 fails and the program run signal pr stops will be described with reference to FIG. An abnormality occurs at time S10 in the microcomputer 10 which has been operating normally until time S9, and the program run signal p
The operation when the output of r is stopped will be described. When the output of the program run signal pr is stopped, the edge detection signal e
d, the edge detection signal e1 and the edge detection signal e2 also become L level after time S10.

Since the counter circuit 28 counts up from the time S9, at the time S11 after the monitoring time T3 from the time S9, as shown in FIG. Output to
The latch output signal o1 shown in (j) goes high at time S11 due to the latch set signal s1, but keeps the high level thereafter since the reset signal r1 is not input.

In the counter circuit 29, when the reset signal r2 is L
The count-up is started from the time S10 when the level becomes the level, and a pulse signal is output to the latch circuit 31 at the time S12 after the monitoring time T3 as shown in (i). The latch output signal o2 shown in (k) goes high at the time S12 due to the latch set signal s2, but keeps the high level thereafter since the reset signal r2 is not input.

Therefore, the diagnostic signal dd becomes H after time S11.
Level, and the abnormality detection signal od becomes H after time S12.
Level. When the abnormality detection signal od becomes H level,
The microcomputer reset signal mr shown in (n), which is the output of the NOR circuit 18, goes low, and the fail-safe signal fs goes high. When the fail-safe signal fs becomes H level, a fail-safe operation is performed. The transistor TR2 for failsafe control is turned on,
The ACTR control signal ac output from the ACTR control signal output terminal 4 of the microcomputer 10 is grounded, the transistor TR1 for ACTR control is turned off, and the microcomputer 10 and the actuator 13 are disconnected.

Next, the operation when the failure diagnosis unit 16 has failed will be described with reference to FIG. The failure diagnosis unit 16 that has been operating normally until the time S9 has an abnormality at the time S13, and despite the output of the program run signal pr, the latch set signal s1 and the latch set signal s2.
Output has stopped. When the output of the latch set signal s1 and the latch set signal s2 is stopped, the latch circuit 30 is set at time S14,
15, the latch circuit 31 is no longer set,
The latch output signal o1 and the latch output signal o2 are at time S
The off state is continued after 13. When the OFF signal is continuously input to the diagnostic signal input terminal 5 for T2 / 2 hours or more, the microcomputer 10 determines that an abnormality has occurred in the failure diagnostic unit 16 and outputs the abnormality from the ACTR control signal output terminal 4. A
When the CTR control signal ac is turned off, the actuator 13
Stop control of.

As described above, the program run signal is output from the microcomputer 10 at the cycle T1, and
When both the failure diagnosis unit 16 and the failure diagnosis unit 16 are operating normally, a pulse signal having a period T2 / 2 is output as the diagnosis signal dd.
An L level off signal is output as the abnormality detection signal od. When the program run signal pr is not output, an H-level ON signal is output as the diagnostic signal dd, and an ON signal is also output as the abnormality detection signal od. When the abnormality detection signal od turns on, the fail-safe signal fs
Is also turned on, and the actuator 13 is disconnected from the microcomputer 10.

An abnormality occurs in the failure diagnosis section 16 and the diagnosis signal d
When the off signal of the L level is continuously output for both d and the abnormality detection signal od, the microcomputer 10 turns off the ACTR control signal ac and stops the control of the actuator 13. As described above, when an abnormality occurs in the failure diagnosis unit 16,
Since it is clear from the state change of the diagnostic signal dd, it is possible to diagnose whether or not the function of the microcomputer failure monitoring system is normal without stopping the operation of the microcomputer, thereby improving the reliability of the microcomputer failure monitoring system. Can be.

[0040]

According to the present invention, when both the microcomputer and the microcomputer failure monitoring system are operating normally, the confirmation pulse is output as the output of the confirmation pulse generation means at predetermined intervals, while the microcomputer fails. On the other hand, when the output of the program run signal is stopped, the output of the confirmation pulse generating means is kept on. When an abnormality has occurred in the diagnostic means, the output of the confirmation pulse generating means is normally turned off. If the output of these confirmation pulse generating means is input to the microcomputer, the microcomputer outputs a confirmation pulse of a predetermined period when the confirmation pulse is output.
It can be determined that both the microcomputer side and the failure monitoring system are operating normally, and if the OFF signal is continuously output, it can be determined that an abnormality has occurred in the diagnostic means, and appropriate measures can be taken. . As described above, a reliable microcomputer failure monitoring system that can diagnose whether the function of the microcomputer failure monitoring system is normal or not from the change in the output state of the confirmation pulse generation means without stopping the operation of the microcomputer Can be provided.

Further, 1 / N of a predetermined cycle is supplied from the gate means.
(N is an integer of 2 or more). By outputting an N-phase reset signal at a timing shifted by each time and generating a confirmation pulse for each N phase from the confirmation pulse generator, the program run signal can be monitored more frequently. it can. In addition, N ANs
A gate means constituted by a D circuit, N counter circuits for setting a predetermined time, a latch circuit for outputting a confirmation pulse, and an AND circuit for outputting a logical product of the latch circuits;
An OR circuit for outputting the logical sum of each latch circuit is provided.
The output of the circuit is input to the microcomputer, and the microcomputer monitors the abnormality of the diagnostic means. The output of the AND circuit is input to the fail-safe means, and the fail-safe means takes measures such as disconnecting the controlled unit from the microcomputer when the ON output state continues from the AND circuit. As a result, even when the output of the program run signal is stopped due to the microcomputer running out of control, appropriate measures can be taken, and a more convenient microcomputer failure monitoring system can be provided.

In this embodiment, the gate portion is connected to two.
However, the present invention is not limited to this. The gate means is constituted by a single AND circuit, and the timer means and the confirmation pulse generating means are constituted by a single set of the count circuit and the latch circuit, respectively. If this is the case, the circuit can be simplified. Furthermore, although the timer means is constituted by the counter circuit, the present invention is not limited to this. Any means may be used as long as it monitors the time elapsed since the reset signal was output from the gate means. If a device that monitors the elapsed time by using the method is used, the cost can be further reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a failure diagnosis unit.

FIG. 3 is a timing chart illustrating the operation of the embodiment.

FIG. 4 is a timing chart illustrating the operation of the embodiment.

FIG. 5 is a timing chart for explaining the operation of the embodiment.

[Explanation of symbols]

1 power terminal 2 switch signal input terminal 3 sensor signal input terminal 4 ACTR control signal output terminal 5 diagnostic signal input terminal 6 program run signal output terminal 7 microcomputer reset signal input terminal 10 microcomputer 11 switch 12 sensor 13 actuator 14 regulator circuit 15 microcomputer control Unit 16 failure diagnosis unit 17 power-on-clear circuit 18 NOR circuit 19, 24 inverter circuit 20 edge detection circuit 21 gate circuit 22 divider circuit 23, 25, 33 AND circuit 26, 27, 32 OR circuit 28, 29 counter circuit 30, 31 Latch circuit R1, R2 Resistance TR1, TR2 Transistor

Claims (3)

[Claims] 1. A failure monitoring system for monitoring an operation state of a microcomputer by inputting a program run signal from a microcomputer to a diagnosis unit, wherein the diagnosis unit converts a part of a pulse train based on the program run signal into a predetermined period. Gate means for passing a reset signal at a timing, timer means for setting a predetermined time after being reset by the reset signal, confirmation that the reset signal is generated every predetermined time set by the timer means and reset by a subsequent reset signal Having a check pulse generating means for generating a pulse, and determining whether or not the microcomputer is operating normally, whether or not the microcomputer is faulty, or whether or not the diagnostic means is abnormal, based on an output state of the check pulse. Microcomputer failure monitoring system. 2. The gate means outputs an N-phase reset signal by passing a part of a pulse train based on a program run signal at a timing shifted by 1 / N (N is an integer of 2 or more) of a predetermined cycle. The timer means sets a predetermined time for each of the N phases, and the confirmation pulse generating means
A confirmation pulse is generated for each of the N phases, and when a state in which none of the confirmation pulses of each phase is reset continues, the microcomputer is identified as a malfunction of the microcomputer, and when none of the confirmation pulses of each phase is output, the diagnosis means. 2. The microcomputer failure monitoring system according to claim 1, wherein the microcomputer is identified as an abnormality. 3. The method according to claim 1, wherein the gate means is 1 / N (N
(N is an integer value of 2 or more), and N pulse circuits based on a program run signal and N timing pulses rising at timings shifted by 2 are input, and N AND circuits outputting a logical product as a reset signal are provided. And N counter circuits that are reset by respective reset signals output from the N AND circuits and output a set signal when a second predetermined time has elapsed after the reset,
The confirmation pulse generating means generates a confirmation pulse in accordance with each set signal output from the N counter circuits, and resets the confirmation pulse in response to a reset signal thereafter. An AND circuit that outputs a logical product of outputs of the circuit and an OR circuit that outputs a logical sum; when the ON output state from the AND circuit continues, it is identified as a microcomputer failure; and the OFF output state is output from the OR circuit. 3. The microcomputer failure monitoring system according to claim 1, wherein the microcomputer is identified as an abnormality of the diagnosis unit when the operation is continued.