JP2003140779A - Watch dog timer diagnosing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a WDT diagnosing system capable of diagnosing the presence or absence of the abnormality of not only a watch dog timer but also a reset signal input terminal. SOLUTION: A WDT diagnosing circuit 20 outputs a reset signal when a pulse signal from a CPU 10 is away from a prescribed period. At the time of diagnosing failure, a reset signal level is set so as to be a higher level than the H level minimum input voltage of the reset signal input terminal RESB of the CPU so that the reset of the CPU can be prevented. When any failure is not diagnosed, the reset signal level is set so as to be a lower level than the L level maximum input voltage of the reset signal input terminal. The CPU receives the reset signal to a diagnosed result signal input terminal SINI which is different from the reset signal input terminal, and judges whether or not the WDT diagnosing circuit is normal based on the change of the reset signal. When WDT failure or open failure or the like on a route to the reset signal input terminal occurs, the reset signal is not changed so that the abnormality can be detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention monitors system operation, and when a pulse signal is not supplied to a specific signal line or deviates from a predetermined cycle, it is determined that the system is not operating normally and reset. The present invention relates to a watchdog timer diagnostic system capable of diagnosing a watchdog timer (hereinafter, referred to as “WDT”) that activates a clock.

[0002]

2. Description of the Related Art A conventional WDT diagnostic system is shown in FIG. In this system, a watchdog timer (WDT) diagnostic circuit 60 is composed of an ASIC, which is a dedicated IC, and is connected to a CPU (central processing unit) 50. The CPU 50 operates at the power supply voltage VDD,
From the pulse signal output terminal PRNO, the PR of a predetermined period pulse
A UN signal can be output. Further, the diagnostic status signal output terminal SINJO outputs a diagnostic status signal for controlling WDT diagnosis.

The WDT diagnostic circuit 60 first includes a power-on clear circuit (POC) 22 connected to a power supply voltage VDD via a power supply input terminal VCC and a PRUN from the CPU 50.
A WDT 24 connected to a pulse signal input terminal PRNI for inputting a signal is provided. WDT24 is the input PR
When the UN signal deviates from the predetermined cycle, the abnormality detection signal is output. In the WDT diagnostic circuit 60, the diagnostic status signal from the CPU 50 received by the diagnostic status signal input terminal SINJI is input to the AND circuit 62 and inverted to the AND circuit 64.

An abnormality detection signal output from the WDT 24 is also input to the AND circuit 64, and the WDT is diagnosed at the time of WDT.
Anomaly detection signal output from 24 is masked, and non-WDT
During diagnosis, an abnormality detection signal is output to the OR circuit 66. OR
The circuit 66 includes an AND circuit 64 and a power-on clear circuit 2
Output signals from 2 and 2 can be input, and when either one of the signals is input, a signal is output to the reset signal output transistor 68. The transistor 68 is turned on by the input of the reset output signal from the OR circuit 66, and outputs the reset signal from the reset signal output terminal RESO to the reset signal input terminal RESB of the CPU 50.

The connection line between the reset signal output terminal RESO and the reset signal input terminal RESB is connected to the power supply voltage VDD via the resistor 74, and when the transistor 68 is off, the reset signal input terminal RESB of the CPU 50 receives a non-reset signal. Is supplied to the reset signal input terminal RESB when the transistor 68 is in the ON state, and the L level (low level) signal as a reset signal is supplied to the reset signal input terminal RESB.

On the other hand, in the AND circuit 62, in addition to the diagnostic status signal from the diagnostic status signal input terminal SINJI, WD
The abnormality detection signal from T24 is input, the abnormality detection signal from the WDT 24 is masked when the WDT is not diagnosed by the diagnostic state signal, and the abnormality detection signal is output to the output buffer 70 during the WDT diagnosis. The output buffer 70 impedance-converts the output signal from the AND circuit 62 and outputs it as a diagnostic result signal from the diagnostic result signal output terminal SINO. This diagnostic result signal is input to the diagnostic result signal input terminal SINI of the CPU 50.

That is, the circuits after the AND circuit 64 are
When the PRUN signal deviates from the predetermined cycle, the reset signal is reset to C based on the abnormality detection signal output from the WDT 24.
This is reset by inputting to PU50, and AN
The circuits subsequent to the D circuit 62 input the abnormality detection signal output from the WDT 24 to the CPU 50 as a diagnosis result signal, so that the CPU 50 determines the abnormality of the WDT 24.

FIG. 8 is a time chart when the PRUN signal is normal in the non-WDT diagnosis in the conventional WDT diagnosis system. A diagnostic status signal input from the diagnostic status signal output terminal SINJO of the CPU 50 to the diagnostic status signal input terminal SINJI of the WDT diagnostic circuit 60,
And diagnostic result signal output terminal SI of the WDT diagnostic circuit 60
Since the WDT diagnostic result signal output from NO to the diagnostic result signal input terminal SINI of the CPU 50 is in the non-WDT diagnostic state, both are constant at the L level. Further, P input to the pulse signal input terminal PRNI
The RUN signal is a pulse signal having a predetermined cycle because it is normal, the WDT 24 does not output an abnormality detection signal, and the reset signal input to the reset signal input terminal RESB is constant at an H level indicating a non-reset state. Has become.

FIG. 9 shows that when the non-WDT diagnosis is performed, the PRUN
It is a time chart when a signal becomes abnormal. Here again, since it is in the non-WDT diagnostic state, the diagnostic state signal input to the diagnostic state signal input terminal SINJI and the WDT diagnostic result signal output from the diagnostic result signal output terminal SINO are both constant at the L level state. Has become. In this state, the PRUN signal input to the pulse signal input terminal PRNI deviates from the predetermined cycle at a certain time t1,
For example, when the low level becomes a constant value, the WDT 24
An abnormality detection signal is output at time t2 when the UN abnormality detection time TRES has elapsed.

Here, since the diagnostic state signal is a constant signal of L level, it is inverted and input to the AND circuit 64 as H level, and the output of the WDT 24 passes through the AND circuit 64 and the OR circuit 66. The transistor 68 is turned on. As a result, the reset signal input from the reset signal output terminal RESO to the reset signal input terminal RESB switches from the H level to the L level.

Next, a time chart when the PRUN signal is normal at the time of WDT diagnosis is shown in FIG. The diagnostic status signal input from the diagnostic status signal output terminal SINJO to the diagnostic status signal input terminal SINJI is WD
At the time t3 when the T diagnosis is started, the L level state is changed to the H level state. At the same time, the CPU 50 sets the PRUN signal input from the pulse signal output terminal PRNO to the pulse signal input terminal PRNI to a low level constant value deviating from a predetermined cycle as a pseudo abnormal signal.

As a result, the WDT 24 outputs an abnormality detection signal to the AND circuit 64 and the AND circuit 62 at the time t4 when the PRUN abnormality detection time TRES has elapsed. Here, the AND circuit 64 uses the diagnostic state signal input terminal SINJ.
The diagnostic status signal input to I is H level,
Since this is inverted and input as the L level signal, the abnormality detection signal is masked. Therefore, the abnormality detection signal is no longer output from the AND circuit 64, and the OR circuit 6
It will not be inputted to the CPU 50 as a reset signal through 6 and below.

On the other hand, since the diagnostic state signal is at the H level, the AND circuit 62 receives the abnormality detection signal from the WDT 24 and outputs the H level, and the AND circuit 62 outputs the diagnostic result from the diagnostic result signal output terminal SINO via the buffer circuit 70. C as signal
It is output to the diagnostic result signal input terminal SINI of the PU 50. As a result, the CPU 50 determines that the WDT 24 is operating normally, terminates the WDT diagnosis at time t5 after the time TSIN has elapsed from time t3, and returns the PRUN signal to normal.

On the other hand, when the WDT 24 has a failure, the WDT 24 does not output the abnormality detection signal as shown in FIG. Therefore, the abnormality detection signal is not output as the diagnosis result signal from the diagnosis result signal output terminal SINO,
It is not input to the CPU 50. Therefore, when the diagnosis result signal is not input to the diagnosis result signal input terminal SINI within the predetermined time TSIN from the WDT diagnosis start time t3, the CPU
50 determines that the WDT 24 is abnormal, and time t5
Then, the WDT diagnosis is completed.

[0015]

By the way, the above WD
At the time of T diagnosis, the CPU is not reset. That is, the diagnostic result signal is output from the dedicated diagnostic result signal output terminal SINO, not from the reset signal output terminal RESO. Where WDT is normal
Considering the case where the reset signal output terminal RESO of the DT diagnostic circuit 60 has an open failure, it is assumed that at the time of WDT diagnosis, the diagnostic status signal is input to the diagnostic status signal input terminal SINJI and the PRUN signal is deviated from the predetermined cycle. Therefore, the WDT 24 outputs the abnormality detection signal, but since the diagnosis state signal is at the H level, the abnormality detection signal is masked by the AND circuit 64, and the reset signal is not input to the reset signal input terminal RESB of the CPU 50. . That is, regardless of whether or not the reset signal output terminal RESO has an open failure, the CPU 50 is not reset during WDT diagnosis.

As described above, in the conventional WDT diagnostic system, since the diagnostic result signal is output from the diagnostic result signal output terminal SINO different from the reset signal output terminal RESO, the CPU is not reset during WDT diagnosis. Although the WDT 24 can be diagnosed, the WDT 24 reset signal output terminal RESO
It is not possible to judge whether or not there is a failure in the path leading up to, and further up to the reset signal input terminal RESB of the CPU 50.

Therefore, the present invention has been made in view of the above problems.
An object of the present invention is to provide a watchdog timer diagnostic system capable of diagnosing not only the watchdog timer but also the presence or absence of an abnormality in the circuit from this circuit to the reset signal input terminal.

[0018]

Therefore, according to the present invention of claim 1, when the pulse signal output from the CPU deviates from the predetermined period, the reset signal on the CPU side is generated based on the abnormality detection signal output from the watchdog timer. While inputting a reset signal to the input terminal, in the watchdog timer diagnosis system that outputs a pseudo abnormal signal from the CPU to diagnose the failure of the watchdog timer, input it to the reset signal input terminal when not diagnosing the watchdog timer. The reset signal level is set to a level lower than the L level maximum input voltage of the reset signal input terminal, and at the time of failure diagnosis of the watchdog timer, the reset signal level is set to a level higher than the H level minimum input voltage of the reset signal input terminal. At the same time, on the CPU side, reconnect to a terminal different from the reset signal input terminal. Enter the Tsu bets signals were assumed to watchdog timer based on a change of the reset signal makes a determination whether or not normal.

According to a second aspect of the present invention, the reset signal level at the time of failure diagnosis and at the time of non-fault diagnosis is switched based on the diagnosis status signal output from the CPU. According to a third aspect of the present invention, in particular, the resistance value is switched based on the diagnostic state signal, and the variable resistance means that can be grounded via the transistor controlled based on the output of the watchdog timer is connected to the power supply voltage. A reset signal output terminal is provided at a connection point between the first resistor and the variable resistance means, and the reset signal level is equal to the resistance value of the first resistor and that of the transistor. The power supply voltage is divided by the on-resistance and the resistance value of the variable resistance means.

According to a fourth aspect of the present invention, in particular, the variable resistance means comprises a second resistance provided in parallel with each other, and a switch whose ON resistance is lower than the second resistance and which is switched based on the diagnostic status signal. The switch is turned off to increase the resistance value at the time of failure diagnosis, and the switch is turned on to decrease the resistance value at the time of non-failure diagnosis.

[0021]

According to the first aspect of the present invention, a reset signal is output from the watchdog timer side, and this reset signal is also used as a diagnosis result signal on the CPU side. And
During diagnosis of the watchdog timer, the CPU is not reset by setting the reset signal level to a level higher than the H level minimum input voltage of the reset signal input terminal of the CPU. In addition, the CPU receives a reset signal at a terminal different from the reset signal input terminal, and the change in the signal determines whether the watchdog timer is normal, and whether a circuit failure from the watchdog timer to the reset signal input terminal occurs. Can also be determined.

On the other hand, at the time of non-diagnosis, it is possible to reset the CPU by setting the reset signal level to a level lower than the L level maximum input voltage of the reset signal input terminal of the CPU.

According to the second aspect of the present invention, since the reset signal level at the time of failure diagnosis and at the time of non-fault diagnosis is switched based on the diagnosis status signal from the CPU, it is complicated to determine the switching timing on the watchdog timer side. It does not require a special circuit. According to the invention of claim 3, a reset signal output terminal is provided at a connection point between the first resistance connected to the power supply voltage and the variable resistance means that can be grounded by a transistor, and the resistance value of the variable resistance means is determined based on the diagnostic state signal. , And the reset signal level is obtained by the divided voltage value. Therefore, the reset signal level can be switched with a simple configuration.

According to a fourth aspect of the present invention, the variable resistance means comprises a second resistor and a switch connected in parallel, the switch is turned off to increase the resistance value at the time of failure diagnosis, and the non-fault diagnosis is made at the time of non-failure diagnosis. Since the switch is turned on and its low on-resistance is used, reset signals of different levels can be obtained particularly simply by turning the switch on and off.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below. FIG. 1 is a block diagram showing a configuration of an embodiment of the invention. The CPU 10 operates at the power supply voltage VDD, can output a pulse signal PRUN of a predetermined cycle from the pulse signal output terminal PRNO, and outputs a diagnostic state signal for controlling WDT diagnosis from the diagnostic state signal output terminal SINJO. Then, a reset signal input terminal RESB that receives the reset signal from the WDT diagnostic circuit 20,
Similarly, a diagnostic result signal input terminal SI for receiving a reset signal
It has NI. The reset signal input terminal RESB and the diagnostic result signal input terminal SINI are respectively at the L level maximum input voltage VLmax and the L level minimum input voltage VLm.
The input range of the L level signal is between in and the H level maximum input voltage VHmax and the H level minimum input voltage VHmin.
The interval between them is the input range of the H level signal.

The WDT diagnosis circuit 20 is connected to a power supply input terminal VCC connected to the power supply voltage VDD, a pulse signal input terminal PRNI connected to the pulse signal output terminal PRNO of the CPU 10, and a diagnosis status signal output terminal SINJO. Diagnostic status signal input terminal SINJI and reset signal output terminal RESO for outputting a reset signal to the CPU 10.
Equipped with. Reset signal output terminal RESO of WDT diagnostic circuit 20 and reset signal input terminal RESB of CPU 10
The connection line between them is connected to the power supply voltage VDD via the resistor 34.

The WDT diagnostic circuit 20 has a power-on clear circuit 22 connected to the power supply input terminal VCC and a WDT 24 connected to the pulse signal input terminal PRNI. The WDT 24 determines that an abnormality has occurred when the input PRUN signal deviates from a predetermined cycle, and outputs an abnormality detection signal (here, an H level signal). The reset signal output terminal RESO is grounded from the resistor 30 via the transistor 28, and the switch 32 is provided in parallel with the resistor 30. The on resistance of the switch 32 is sufficiently smaller than the resistance 30 and the resistance 34. Power-on clear circuit 22 and W
Each output of the DT 24 is input to the OR circuit 26, and the output of the OR circuit 26 is connected to the gate of the transistor 28.

The switch 32 has its control terminal connected to the diagnostic state signal input terminal SINJI and is turned on / off by the diagnostic state signal. That is, the non-WDT diagnosis in which the diagnostic state signal is at the L level is in the on state, and the WDT diagnostic in which the diagnostic state signal is at the H level is in the off state. As a result, the resistor 30 and the switch 32 provided in parallel constitute variable resistance means whose overall resistance value changes as will be described later when the switch 32 is turned on and off. The above WDT diagnostic circuit 20 is configured as a dedicated ASIC.

When the transistor 28 is off, the CPU
A high-level (H-level) signal as a non-reset signal is applied to the reset signal input terminal RESB 10 and a reset signal input terminal R when the transistor 28 is on.
The ESB is configured to supply a low level (L level) signal as a reset signal.

The connecting line between the reset signal output terminal RESO and the reset signal input terminal RESB is also connected to the diagnostic result signal input terminal SINI of the CPU 10, and the reset signal is also input to the diagnostic result signal input terminal SINI as described above. It is supposed to be done. The heights of the H level and the L level of the reset signal output from the reset signal output terminal RESO of the WDT diagnostic circuit 20 change depending on whether the WDT is diagnosed or not.

FIG. 2A shows the reset signal level during non-WDT diagnosis, and FIG. 2B shows the reset signal level during WDT diagnosis. At the time of non-WDT diagnosis, the CPU 10 outputs the diagnosis state signal input terminal SINJI of the WDT diagnosis circuit 20.
The switch 32 is in the on-state because the diagnostic state signal input to is set to the L level. The pulse signal P from the CPU 10 input to the pulse signal input terminal PRNI
When the RUN deviates from the predetermined cycle, the WDT 24 determines that it is abnormal and outputs an abnormality detection signal (H level signal). Based on this abnormality detection signal, the output of the OR circuit 26 turns on the transistor 28.

At this time, the on resistance of the switch 32 is the resistance 3
Since it is sufficiently smaller (lower) than the resistance value of 0, the resistance value as the variable resistance means described above is substantially represented by the ON resistance of the switch 32. Thus, the reset signal output terminal R
The voltage level of the reset signal appearing in ESO is a voltage obtained by dividing the power supply voltage VDD by the resistance 34, the on resistance of the switch 32, and the on resistance of the transistor 28.
As for the resistance value of the on-resistance of the resistor 34 and the switch 32, the divided voltage level is, as shown in FIG. 2A, the L level maximum input voltage VLmax and L of the reset signal input terminal RESB of the CPU 10. Level minimum input voltage V
The ON resistance of the transistor 28 is also taken into consideration so as to be within the voltage range Va during Lmin. Therefore, the CPU 10 at the time of non-WDT diagnosis receives the reset signal at the reset signal input terminal RESB and is reset.

On the other hand, at the time of WDT diagnosis, the switch 32 is turned off because the diagnosis status signal input from the CPU 10 to the diagnosis status signal input terminal SINJI is at the H level. Also in this case, when the PRUN signal deviates from the predetermined cycle, the WDT 24 detects the abnormality and outputs the abnormality detection signal. Based on this abnormality detection signal, the output of the OR circuit 26 turns on the transistor 28.

At this time, the voltage level of the reset signal appearing at the reset signal output terminal RESO is the power supply voltage VDD.
Is divided by the resistance 34, the resistance 30 and the on-resistance of the transistor 28 to obtain a voltage. Resistor 34 and switch 32
Further, as for the resistance value of the on resistance of, the divided voltage level is, as shown in FIG. 2B, the H level maximum input voltage VHm of the reset signal input terminal RESB of the CPU 10.
It is set to be within a voltage range Vb between ax and the H level minimum input voltage VHmin. Therefore, WD
At the time of T diagnosis, the CPU 10 is not reset by the reset signal.

Next, FIG. 3 shows a time chart when the PRUN signal is normal during the non-WDT diagnosis in the present embodiment. The diagnostic status signal output from the diagnostic status signal output terminal SINJO of the CPU 10 and input to the diagnostic status signal input terminal SINJI of the WDT diagnostic circuit 20 is
This is a constant signal in the L level state because it is during non-WDT diagnosis. Therefore, the switch (SW) 32 is in the on state.

Since the PRUN signal input to the pulse signal input terminal PRNI of the WDT diagnostic circuit 20 is a normal predetermined pulse signal, the WDT2 input to the OR circuit 26 is input.
The output of 4 is in the L level state, and the power-on clear circuit 22
The transistor (TR) 28 is in an off state together with the off state. As a result, the reset signal of the reset signal output terminal RESO is a constant signal of H level which is a non-reset level state, and therefore the reset signal input terminal RESB and the diagnostic result signal input terminal SINI of the CPU 10 are in the H level state, , CPU10
Will never be reset.

On the other hand, the PR during non-WDT diagnosis
FIG. 4 shows a time chart when the UN signal is abnormal.
Similarly to the above, the switch 32 in the WDT diagnostic circuit 20 is in the ON state. Here, when the PRUN signal becomes abnormal at time t1 and a signal (here, a constant low level signal) deviating from the predetermined period is input to the pulse signal input terminal PRNI, the WDT 24 causes the PRUN abnormality detection time (TRES).
At time t2 after the passage of time, an abnormality detection signal (H level signal) is output, and the transistor 28 is switched from the off state to the on state via the OR circuit 26. Therefore, the voltage level at the reset signal output terminal RESO is determined by the reset signal input terminal RESB and the diagnostic result signal input terminal SINI.
To a height within a voltage range Va between the L level maximum input voltage VLmax and the L level minimum input voltage VLmin, and the CPU 10 is reset by this reset signal.

Next, a time chart when the WDT diagnosis is performed when the WDT is normal will be described with reference to FIG. The signal input to the diagnostic status signal input terminal SINJI is W
At time t3 when the DT diagnosis starts, the L level rises to the H level. As a result, the switch 32 is switched from the on state to the off state. At the same time, the PRUN signal output from the pulse signal output terminal PRNO of the CPU 10 becomes a low-level constant signal deviated from the predetermined cycle, so the WDT 24
Outputs an abnormality detection signal at time t4 after the abnormality detection time TRES has elapsed, and turns on the transistor 28.

At this time, the reset signal output terminal RESO
The voltage level of the reset signal at is slightly lowered to the height within the voltage range Vb between the H level maximum input voltage VHmax and the H level minimum input voltage VHmin of the reset signal input terminal RESB and the diagnostic result signal input terminal SINI. Therefore, although the CPU 10 is not reset by this reset signal, the CPU 10 detects the above voltage change input to the diagnostic result signal input terminal SINI and determines that the WDT 24 is operating normally. After that, the diagnosis ends at time t5. That is, WDT2
4 outputs the abnormality detection signal normally, and WDT2
4 to the reset signal output terminal RESO, and eventually C
It is determined that the WDT diagnostic circuit 20 is normal since there is no failure up to the diagnostic result signal input terminal SINI of the PU 10.

On the other hand, FIG. 6 shows that when the WDT is abnormal, the WD
It is a time chart at the time of implementing T diagnosis. In this case also, the switch 32 in the WDT diagnostic circuit 20 is in the off state. At the same time, the PRUN signal output from the pulse signal output terminal PRNO of the CPU 10 also becomes a signal deviated from the predetermined cycle, but if the WDT 24 is abnormal, the abnormality detection signal is not output. Therefore, the voltage level of the reset signal output terminal RESO is held at the H level which is the non-reset level state, and the CPU 10 is not reset. Then, since the reset signal is not input to the diagnosis result signal input terminal SINI within the predetermined time TSIN from the WDT diagnosis start time t3, the CPU 10 determines that the WDT 24 has an abnormality, and ends the WDT diagnosis at time t5.

The same applies when the WDT 24 is operating normally but the reset signal output terminal RESO has an open failure. That is, as in the case of FIG.
When the WDT diagnostic circuit 20 receives the diagnostic status signal, the time t3
Then, the switch 32 is turned off. And at the same time, CP
The PRUN signal output from the PRNO terminal 7 on the U5 side also becomes a signal deviated from the predetermined cycle, and the WDT 24 outputs the time TR.
After ES has passed, an abnormality detection signal is output. However, since the reset signal output terminal RESO has an open failure, the reset signal is not input to the reset signal input terminal RESB and the diagnostic result signal input terminal SINI of the CPU 10. Therefore, as in the case of FIG.
0 does not receive the reset signal within the predetermined time TSIN from the WDT diagnosis start time t3, so the WDT diagnosis circuit 2
It is determined that 0 is abnormal, and the WDT diagnosis is ended at time t5.

As described above, in the present embodiment, the WDT
Reset signal output terminal R of WDT diagnostic circuit 20 at the time of diagnosis
A reset signal is output from the ESO, and the CPU 10 side also uses this reset signal as a diagnostic result signal. Then, at the time of WDT diagnosis, the WD of the WDT diagnosis circuit 20
By outputting an abnormality detection signal to T24 and switching the switch 32 from the ON state to the OFF state, the CPU 1
0 reset signal input terminal RESB and diagnostic result signal input terminal SINI
Minimum H level input voltage VHmi of reset signal input terminal
Since the level is higher than n, it can be determined that the WDT diagnostic circuit has no abnormality without resetting the CPU 10.

On the other hand, when the WDT 24 has a failure or the reset signal output terminal RESO has an open failure, the reset signal is not input to the diagnosis result signal input terminal SINI within the predetermined time TSIN from the WDT diagnosis start time t3. , W without resetting the CPU 10
It can be detected that the DT diagnosis circuit 20 is abnormal.

The switch 32 is used for non-WDT diagnosis.
Is on, the reset signal level input to the reset signal input terminal RESB of the CPU 10 is set to the L level maximum input voltage VL of the input terminal RESB.
Since the level is between max and the L level minimum input voltage VLmin, the CPU 10 can be reset when the cycle of the PRUN signal from the CPU 10 is deviated.

Thus, not only the WDT 24 but also the WDT
Since the WDT diagnostic circuit 20 including the path from 24 to the reset signal output terminal RESO can be diagnosed and the reset signal is also used as the diagnostic result signal, the WDT diagnostic circuit 20 can output the diagnostic result. No separate circuit is required.

Although the embodiments have been described above, the present invention is not limited to the illustrated embodiments, and various modifications can be made without departing from the scope of the invention. For example, in the embodiment, the variable resistance means is composed of the resistor 30 and the switch 32, and the resistor 3 for the power supply voltage VDD is used.
0, the resistance 34, the on resistance of the switch 32, and the on resistance of the transistor 28, the reset signal input terminal RESB of the CPU 10 and the diagnostic result signal input terminal SI.
Although the reset voltage level of the NI is changed, the variable resistance means is replaced with a second switch having an ON resistance having the same resistance value as the resistance 30, and the variable resistance means is operated opposite to the ON / OFF control of the switch 32. You may do it.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an input voltage of a reset signal input terminal and a reset signal level.

FIG. 3 is a time chart when the pulse signal of the CPU is normal during non-diagnosis.

FIG. 4 is a time chart when the pulse signal of the CPU is abnormal during non-diagnosis.

FIG. 5 is a time chart when a diagnosis is performed when the watchdog timer is normal.

FIG. 6 is a time chart when the diagnosis is performed when the watchdog timer is abnormal.

FIG. 7 is a diagram showing a configuration of a conventional example.

FIG. 8 is a time chart when the pulse signal of the CPU is normal during non-diagnosis in the conventional example.

FIG. 9 is a time chart when the pulse signal of the CPU is abnormal during non-diagnosis in the conventional example.

FIG. 10 is a time chart in the case of performing diagnosis when the watchdog timer is normal in the conventional example.

FIG. 11 is a time chart when diagnosis is performed when a watchdog timer is abnormal in a conventional example.

[Explanation of symbols]

10 CPU 20 Watchdog timer diagnostic circuit 22 Power-on clear circuit 24 watchdog timer 26 OR circuit 28 transistors 30 resistance (second resistance) 32 switch 34 resistance (first resistance) 50 CPU 60 Watchdog timer diagnostic circuit 62 AND circuit 64 AND circuit 66 OR circuit 68 transistors 70 output buffer 74 resistance PRNI pulse signal input terminal PRNO pulse signal output terminal RESB reset signal input terminal RESO reset signal output terminal SINI Diagnostic result signal input terminal SINJI diagnostic status signal input terminal SINJO diagnostic status signal output terminal VCC power input terminal VDD power supply voltage VHmax H level maximum input voltage VHmin H level minimum input voltage VLmax L level maximum input voltage VLmin L level minimum input voltage

Claims (4)

[Claims] 1. When a pulse signal output from a CPU deviates from a predetermined cycle, a reset signal is input to a reset signal input terminal on the CPU side based on an abnormality detection signal output from a watchdog timer, while a pseudo abnormality is output from the CPU. In a watchdog timer diagnosis system that outputs a signal to perform failure diagnosis of the watchdog timer, at the time of non-fault diagnosis of the watchdog timer, the reset signal level input to the reset signal input terminal is set to the reset signal input terminal The level is lower than the L level maximum input voltage, and at the time of failure diagnosis of the watchdog timer, the reset signal level is higher than the H level minimum input voltage of the reset signal input terminal, and the CPU
On the side, the reset signal is input to a terminal different from the reset signal input terminal, and it is configured to determine whether the watchdog timer is normal based on a change in the reset signal. Watchdog timer diagnostic system. 2. The watchdog timer diagnostic system according to claim 1, wherein the reset signal level at the time of the fault diagnosis and at the time of the non-fault diagnosis is switched based on a diagnostic state signal output from the CPU. . 3. The resistance value is switched based on the diagnostic state signal, and variable resistance means that can be grounded via a transistor controlled based on the output of the watchdog timer and a first voltage source connected to a power supply voltage. The reset signal output terminal is provided at a connection point between the first resistor and the variable resistance means, and the reset signal level is set to the resistance value of the first resistor and that of the transistor. The watchdog timer diagnostic system according to claim 2, wherein the power supply voltage is divided by the on-resistance and the resistance value of the variable resistance means. 4. The variable resistance means comprises a second resistance provided in parallel with each other and a switch whose ON resistance is lower than that of the second resistance and which is switched based on the diagnosis status signal. 4. The watchdog timer diagnosis system according to claim 3, wherein the switch is turned off to increase the resistance value, and the switch is turned on to decrease the resistance value during non-fault diagnosis.