JP2007041824A - Resetting circuit for electronic control unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine the cause of resetting of CPUs using a resetting circuit for an electronic control unit having two CPUs. <P>SOLUTION: A main reset generating part 13 outputs a reset signal RSa whose pulse width varies depending on whether a voltage drop in the output of a power supply circuit 15 is detected or runaway is detected through the monitoring of a WDT signal coming from a main CPU. A sub reset generating part 14 also has the function of detecting the low voltage of a power supply. A threshold Vtha for detecting low voltages at the main reset generating part 13 is set to be higher than a threshold Vthb for detecting low voltages at the sub reset generating part 14; a voltage drop at the power supply is first detected by the main reset generating part 13 and then the main CPU 11 is reset. The sub reset generating part 14 monitors the reset signal RSa outputted by the main reset generating part 13, and determines whether the cause of a reset is a voltage drop at the power supply or the runaway of the main CPU 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a reset circuit for an electronic control unit, and more particularly to a reset circuit for a CPU in an electronic control unit having two CPUs for mutual monitoring.

When a CPU runaway occurs in the electronic control unit, the CPU is reset and then restarted to obtain normal operation. The CPU reset is also executed when there is a possibility that the CPU does not perform a normal function due to a decrease in power supply voltage.
Such a CPU reset is performed even in the case where two CPUs are provided and the operation is monitored between them in order to ensure a stable operation of the electronic control unit. For example, in the electronic control unit disclosed in Japanese Patent Application Laid-Open No. 4-291610, when a reset condition is established for one CPU, the other CPU is also reset at the same time, and then restarted again.
JP-A-4-291610

However, in the above-mentioned conventional electronic control unit, since both of the two CPUs are reset, it is restarted without knowing the cause of the reset, whether it is due to the runaway of the CPU, the power supply voltage or the like. End up. If the reset is caused by a voltage drop, there is no abnormality in the CPU. However, since the identification cannot be performed, there is a problem that the CPU abnormality cannot be accurately determined.
Even when both CPUs are reset individually, only one CPU is reset due to a circuit error and restarted despite the fact that the threshold value for detecting a drop in power supply voltage is set to be the same. In such a case, the CPU may be erroneously determined that the other CPU is abnormal.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a reset circuit capable of determining the cause of CPU reset in an electronic control unit including two CPUs.

  According to the present invention, the first reset generation unit for resetting the first CPU has a plurality of abnormality detection functions including a low voltage detection function of a power supply, and a reset signal having a pulse width that differs for each abnormality at the time of abnormality detection The second reset generation unit that resets the second CPU has a function of detecting a low voltage of the power source, and outputs a reset signal when the low voltage of the power source is detected. In the first reset generation unit, The low voltage detection threshold value and the low voltage detection threshold value in the second reset generation unit are set so that the first reset generation unit detects the voltage drop of the power supply earlier than the second reset generation unit. It is assumed that the second CPU monitors the reset signal from the first reset generation unit.

  Even if the first reset generator detects the voltage drop of the power supply and resets the first CPU, the second reset generator is set not to output a reset signal for resetting the second CPU at the same time. Therefore, the second CPU can monitor the reset signal output from the first reset generation unit, and can correctly determine the cause of the abnormality based on the pulse width of the reset signal.

Next, embodiments of the present invention will be described by way of examples.
FIG. 1 is a diagram showing a configuration of an embodiment in which the present invention is applied to an electronic control unit for a vehicle.
The electronic control unit 10 stores a program for controlling an in-vehicle device (not shown) and executes various necessary calculations, and a sub CPU 12 that is connected to the main CPU 11 so as to communicate with each other and executes the same calculations. The main reset generator 13 and the sub-reset generator 14 are connected to each other, and the main reset generator 13 and the sub-reset generator 14 are connected to the power supply circuit 15 respectively.
The power supply circuit 15 is connected to a battery power supply (battery voltage VB) and converts the battery voltage VB into an operating voltage Vcc in the electronic control unit 10.

The main CPU 11 and the sub CPU 12 output a WDT signal from their output terminals (OUT). The WDT signal is a pulse having a predetermined period Twd while each CPU is operating normally. When an abnormality occurs in which the CPU runs away, the pulse stops.
The main reset generator 13 and the sub-reset generator 14 each have a watchdog timer function and a power supply low voltage detection function.

The main CPU 11 outputs the WDT signal to the main reset generator 13 and receives the reset signal RSa from the main reset generator 13 at its reset terminal (R).
Similarly, the sub CPU 12 outputs the WDT signal to the sub reset generation unit 14 and receives the reset signal RSb from the sub reset generation unit 14 at its reset terminal. The sub CPU 12 also receives a reset signal RSa from the main reset generator 13 at its input terminal (IN).

  The main reset generator 13 normally outputs an H (high) signal to the reset terminal of the main CPU 11 as the reset signal RSa. The power supply voltage is monitored, and while the power supply voltage Vmain (= Vcc) supplied from the power supply circuit 15 to the main reset generation unit 13 is lower than the threshold value Vtha, the reset signal RSa is set to L (low) level. When the power supply voltage Vmain becomes equal to or higher than the threshold value Vtha, the reset signal RSa is held at the L level for the time Trs1 from that point.

The main reset generator 13 further monitors the WDT signal from the main CPU 11 and outputs an L level of a predetermined length Trs2 when the pulse stops.
That is, in the main reset generator 13, in the built-in CR circuit 20 including the resistor R1 and the capacitor C1, the terminal voltage Vt of the capacitor C1 is repeatedly charged and discharged between Vwh and Vwl. When the WDT signal from the main CPU 11 is received before the voltage reaches Vwh, the signal returns to Vwl, and the terminal voltage Vt of the capacitor does not reach Vwh while the WDT signal is input in a regular cycle. When the pulse of the WDT signal is lost, the terminal voltage Vt of the capacitor reaches Vwh, and the main reset generator 13 sets the reset signal RSa to L level.

The sub-reset generation unit 14 also includes a CR circuit 21 having the same configuration as the CR circuit 20, and normally outputs an H signal to the reset terminal of the sub CPU 12 as the reset signal RSb. The power supply voltage is monitored, and while the power supply voltage Vsub (= Vcc) supplied from the power supply circuit 15 to the sub-reset generation unit 14 is lower than the threshold value Vthb, the L level is output, while the power supply voltage Vsub is When the threshold value Vthb is exceeded, the reset signal RSb is held at the L level for the time Trs1 from that point.
The sub-reset generation unit 14 further monitors the WDT signal from the sub CPU 12, and outputs an L level of length Trs2 when the pulse stops.
The pulse length Trs2 of the reset signals RSa and RSb at the time of CPU runaway detection is set to be significantly shorter than the pulse length at the time of low voltage detection, as will be described later.

Here, the threshold value for detecting the low voltage in the main reset generation unit 13 and the sub reset generation unit 14 is Vtha> Vthb.
Therefore, the main reset generation unit 13 always detects a drop in the power supply voltage before the sub-reset generation unit 14. Vthb is set to a value sufficiently lower than the voltage value that temporarily decreases.

Hereinafter, the flow of the CPU reset control in the electronic control unit 10 having the above configuration will be described with reference to the timing chart of FIG.
This reset control is started when an ignition switch (not shown) of the vehicle is turned on.
When the power supply voltages Vmain and Vsub (both Vcc) are output from the power supply circuit 15 at time t0 based on the battery voltage VB, charging of the capacitor C1 of the CR circuit 20 of the main reset generation unit 13 is started. The terminal voltage Vt increases. When the terminal voltage Vt of this capacitor reaches Vwh (for example, 4V), the capacitor is discharged to Vwl (for example, 2V), and charging / discharging is repeated between the maximum widths Vwh to Vwl.

The reset signal RSa from the main reset generator 13 is at the L level during the time Trs1 including the period from the time t0 until the terminal voltage Vt reaches Vwh, and the reset signal RSa is at the time t1 when the time Trs1 has elapsed. Change to H level.
Although a change in terminal voltage in the CR circuit 21 of the sub-reset generation unit 14 is not particularly shown, similarly, the reset signal RSb changes to the H level at time t1.

During charging / discharging in the CR circuit 20, the terminal voltage Vt returns to Vwl every time the WDT signal is received, and does not reach Vwh.
For example, in order to start the engine, when the ignition switch is turned from the ON position to the START (start) position and the starter motor is driven and cranked, the battery voltage VB temporarily decreases. Along with this, the power supply voltage Vcc (Vmain, Vsub) output from the power supply circuit 15 also decreases.
When the power supply voltage Vmain (= Vcc) falls below the threshold value Vtha in the main reset generation unit 13 at time t2 due to this decrease, the reset signal RSa from the main reset generation unit 13 becomes L level. Thereby, the main CPU 11 is reset.

  On the other hand, since the power supply voltage Vsub (= Vcc), which has decreased as the battery voltage temporarily decreases, does not fall below the threshold value Vthb in the sub-reset generation unit 14, the reset signal from the sub-reset generation unit remains at the H level. There is no change.

  When the power supply voltage Vmain recovers to the threshold value Vtha or more at time t3 after the CR circuit 20 has completely discharged, the reset signal RSa is held at the L level from that time until time t4 when Trs1 elapses. The CR circuit 20 resumes charging of the capacitor C1 from time t3, and the terminal voltage Vt returns to the charge / discharge repetition level between Vwh and Vwl while the reset signal RSa is at the L level. Thereafter, the reset signal RSa returns to the H level at time t4.

On the other hand, even when the power supply voltage Vmain is higher than the threshold value Vtha in the main reset generation unit 13, if a missing pulse occurs in the WDT signal from the main CPU 11, the terminal voltage Vt of the CR circuit 20 continues to increase and reaches Vwh. At time t5, the main reset generator 13 sets the reset signal RSa to L level. The L-level pulse width is Trs2. Thereby, the main CPU 11 is reset.
Note that the length at which the reset signal RSa is set to the L level, that is, the pulse width is determined by a constant of the CR circuit 20, for example, Trs1 = 1.6 × C × R
Trs2 = 0.3 × C
(Where C is the capacitance value of the capacitor C1, and R is the resistance value of the resistor R1.)
Set to

  During this time, the sub CPU 12 inputs and monitors the reset signal RSa from the main reset generation unit 13 to the input terminal IN, and detects that the main CPU 11 is reset when the reset signal RSa becomes L level. Based on whether the L-level pulse width is Trs1 or more or Trs2, it is possible to determine whether the reset of the main CPU 11 is a reset due to a low voltage or a reset due to a missing pulse of the WDT signal. .

When the reset is due to a missing pulse of the WDT signal from the main CPU 11, it is assumed that an operation abnormality has occurred in the main CPU 11, for example, and a transition is made to a fail operation. Alternatively, if there is no problem based on the result of the initial check executed after the main CPU 11 is restarted, the control operation can be resumed.
If the reset is due to a drop in power supply voltage, the control operation is temporarily stopped, and the control operation is resumed after the main CPU 11 is restarted.

In the present embodiment, the main CPU 11 corresponds to the first CPU in the invention, and the sub CPU 12 corresponds to the second CPU. The main reset generation unit 13 corresponds to a first reset generation unit, and the sub-reset generation unit 14 corresponds to a second reset generation unit.
The length of the L level section of the reset signals RSa and RSb is the pulse width of the reset signal for resetting the first CPU and the second CPU.

  The embodiment is configured as described above, and the main reset generation unit 13 for resetting the main CPU 11 has a low voltage detection function for detecting a voltage drop of the power source and a runaway detection function for detecting a runaway of the main CPU 11. The sub-reset generation unit 14 that outputs a reset signal RSa having a different pulse width at the time of voltage drop detection and at the time of runaway detection and resets the sub CPU 12 has a power source low voltage detection function. It is assumed that the reset signal RSb is output at the time of detection, and the low voltage detection threshold value in the main reset generation unit 13 and the low voltage detection threshold value in the sub reset generation unit 14 indicate that the power supply voltage drop is caused by the sub reset generation unit 14. Since the main reset generator 13 is set so that it is detected earlier than the main reset generator 13, the main reset generator 13 Even if the main CPU 11 is reset by detecting the bottom, the sub reset generation unit 14 does not output a reset signal for resetting the sub CPU 12, so the sub CPU 12 may monitor the reset signal RSa output by the main reset generation unit 13. It is possible to determine whether the cause of the reset is a voltage drop of the power supply or a runaway of the main CPU 11 based on the pulse width of the reset signal RSa.

  In addition, when only one of the two CPUs is reset and restarted, there is an example in which the other CPU misidentifies the restarted CPU as a failure. Since the main CPU 11 is reset by detecting the decrease, it is not mistaken for the failure of the main CPU 11 only by resetting and restarting only the main CPU 11.

  Since the runaway of the main CPU 11 is detected based on, for example, a periodic WDT signal, the pulse width of the reset signal RSa at that time is preferably short. Therefore, when the main reset generator 13 detects a low voltage of the power supply The pulse width of the reset signal RSa to be output is set to be longer than the pulse width of the reset signal RSa to be output when the runaway of the main CPU 11 is detected, thereby making it easy to determine the cause of the reset.

  The main reset generator 13 and the sub-reset generator 14 are supplied with power from a common power supply circuit 15, and the low-voltage detection threshold Vtha in the main reset generator 13 is lower than the low-voltage detection threshold Vthb in the sub-reset generator 14. Therefore, when the power supply voltage decreases, the main reset generation unit 13 reliably detects this first and outputs the reset signal RSa, while the sub CPU 12 that is not reset resets from the main reset generation unit 13. The pulse width of the signal RSa can be confirmed.

In the above embodiment, the power supply circuit 15 is shared by both the main CPU 11 and the sub CPU 12, and the power supply voltage Vmain supplied to the main reset generating unit 13 and the power supply voltage supplied to the sub reset generating unit 14 are used. Although Vsub is the same for all Vcc, the present invention can be applied to an electronic control unit 10A provided with different power supply circuits for each system as shown in FIG.
Hereinafter, this modification will be described.

  In this modification, capacitors Ca and Cb for setting the low voltage detection order are provided between the output of the power supply circuit 15A and the ground and between the output of the power supply circuit 15B and the ground, respectively. Before the power supply voltage Vsub supplied from the power supply circuit 15B to the sub-reset generation unit 14 falls below the threshold value Vthb, the power supply voltage Vmain supplied from the power supply circuit 15A to the main reset generation unit 13 falls below the threshold value Vtha. What is necessary is just to set the combination of each threshold value Vtha and Vthb and the capacity | capacitance of capacitor | condenser Ca and Cb.

For example, even if the power supply voltages Vmain and Vsub are set to be the same and the threshold values Vtha and Vthb are also set to be the same, the capacitance of the capacitor Cb between the output of the power supply circuit 15A and the ground is set to the capacitor Ca between the output of the power supply circuit 15A and the ground. When the power supply voltage Vmain, Vsub is reduced, the discharge rate on the side with the smaller capacity is increased when the power supply voltages Vmain, Vsub are lowered, and the main reset generation unit 13 detects the voltage drop first.
Other configurations are the same as those of the embodiment of FIG.

  As described above, even when different power supply circuits 15A and 15B are provided for each system, the detection timing of the power supply voltage drop can be shifted between the main reset generation unit 13 and the sub-reset generation unit 14, and simultaneously with the main CPU 11. By monitoring the reset signal RSa from the main reset generation unit 13 by the sub CPU 12 that is not reset, the reset of the main CPU 11 is caused by a low voltage based on whether the L level length is Trs1 or more or Trs2. It is possible to determine whether the reset is due to a missing pulse of the WDT signal, that is, a reset due to runaway.

In the embodiment and the modification, the example applied to the vehicle electronic control unit has been described. However, the present invention is not limited to the vehicle and can be applied to reset circuits of various electronic control units. it can.
In addition, the reset signal output from the main reset generation unit 13 and the sub-reset generation unit 14 is normally at the H level, and the corresponding CPU is reset by setting it to the L level. However, the present invention is not limited to this. Alternatively, it may be at the L level when normal and at the H level when the CPU is reset.

It is a figure which shows the structure of embodiment of this invention. It is a timing chart which shows the flow of reset control. It is a figure which shows a modification.

Explanation of symbols

10, 10A Electronic control unit 11 Main CPU (first CPU)
12 Sub CPU (second CPU)
13 Main reset generator (first reset generator)
14 Sub-reset generator (second reset generator)
15, 15A, 15B Power supply circuit 20, 21 CR circuit

Claims (6)

In an electronic control unit comprising a first CPU and a second CPU,
A first reset generation unit having a plurality of abnormality detection functions including a low voltage detection function of a power supply, and outputting a reset signal having a different pulse width for each abnormality at the time of abnormality detection, and resetting the first CPU;
A second reset generation unit that has a power source low voltage detection function and outputs a reset signal when the power source low voltage is detected to reset the second CPU;
The threshold for low voltage detection in the first reset generation unit and the threshold for low voltage detection in the second reset generation unit are such that the first voltage drop in the power supply occurs earlier than the second reset generation unit. Set to be detected by the
A reset circuit for an electronic control unit, wherein the second CPU is configured to monitor a reset signal from the first reset generation unit and determine a cause of abnormality based on a pulse width of the reset signal. . 2. The electronic control unit according to claim 1, wherein the first reset generation unit includes a low voltage detection function of the power supply and a runaway detection function of the first CPU as the plurality of abnormality detection functions. Reset circuit. The pulse width of the reset signal output when the first reset generation unit detects a low voltage of the power supply is set longer than the pulse width of the reset signal output when the runaway of the first CPU is detected. 3. A reset circuit for an electronic control unit according to claim 2, wherein: The first reset generator and the second reset generator are powered from a common power circuit,
4. The low voltage detection threshold value in the first reset generation unit is set higher than the low voltage detection threshold value in the second reset generation unit. 5. The reset circuit of the electronic control unit described. The first reset generation unit and the second reset generation unit are supplied with power from individual power supply circuits having a common power source,
A capacitor is provided between the output of each power supply circuit and the ground, and the power supply voltage supplied to the second reset generation unit is reduced to a low voltage detection threshold value in the second reset generation unit due to circuit constants. 4. The power supply voltage supplied to the first reset generation unit early is set to drop to a threshold value for detecting a low voltage in the first reset generation unit. The reset circuit of the electronic control unit described in 1. A first reset generation unit that includes a first CPU and a second CPU and outputs a reset signal for resetting the first CPU; and a second that outputs a reset signal for resetting the second CPU In an electronic control unit having a reset generation unit of
The first reset generation unit detects a plurality of abnormalities including a power supply voltage drop, and varies the pulse width of a reset signal for resetting the first CPU for each abnormality,
The second reset generator also detects a power supply voltage drop and outputs a reset signal for resetting the second CPU,
The threshold for low voltage detection in the first reset generation unit and the threshold for low voltage detection in the second reset generation unit are such that the first voltage drop in the power supply occurs earlier than the second reset generation unit. Set to be detected by the
A method for resetting an electronic control unit, characterized in that a second CPU monitors a reset signal from a first reset generation unit and determines a cause of an abnormality based on a pulse width of the reset signal.

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