CN110928220A - Monitoring method and monitoring circuit - Google Patents
Monitoring method and monitoring circuit Download PDFInfo
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- CN110928220A CN110928220A CN201911146091.9A CN201911146091A CN110928220A CN 110928220 A CN110928220 A CN 110928220A CN 201911146091 A CN201911146091 A CN 201911146091A CN 110928220 A CN110928220 A CN 110928220A
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- control signal
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- monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24024—Safety, surveillance
Abstract
The present disclosure provides a monitoring method applied to a monitoring circuit, including: acquiring a first control signal related to the starting time of a monitored circuit system; generating a third control signal according to the first control signal and the second control signal, wherein the state of the second control signal is different based on whether a predetermined signal from the monitored circuit system is received in each predetermined time length; based on the third control signal, it is determined whether to generate a reset signal for the monitored circuitry. The present disclosure also provides a corresponding monitoring circuit. The monitoring scheme disclosed by the invention can overcome the defect that the traditional monitoring circuit can cause repeated restart of a monitored circuit system.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a monitoring method and a monitoring circuit for an integrated circuit.
Background
In an integrated circuit system, for example, a microcomputer system including a single chip microcomputer, the single chip microcomputer is easily interfered by the outside, so that the operation of a circuit is disordered, and the whole circuit falls into a dead cycle. Therefore, a monitoring circuit called watchdog is commonly used to monitor the integrated circuit system. The watchdog has the function of regularly checking the running condition of the singlechip system and sending a restart signal to the system once an error of the system is monitored.
The watchdog circuit monitors whether the integrated circuit system is in a dead cycle by using a fixed timeout, the integrated circuit system in normal operation outputs a signal to the watchdog circuit (commonly called "feeding dog") at regular intervals, and if the time interval of the signal received by the watchdog circuit does not exceed the timeout, the timing monitoring is restarted. A typical value of timeout for a chip of such a watchdog circuit is 1.6 s. When the integrated circuit system adopts the hardware architecture of ARM and Linux, the starting time of the whole circuit system exceeds the dog feeding time limit of the watchdog chip, so that the watchdog circuit sends a reset signal to the system before the dog feeding program of the system runs, and the whole system is restarted, namely, the system enters an infinite restart/reset dead cycle once being started.
Fig. 1 is a schematic circuit diagram of a prior art monitoring circuit. FIG. 1 illustrates a conventional design scheme using SP706SEN _ L _ TR watchdog chip as an example:
the SYS-RESETn signal is a reset signal output by the watchdog chip, and the WDI signal is a dog feeding signal output to the watchdog chip by the system CPU. Originally, within a fixed timeout time of 1.6s, if the WDI signal has a transition of high and low levels, the watchdog internal timer can be cleared to zero, and no reset signal is output. However, in the hardware architecture of ARM and Linux, since the BOOTLOADER of the Linux operating system employs U-BOOT, in the process from U-BOOT to Linux kernel, the timer interrupt needs to be closed, the system CPU cannot run the dog feeding program, and the time is greater than 1.6s, the watchdog circuit will send a reset signal to the system before the system is started, so that the whole system is restarted repeatedly.
Disclosure of Invention
In view of the problems in the background art, the present disclosure provides a monitoring method and a monitoring circuit, which aim to avoid repeated start-up when a specific integrated circuit system is started for longer than a predetermined monitoring period.
Therefore, an embodiment of the present invention provides a monitoring method applied to a monitoring circuit, including: acquiring a first control signal related to the starting time of a monitored circuit system; generating a third control signal according to the first control signal and the second control signal, wherein the state of the second control signal is different based on whether a predetermined signal from the monitored circuit system is received in each predetermined time length; based on the third control signal, it is determined whether to generate a reset signal for the monitored circuitry.
Optionally, the first control signal switches the signal state in real time after the monitored circuit system is started.
Optionally, the first control signal is obtained by the monitoring circuit from the monitored circuitry.
Optionally, the first control signal switches the signal state according to whether a predetermined starting time length is reached.
Optionally, a logic gate circuit unit is used to generate a third control signal according to the first control signal and the second control signal.
The embodiment of the present invention further provides a monitoring circuit, configured to monitor a monitored circuit system, where the monitoring circuit includes: an acquisition unit configured to acquire a first control signal related to a start-up duration of the monitored circuitry; a generation unit connected to receive the first control signal and configured to generate a third control signal according to the first control signal and a second control signal, a state of the second control signal being different based on whether a predetermined signal from the monitored circuitry is received every predetermined time period; a reset unit connected to receive the third control signal and configured to determine whether to send a reset signal to the monitored circuitry based on the third control signal.
Optionally, the obtaining unit is configured to obtain the first control signal from the monitored circuitry.
Optionally, the obtaining unit is configured to generate the first control signal in different states according to whether a start-up completion signal is received from the monitored circuitry.
Optionally, the generating unit is a logic gate circuit unit.
Optionally, the generating unit is a controlled switching circuit unit.
According to the embodiment of the invention, whether the reset signal is sent to the monitored circuit system is determined by the third control signal generated based on the first control signal and the second control signal, the starting time of the monitored circuit system can be taken into account in the monitoring process, and the reset signal is not sent to the monitored circuit system during the starting period of the monitored circuit system, so that the repeated starting when the starting time of the monitored circuit system is longer than the monitoring period is effectively avoided.
Drawings
In order that the invention may be more readily understood, it will be described in more detail with reference to specific embodiments thereof that are illustrated in the accompanying drawings. These drawings depict only typical embodiments of the invention and are not therefore to be considered to limit the scope of the invention.
FIG. 1 is a schematic circuit diagram of a prior art monitoring circuit;
FIG. 2 is a schematic flow chart diagram illustrating one embodiment of a monitoring method of the present invention;
FIG. 3 is a schematic block diagram of one embodiment of a monitoring circuit of the present invention;
FIG. 4 is a schematic circuit diagram of one embodiment of a monitoring circuit of the present invention.
Detailed Description
Embodiments of the present invention will now be described with reference to the drawings, wherein like parts are designated by like reference numerals. The embodiments described below and the technical features of the embodiments may be combined with each other without conflict.
FIG. 2 is a schematic flow chart diagram illustrating one embodiment of a monitoring method of the present invention. The monitoring method of the embodiment is applied to a monitoring circuit, and as shown in fig. 2, the method includes:
s101, acquiring a first control signal related to the starting time of a monitored circuit system;
s102, generating a third control signal according to the first control signal and the second control signal, wherein the state of the second control signal is different based on whether a preset signal from the monitored circuit system is received in each preset time length;
and S103, determining whether to send a reset signal to the monitored circuit system based on the third control signal.
Referring to fig. 1, the predetermined signal from the monitored circuitry in S102 of this embodiment is a WDI signal (feeding dog signal), and the second control signal is a WDO signal in the conventional monitoring circuit. In the conventional monitoring circuit shown in fig. 1, when the no-transition time of the WDI signal reaches the monitoring period (timeout time), the WDO terminal outputs a low level signal to the MR terminal, which triggers the RESET terminal to output a RESET signal SYS-RESETn to the monitored circuit system. That is, in the conventional monitoring circuit, whether to transmit the reset signal to the monitored circuit is determined only based on the second control signal.
In contrast, in the present embodiment, whether to send the reset signal to the monitored circuit is determined according to the third control signal, and the third control signal is generated according to the first control signal and the second control signal, and the first control signal is related to the start-up time length of the monitored circuit. Therefore, in this embodiment, the state of the first control signal may be set such that the third control signal is in an inactive state as the reset signal trigger signal before the monitored circuitry completes the start-up, and the state of the first control signal changes after the monitored circuitry completes the start-up such that the third control signal generated at this time becomes an active reset signal trigger signal.
Therefore, by the embodiment of the invention, the starting time of the monitored circuit system can be taken into consideration during monitoring, and the reset signal is not sent to the monitored circuit system during the starting of the monitored circuit system, so that the repeated starting when the starting time of the monitored circuit system is longer than the monitoring period is effectively avoided.
In some embodiments of the present invention, the first control signal may switch the signal state in real time after the monitored circuitry completes booting. In other words, the signal state of the first control signal may vary depending on whether the monitored circuitry actually completes the startup.
Specifically, as an embodiment, the first control signal may be generated by the monitored circuitry in real time and transmitted to the monitoring circuit, and the real-time status of the first control signal acquired by the monitoring circuit from the monitored circuitry may reflect whether the monitored circuitry is currently during startup or has completed startup.
As another embodiment, the first control signal may be generated by a signal generator included in the monitoring circuit or additionally added, the monitored circuitry may transmit an indication signal indicating that the startup is completed to the signal generator when the startup is completed, and the signal generator may generate the first control signal in a first state before receiving the indication signal from the monitored circuitry and switch the generated first control signal from the first state to a second state after receiving the indication signal from the monitored circuitry. In this embodiment, the indication signal sent by the monitored circuit system to the monitoring circuit may be the first feedback signal (i.e., the dog feeding signal) or may be another dedicated signal independent of the feedback unit (the dog feeding program).
In some embodiments of the present invention, the first control signal may also switch the signal state according to whether a predetermined start-up time period is reached, the start-up time period may be measured and determined by starting up the monitored circuitry a plurality of times in advance, for example, an average start-up time period or a longest start-up time period of the monitored circuitry or a value greater than the longest start-up time period may be used as the start-up time period of the monitored circuitry. After the start-up period of the monitored circuit system has been determined, a timer may be provided in the monitoring circuit or in the monitored circuit system, for example, which timer is used to output a first control signal in a first state and to switch the state of the first control signal to a second state after the start-up period has elapsed. Optionally, in this embodiment, the timer and the signal generator may be set simultaneously, so that the signal generator outputs the first control signal in the first state first and switches the state of the first control signal to the second state after receiving the signal indicating that the start duration has elapsed from the timer.
In some embodiments of the present invention, in generating the third control signal, a logic gate circuit unit may be used, the first control signal and the second control signal being input to an input terminal of the logic gate circuit unit, and an output signal of the logic gate circuit unit being the third control signal.
In other embodiments of the present invention, when generating the third control signal, the controlled switch circuit unit may be used, the first control signal may be input to the control terminal of the controlled switch circuit unit, and the second control signal may be input to one terminal of the controlled switch circuit unit, so that when the first control signal is in the first state indicating that the monitored circuit system is during the start-up period, the controlled switch circuit unit is controlled to be in the on state, and the second control signal cannot be transmitted to the other terminal thereof through the controlled switch circuit unit, so that the monitoring circuit temporarily stops performing the normal monitoring on the operation state of the monitored circuit system; and when the first control signal is in a second state indicating that the monitored circuit system is started, the controlled switch circuit unit is controlled to be in a closed state, and the second control signal can be transmitted to the other end of the controlled switch circuit unit through the controlled switch circuit unit to serve as a third control signal, so that the monitoring circuit enters a stage of performing conventional monitoring on the running state of the monitored circuit system.
FIG. 3 is a schematic block diagram of one embodiment of a monitoring circuit of the present invention. The monitoring circuit 1 of the present embodiment is used to monitor the monitored circuitry 2.
As shown in fig. 3, the monitoring circuit 1 of the present embodiment includes an acquisition unit 11, a generation unit 12, and a reset unit 13.
The acquisition unit 11 is configured to acquire a first control signal related to a start-up time period of the monitored circuitry 2.
The generating unit 12 is connected to receive the first control signal and configured to generate a third control signal according to the first control signal and a second control signal, a state of the second control signal being different based on whether a predetermined signal from the monitored circuitry 2 is received every predetermined time period.
The reset unit 13 is connected to receive the third control signal and configured to determine whether to send a reset signal to the monitored circuitry 2 based on the third control signal.
Unlike the conventional monitoring circuit in which the reset unit determines whether to send the reset signal to the monitored circuit only based on the second control signal, the reset unit 13 in this embodiment determines whether to send the reset signal to the monitored circuit 2 based on the third control signal generated based on the first control signal and the second control signal, the first control signal being related to the start-up time period of the monitored circuit system. Therefore, in this embodiment, the state of the first control signal may be set such that the third control signal is in an inactive state as the reset signal trigger signal before the monitored circuitry completes the start-up, and the state of the first control signal changes after the monitored circuitry completes the start-up such that the third control signal generated at this time becomes an active reset signal trigger signal.
Therefore, by the embodiment of the invention, the starting time of the monitored circuit system can be taken into consideration during monitoring, and the reset signal is not sent to the monitored circuit system during the starting of the monitored circuit system, so that the repeated starting when the starting time of the monitored circuit system is longer than the monitoring period is effectively avoided.
In an embodiment of the invention, the obtaining unit 11 is configured to obtain the first control signal from the monitored circuitry 2. In this embodiment, the first control signal in different states generated by the monitored circuitry 2 according to whether the start-up is completed is sent to the monitoring circuit 1, and the state of the first control signal acquired by the monitoring circuit 1 from the monitored circuitry 2 may reflect whether the monitored circuitry 2 is currently during the start-up or has completed the start-up. According to the foregoing embodiment, the monitored circuit system 2 may switch the state of the generated first control signal in real time according to whether the start-up is completed, or may count fixedly according to a predetermined start-up time period to generate the first control signal in different states.
In another embodiment of the present invention, the obtaining unit 11 may be configured to generate the first control signal in different states according to whether the start-up completion signal is received from the monitored circuitry. In the present embodiment, the first control signal is generated by the circuit unit on the monitoring circuit side, and the signal state of the generated first control signal is switched depending on whether or not the indication signal indicating the completion of the activation is received from the monitored circuit system 2. Likewise, according to the foregoing embodiment, the monitored circuit system 2 may send the indication signal to the obtaining unit 11 in real time when the activation is completed, or may count fixedly according to a predetermined activation time period to generate the indication signal to send to the obtaining unit 11, so that the obtaining unit 11 switches the signal state of the generated first control signal.
In some embodiments of the present invention, the generating unit 12 may be a logic gate unit, the first control signal and the second control signal are input to an input terminal of the logic gate unit, and an output signal of the logic gate unit is transmitted to the resetting unit 13 as the third control signal.
In other embodiments of the present invention, the generating unit 12 may be a controlled switch circuit unit, and the first control signal may be input to a control terminal of the controlled switch circuit unit, and the second control signal may be input to one terminal of the controlled switch circuit unit, as described in detail in the foregoing embodiments.
FIG. 4 is a schematic circuit diagram of one embodiment of a monitoring circuit of the present invention.
As shown in fig. 4, in the monitoring circuit, the obtaining unit 11 shown in fig. 3 is implemented as a signal interface and configured to obtain a WD _ CTR signal as a first control signal from the monitored circuitry, the generating unit 12 is implemented as a logic gate unit (SN 74AUP1G32 logic gate chip in fig. 4) that receives the first control signal and a second control signal output from a WDO terminal, and the resetting unit 13 is an on-chip circuit between an MR terminal and a RESET terminal (same as the conventional scheme). And when the signal from the monitored circuit system received by the WDI end in the monitoring period (1.6s) has no state transition, triggering the WDO end to output a second control signal with low level. At this time, since the MR terminal is active at a low level, the MR terminal needs to receive a high level signal during the start period in order not to transmit a RESET signal to the monitored circuit system during the start period of the monitored circuit system, so that the MR terminal can output a high level first control signal WD _ CTR to the monitoring circuit during the start period of the monitored circuit system, and the logic gate circuit unit can be implemented as an or gate, the MR terminal is connected to an output terminal of the or gate, an input terminal of the or gate is respectively a low level second control signal output by the WDO terminal and a high level first control signal WD _ CTR, or an output terminal of the or gate is a high level, so that the MR terminal receives a high level signal during the start period of the monitored circuit system, and the RESET terminal is not triggered to output the RESET signal to the monitored circuit system. When the monitored circuit system is started, the dog feeding program starts to run, meanwhile, the first control signal WD _ CTR is set to be low, the output of the OR gate is consistent with the second control signal, and the monitoring circuit enters a conventional monitoring state.
The above-described embodiments are merely preferred embodiments of the present invention, and general changes and substitutions by those skilled in the art within the technical scope of the present invention are included in the protection scope of the present invention.
Claims (10)
1. A monitoring method is applied to a monitoring circuit and comprises the following steps:
acquiring a first control signal related to the starting time of a monitored circuit system;
generating a third control signal according to the first control signal and the second control signal, wherein the state of the second control signal is different based on whether a predetermined signal from the monitored circuit system is received in each predetermined time length;
based on the third control signal, it is determined whether to send a reset signal to the monitored circuitry.
2. The method of claim 1, wherein the first control signal switches signal states in real time after the monitored circuitry completes booting.
3. The method of claim 2, wherein the first control signal is obtained by the monitoring circuit from monitored circuitry.
4. The method of claim 1, wherein the first control signal switches signal states depending on whether a predetermined said activation duration is reached.
5. The method of any of claims 1-4, wherein a third control signal is generated from the first control signal and the second control signal using a logic gate circuit unit.
6. A monitoring circuit for monitoring monitored circuitry, the monitoring circuit comprising:
an acquisition unit configured to acquire a first control signal related to a start-up duration of the monitored circuitry;
a generation unit connected to receive the first control signal and configured to generate a third control signal according to the first control signal and a second control signal, a state of the second control signal being different based on whether a predetermined signal from the monitored circuitry is received every predetermined time period;
a reset unit connected to receive the third control signal and configured to determine whether to send a reset signal to the monitored circuitry based on the third control signal.
7. The monitoring circuit of claim 6, wherein the obtaining unit is configured to obtain the first control signal from the monitored circuitry.
8. The monitoring circuit of claim 6, wherein the acquisition unit is configured to generate the first control signal in different states depending on whether a start-up completion signal is received from the monitored circuitry.
9. A monitoring circuit according to any of claims 6-8, wherein the generating unit is a logic gate unit.
10. The monitoring circuit of any one of claims 6-8, wherein the generating unit is a controlled switching circuit unit.
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|---|---|---|---|
| CN201911146091.9A CN110928220A (en) | 2019-11-19 | 2019-11-19 | Monitoring method and monitoring circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911146091.9A CN110928220A (en) | 2019-11-19 | 2019-11-19 | Monitoring method and monitoring circuit |
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| CN110928220A true CN110928220A (en) | 2020-03-27 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4809280A (en) * | 1984-06-12 | 1989-02-28 | Omron Tateisi Electronics Co. | Microcomputer system with watchdog timer |
| CN1908856A (en) * | 2005-08-05 | 2007-02-07 | 中兴通讯股份有限公司 | Position restoration circuit device |
| CN102214124A (en) * | 2011-06-08 | 2011-10-12 | 深圳市理邦精密仪器股份有限公司 | Watchdog reset control system |
| CN105897618A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Reset circuit device of switch |
| CN105892607A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Circuit and method for preventing switch from being repetitively reset |
| CN108415791A (en) * | 2018-02-02 | 2018-08-17 | 上海康斐信息技术有限公司 | A kind of watchdog circuit and control method |
-
2019
- 2019-11-19 CN CN201911146091.9A patent/CN110928220A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4809280A (en) * | 1984-06-12 | 1989-02-28 | Omron Tateisi Electronics Co. | Microcomputer system with watchdog timer |
| CN1908856A (en) * | 2005-08-05 | 2007-02-07 | 中兴通讯股份有限公司 | Position restoration circuit device |
| CN102214124A (en) * | 2011-06-08 | 2011-10-12 | 深圳市理邦精密仪器股份有限公司 | Watchdog reset control system |
| CN105897618A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Reset circuit device of switch |
| CN105892607A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Circuit and method for preventing switch from being repetitively reset |
| CN108415791A (en) * | 2018-02-02 | 2018-08-17 | 上海康斐信息技术有限公司 | A kind of watchdog circuit and control method |
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