JP2000003239A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for suppressing peak currents regularly running through a circuit synchronously with a clock signal or the like, and easing a radiation noise. SOLUTION: A capacitative element Cs is inserted through resistance means R1 and R2 to power supply sources Vcc and Gnd in a circuit whose driving load is relatively large such as an output stage circuit 8A of a clock driver or the like. Currents are supplied from the capacitative element at a relatively low impedance side, or currents are extracted to the capacitative element in the transitional response stage of the reversal operation of an output stage circuit. The capacitative element is charged through the resistance means in a normal state after the transitional response operation, and preparation for the next transitional response operation can be realized. Therefore, any large currents can be prevented from running to a power source terminal at the time of the reversal operation in synchronism with the rising edge of a clock signal ϕ. Thus, a current peak can be eased, and an electromagnetic radiation noise can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EMI (Electro-Magnetic Int.
The present invention relates to a technique for mitigating erference (electromagnetic interference), and relates to a technique effective when applied to a semiconductor integrated circuit operated synchronously with a clock, such as a microprocessor, a microcomputer, and a data processor.

[0002]

2. Description of the Related Art As the speed of operation of a semiconductor integrated circuit such as a microcomputer is increased, the internal operation cycle time is shortened. Accordingly, the internal clock signal and the internal bus signal must be changed sharply. When the signal is changed sharply, the signal waveform contains noise (harmonics) of frequency components ranging from several hundred MHz (megahertz) to several GHz (gigahertz).

In a semiconductor integrated circuit, clock signal wiring and signal wiring of a bus run over the entire surface of a chip, and these function as an antenna, and such harmonic components are emitted as radiation noise. The emitted radiation noise affects an external electric field, so-called EMI (Electro-Magnetic I).
nterference: electromagnetic interference).

Conventionally, for such radiation noise,
The countermeasures were taken by the mounting technology of the semiconductor integrated circuit. For example, placing a metal shield plate on the surface of a semiconductor integrated circuit mounted on a substrate, devising a mounting position of the semiconductor integrated circuit with respect to the substrate, and devising a shape of the substrate itself. I was taking measures.

[0005]

However, when measures are taken against radiation noise by mounting technology, there are problems that the number of components to be mounted on the board increases and that the design of the board is not easy. Revealed by the inventor.

Further, a receiver, a portable telephone, a PHS (Personal Handyphone System) using a VHF (Very High Frequency) band or a UHF (Ultra High Frequency) band.
m), a large number of semiconductor integrated circuits are mounted at high density from the viewpoint of miniaturization, and some frequency components of the radiated noise overlap with the practical frequency band of those portable wireless devices. It can be a noise source by itself.

The inventor of the present invention has proposed that the radiation noise of a semiconductor integrated circuit is caused by a harmonic component due to an operation clock signal or a bus signal that is changed at a high frequency. EMI (Electro-Magnetic Interference:
To reduce electromagnetic interference). In addition, depending on the application, whether the highest priority is given to high-speed operation, the highest priority to low radiation noise,
There are different market requirements. The inventor of the present invention has found that it is necessary to selectively cope with these conflicting demands.

It is an object of the present invention to provide a semiconductor integrated circuit capable of suppressing a peak current flowing in a circuit regularly in synchronization with a clock signal or the like and thereby reducing radiation noise.

Another object of the present invention is to provide a semiconductor integrated circuit capable of selectively responding to mutually different requests whether to give top priority to high-speed operation or low-radiation noise. Is to provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] A capacitive element is inserted into a power supply source of a circuit having a relatively large driving load via a resistance means. For example, in a semiconductor integrated circuit having a push-pull circuit or a CMOS circuit operated in synchronization with a clock signal, the push-pull circuit or the CMOS circuit (IN
V1) is connected to one power supply terminal (Vcc) via first resistance means (R1), and connected to the other power supply terminal (Gnd) via second resistance means (R2). (Cs) having a first storage electrode connected to the second resistance means and a second storage electrode connected to the second resistance means
Is provided. The push-pull circuit or the CMOS circuit is a clock driver that transmits a clock signal to a subsequent stage, or a bus driver that drives a bus.

According to the above means, the capacitance element is charged via the first and second resistance means in a state where the operation of the push-pull circuit or the CMOS circuit is determined. In the transient response stage of the inversion operation of the push-pull circuit or the CMOS circuit, first, operation power is supplied from the capacitor. Since the resistance means is interposed between the power supply terminal and the power supply terminal, a current is supplied from a capacitor element having a relatively low impedance, or the current is drawn toward the capacitor element. Therefore, a large current does not flow to the power supply terminal during the inversion operation synchronized with the rising edge of the clock signal, and the current peak is reduced.

In particular, the first and second resistance means and the capacitance element can be shared by the inverter circuit units (INV2, INV3) to which the mutually inverted clock signals are supplied. According to this, when the outputs of both inverter circuit sections are inverted, one of the inverter circuit sections takes out charge from the capacitive element to output a high level, and the other inverter circuit section outputs a low level. The charge is supplied to the capacitor. At this time, the direction of the current is one direction with respect to the capacitive element. In other words, the charge extracted in the inversion operation to the high-level output is intended to supplement the charge supplied in the inversion operation to the low-level output. Therefore, most of the current required at the time of output inversion can be efficiently covered by the charge accumulated in the capacitor.

[2] A plurality of clock gate circuits (11A to 11A) for supplying a clock signal to the inside of the semiconductor integrated circuit
The output phase of F) can be made variable. The plurality of clock gate circuits receive a clock signal (φ) from, for example, a clock pulse generator (8), output clock signals having different phases, and supply the clock signals to a target internal circuit. For example, when the internal circuit operates in synchronization with the rising edge of the clock signal, the internal circuit is operated in synchronization with clock signals having mutually different phases. As a result, the current consumption timing in the entire semiconductor integrated circuit becomes the clock signal. Is shifted according to the phase shift of That is, the peak of the power supply current does not concentrate on the rising edge of the clock signal. As a result, it is possible to suppress the peak current flowing in the circuit regularly in synchronization with the clock signal or the like, and to reduce the radiation noise.

How to shift the phase is determined by, for example, a CPU.
It can be determined by the control operation according to (2).
For example, the CPU (2) sets control information for forming a one-to-one control signal for each clock gate circuit in the control register (30). Whether or not to shift the phase according to the set value, and if so, how much to shift, is set. In a usage mode in which high speed operation is prioritized over reduction of radiation noise, the phases are not shifted at all, synchronization of each circuit is guaranteed, and the upper limit of the clock signal frequency can be increased. When the priority is placed on the reduction of radiation noise, the phase of the synchronous operation clock signal of each circuit is shifted as much as possible within a range where no malfunction occurs.

According to the above, it is possible to selectively answer any of different requests whether to give top priority to high-speed operation or to give top priority to low radiation noise.

[3] The transistor size of an output circuit (10A) for outputting a signal to the outside, such as an output buffer circuit or an input / output buffer circuit, can be varied. For example, the output buffer circuit has push-pull circuits (INV5, INV6) connected to output terminals, and the push-pull circuits include output transistors (Mp4, Mn4, Mp5, Mp5).
n5)) and logic means (18, 19) for variably controlling the size of the output transistor according to a control signal (22G) given from the internal circuit.

If the transistor size is reduced, the power supply current peak during the output operation can be reduced.

When the operation speed is the highest priority, the transistor size is selected to be large, and when the radiation noise reduction is the highest priority, the transistor size is selected to be small. Which one to select can be determined by the control operation of the CPU (2). For example, control information for forming a one-to-one control signal for an output circuit
(2) sets the control register (30). Reduce the transistor size according to the set value, or
When making it small, how much is made small is determined.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Outline of Microcomputer
FIG. 2 is a block diagram schematically showing a microcomputer as an example of the semiconductor integrated circuit according to the present invention. Although not particularly limited, the microcomputer 1 shown in FIG. 1 is formed on a single semiconductor chip made of single crystal silicon by a CMOS integrated circuit manufacturing technique.

Although not particularly limited, the microcomputer 1 includes a CPU (Central Processing Unit) 2 and a system controller 9 together with a RAM (Random Access Memory) on a semiconductor chip.
Access memory) 3, ROM (read only memory) 4, DMAC (direct memory access controller) 5, TMR (timer counter) 6, SC
I (serial communication interface
Peripheral circuit blocks such as a controller 7, a CPG (clock pulse generator) 8, and an IOP (input / output port) 10 are provided by being connected by a bus 12.

The CPU 2 fetches an instruction stored in, for example, the ROM 4, decodes the fetched instruction, and controls data processing. Data to be subjected to data processing is loaded from the RAM 3 or the like into a data register (not shown) in the CPU 2. The data loaded into the data register or the like is subjected to data processing using an arithmetic unit such as an arithmetic and logic unit (not shown) in the CPU 2. DMAC5
Is a source for DMA transfer control by the CPU 2.
Destination information is initialized. DMAC
5 acquires the bus right from the CPU 2 in response to the DMA transfer request, and controls the data transfer from the area specified by the source information to the area specified by the destination information.

The clock pulse generator 8 receives a system clock signal supplied from the outside or an oscillation signal generated by an oscillator, divides the frequency, and generates a reference clock signal φ. Reference numeral 10 denotes a clock driver that outputs a reference clock signal φ. The reference clock signal φ is supplied to the clock gate circuits 11A to 11F via a clock wiring not shown. Clock signals φ input to clock gate circuits 11A to 11F are supplied to the corresponding circuit blocks.

FIG. 1 shows a detailed example of a clock supply system in the microcomputer 1. FIG. 1 representatively shows, as circuit blocks, a CPU 2, a clock driver 8A included in the SCI 7, the CPG 8, a system controller 9, and an output circuit 10A included in the IOP 10. The output circuit 10A is a microcomputer 1
Functions as a bus driver to the outside of the device.

The circuit blocks represented by the CPU 2 and the SCI 7 are operated in synchronization with the clock signal. As a logical configuration for performing such a clock synchronous operation, CP shown in FIG.
As schematically shown in U2 and SCI7, a sequential logic circuit FF such as a flip-flop or a latch circuit is arranged at a key point of the combinational logic circuit unit LGT configuring a signal transmission path for data processing. The data processing is performed in the combinational logic circuit unit LGT while sequentially latching the information in the sequential logic circuit FF every clock cycle.

The clock signal CK2 is an internal clock signal of the CPU 2 output from the clock gate circuit 11A. Similarly, the clock signal CK7 is an internal clock signal of the SCI7 output from the clock gate circuit 11F.

The microcomputer 1 operates in synchronization with the clock signal φ as described above. Therefore, a relatively large power supply current flows in the entire microcomputer 1 every clock cycle. The microcomputer 1 has the following characteristics in order to suppress the peak current of the power supply current flowing through the circuit regularly in this manner. The contents are as follows. The clock gate circuit of each circuit block changes the phase of the output clock signal according to the control signal from the system controller, and the clock gate circuit drives the relatively large load in the clock system and the power supply system of the clock driver. Adopts a secondary battery circuit that uses the charge of the capacitive element. In the signal output system for driving an external load, the size of the drive transistor is varied according to a control signal from a system controller. Each is described in detail below. The power supply current is a current flowing through the power supply wiring of the microcomputer chip, and can be grasped as a current flowing through an external power supply terminal (power supply pin) of the microcomputer chip.

<< Phase Control of Clock Signal >> FIG. 3 shows an example of the clock gate circuit 11A. The clock gate circuit 11A includes an inverter I as a delay means for delaying the input clock signal φ by different times.
NVd two-stage series circuit DEL1 to n-stage series circuit DEL
n. A plurality of inverter series circuits DEL1 to DEL
The output of ELn is made selectable by the selector 20 according to the control signal 22A of a plurality of bits. The delay signal 23 and the clock signal φ selected by the selector 20 are
Is input to Clock signal CK2 output from AND gate 21 has a phase delayed from clock signal φ by the delay time of the inverter series circuit. With this configuration, the phase can be shifted within a time range shorter than the high-level period of the clock signal φ. Clock gate circuits 11B to 11 of other circuit modules such as SCI7
F is similarly configured. Those clock gate circuits 11
The control signals supplied to B-11F are shown in FIG. 2 as 22B-22F.

The system controller 9 is provided with a control register 30 which is initialized by reset processing such as power-on, and thereafter can be arbitrarily read / written by the CPU 2. The control signals 22A-2
2F is control information set in the control register 30 or information formed based on the control information.

The initial state of the control register 30 at the time of power-on reset is determined according to a reset processing program, and the operation of the control register 30 after reset can be determined by an application program or the like. That is, CPU2
How the phases of the internal clock signals CK2 and CK7 of the circuit blocks such as are shifted can be determined by the control operation of the CPU 2. In accordance with the value of the control information set in the control register 30 by the CPU 2, whether or not to shift the phase and, if so, how much to shift the phase are set.

For example, circuit blocks such as the CPU 2
When the operation is performed in synchronization with the rising edge of the clock signal CK2, the phase of the internal clock signal of each circuit block such as the CPU 2 becomes the clock signal φ as illustrated in FIG.
As a result, the respective circuit blocks are operated synchronously with the clock signal having the same phase, so that the current consumption timing in the entire microcomputer 1 is synchronized with the rising of the clock signal φ, and the peak of the power supply current is Focus on the rising edge of signal φ. As a result, the peak current flowing in a circuit block such as the CPU 2 regularly in synchronization with the clock signal is increased in proportion to the frequency of the clock signal φ.

On the other hand, as exemplified in FIG.
If the phases of the internal clock signals are shifted among the circuit blocks by the control signals 22A to 22F, as illustrated in FIG. 6, the circuit blocks such as the CPU 2 are operated in synchronization with the clock signals having different phases from each other. The current consumption timing in the entire computer 1 is shifted according to the phase shift of the clock signals CK2 and CK7. That is, the peak of the power supply current does not concentrate on the rising edge of the clock signal φ. As a result, it is possible to reduce the peak current flowing to the circuit regularly in synchronization with the clock signal, and to reduce the radiation noise.

How to shift the phase can be arbitrarily determined depending on the setting of the control information of the CPU 2 in the control register 30. Therefore, a usage mode in which the highest speed operation is prioritized over the reduction of radiation noise. Then, the phase is not shifted at all, the synchronization of each circuit is guaranteed, and the upper limit of the clock signal frequency can be increased. When reducing the radiation noise is given top priority, the phase of the synchronous operation clock signal of each circuit block is shifted as much as possible within a range where no malfunction occurs. Therefore, it is possible to selectively respond to any of mutually different requests whether to give top priority to high-speed operation or to give top priority to low radiation noise.

<< Secondary Battery Circuit >> In FIG.
Is a secondary battery circuit, and the secondary battery circuit 1
3 and 14 are circuits having a relatively large driving load, for example, C
A final output stage of the clock driver 8A included in the PG8,
It is provided in the power supply source of the final output stage of the clock gate circuits 11A to 11F.

For example, the final output stage of the clock driver 8A has a CMOS inverter constituted by a p-channel MOS transistor Mp1 and an n-channel MOS transistor Mn1. At this time, the secondary battery circuit 13 is configured by inserting the capacitance element Cs into the power supply source via the resistance means R1 and R2. That is, the source of the MOS transistor Mp1 is connected to one power supply terminal (high-potential-side power supply terminal Vcc) via the first resistance means R1, and the source of the MOS transistor Mn1 is connected via the second resistance means R2. A capacitive element connected to the other power supply terminal (ground terminal Gnd) and having a first storage electrode connected to the first resistance means R1 and a second storage electrode connected to the second resistance means R2; Cs is provided.

The resistance means R1 and R2 include, for example,
The ON resistance of the MOS transistor can be used,
P-channel type MO with gate coupled to ground terminal Gnd
It can be constituted by an n-channel MOS transistor having an S transistor and a gate coupled to a power supply terminal Vcc. The magnitudes of the resistance means R1, R2 and the capacitance element Cs are determined by the power supply voltage, the overall circuit scale of the semiconductor integrated circuit,
For example, the resistance means R1 and R2 are 1 to 5 kΩ, and the capacitance element is 40 to 200 pF.
Degree.

As shown in FIGS. 1 and 7, the secondary battery circuit 14 has a power supply source Vc for the AND gate 21.
c and Gnd via the resistance means R1 and R2 to the capacitive element Cs
Can be inserted. In FIG. 7, Mp
2 and Mp3 are p-channel MOS transistors, and Mn2 and Mn3 are n-channel MOS transistors.

According to the secondary battery circuit 13, as shown in FIG. 8, when the operation of the CMOS inverter INV1 including the MOS transistors Mp1 and Mn1 is determined, the CMOS inverter INV1 allows a through current to flow. Since there is no capacitive element, the capacitive element Cs is charged via the first and second resistance means R1 and R2. CMOS
In the transient response stage of the inverting operation of the inverter INV1, C
Although a current through path is generated in the MOS inverter INV1, a resistance means R is provided between the power supply terminals Vcc and Gnd.
1 and R2, a current is first supplied from the capacitive element Cs on the relatively low impedance side,
Alternatively, current is drawn toward the capacitance element Cs. After the transient response operation, when the state of the CMOS inverter INV1 is determined, the charging operation for the capacitance element Cs is performed, and the power supply current Icc gradually flows accordingly. Thereby, as illustrated in FIG. 9, the peak of power supply current Icc is reduced. During the inversion operation synchronized with the rising edge of the clock signal φ, a large current does not flow through the power supply terminals Vcc and Gnd, and the current peak is alleviated. As a result, radiation noise can be reduced. The secondary battery circuit 14 can obtain the same effect.

FIG. 10 shows another usage of the secondary battery circuit. The first and second resistance means R1 and R2 and the capacitance element Cs are shared by CMOS inverters INV2 and INV3 that output complementary signals. In FIG. 10, the CMO
The clock signal φ is supplied to the S inverter INV2. An inverted clock signal obtained by inverting the clock signal φ by the inverter INV4 is supplied to the CMOS inverter INV3.

According to the configuration of FIG. 10, when the outputs of both CMOS inverters INV2 and INV3 are inverted, one of the CMOS inverters extracts electric charge from the capacitive element Cs to output a high level, and the other CMOS inverter outputs the high level. The charge is supplied to the capacitor Cs to output a low level. At this time, the direction of the current is one direction with respect to the capacitive element Cs as shown in FIG. 10, in other words, the charge extracted by the inversion operation to the high level output is inverted to the low level output. Since the charge supplied by the operation is intended to supplement, most of the current required at the time of output inversion can be efficiently covered by the charge accumulated in the capacitor.

For example, in the example of FIG. 10, in the circuit block,
The present invention can be applied to a circuit that supplies a clock signal as a complementary signal. For example, the circuit of FIG. 10 may be added to the output of the AND gate 21 of FIG. If the clock signal is supplied as a complementary signal, the in-phase noise component can be canceled and the noise resistance of the clock signal can be improved. A clock signal may be output to the clock driver 8A as a complementary signal.

<< Transistor Size Control of Output Circuit >> According to FIG. 1, the output circuit 10A for outputting a signal to the outside, such as an output buffer circuit or an input / output buffer circuit, included in the input / output port 10 has its transistor The size is variable. For example, the output circuit 10A is a p-channel MOS having a drain coupled to an output terminal OUT.
Transistors Mp4, Mp5 and n-channel type MOS
It has transistors Mn4 and Mn5. MOS transistors Mp4, Mn4 and Mp5, Mn5 are CMOS
Function as inverters INV5 and INV6. The output circuit 10A includes signals IN1 and IN2 to be output and a control signal 22 corresponding to the control information of the control register 30.
G is supplied. When the signals IN1 and IN2 are set to the high level and the low level, the output circuit 10A is set to the high output impedance state, and the output operation is disabled. Output circuit 10
A outputs a high level when both the signals IN1 and IN2 are set to a low level, and outputs a low level when both the signals IN1 and IN2 are set to a high level.

The AND gate 18 and the OR gate 19 are
A logic means for variably controlling the size of the output transistor of the output circuit 10A according to the control signal 22G is configured.

As shown in FIG. 11, the control signal 22G
Is set to the high level ("1"), the output of the OR gate 19 matches the logical value of the signal IN1 and the AND gate 1
The output of 8 is matched with the logical value of the signal IN2, whereby both the CMOS inverters INV5 and INV6 can perform the output operation, and the output operation can be speeded up. On the other hand, when the control signal 22G is set to a low level ("0"), the output of the AND gate 18 is fixed at a low level, and the output of the OR gate 19 is fixed at a high level.
Thereby, one CMOS inverter INV5 is brought into a high output impedance state. This state is a state in which the size of the MOS transistor forming the output circuit 10A is reduced to approximately half as compared with the former. Although the speeding up of the output operation is sacrificed, the transistor size of the output circuit 10A can be reduced, so that the peak of the power supply current during the output operation can be reduced. Therefore, priority can be given to reducing the induction noise.

As described above, the transistor size is selected to be large when the operation speed is the highest priority, and the transistor size is selected to be small when the radiation noise reduction is the highest priority. Which one to select can be arbitrarily determined based on control information set in the control register 30 by the CPU 2. For example, the CPU 2 sets control information for forming the control signal 22G of the output circuit 10A in the control register 30. According to the set value, it is possible to determine whether to reduce the transistor size or, if so, how small.

In the example of FIG. 1, the sizes of both the p-channel type and the n-channel type output transistors are made variable. However, as shown in FIG. It may be limited to only a transistor.

As described above, each of the phase control of the clock signal, the control of the transistor size of the secondary battery circuit, and the control of the transistor size of the output circuit can reduce the electromagnetic radiation noise. Here, the evaluation method will be described. Since the above-mentioned electromagnetic radiation noise reduction method is intended to reduce the EMI by regularly suppressing the peak current flowing in the circuit, a current spectrum measurement method can be cited as one of the suitable evaluation methods. . This is because the L
The SI is mounted and externally supplied with power to operate. At this time, a current spectrum is measured by bringing the current probe close to the power supply line. For example, as a result of performing such a current spectrum measurement, the clock driver 8A described with reference to FIG.
In addition, the peak value of the high-frequency current is reduced by 10 dB only by employing the secondary battery circuits 13 and 14 in the clock gate circuits 11A to 11F.

The invention made by the inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the circuit to which the secondary battery circuit can be applied is not limited to the clock gate circuit and the clock driver having the circuit configuration described above. For example, the clock gate circuit 17 illustrated in FIG. 13 may be used. In this example,
The clock gate circuit 17 includes a two-input AND gate, and one input of the clock gate circuit 17 may be, for example, a standby signal that is set to a low level in a standby mode. In the above description, a CMOS circuit is taken as an example.
The inverter may be a push-pull circuit using a pair of n-channel MOS transistors.

In the present invention, the same means as described above can be employed not only for a clock signal driver or a buffer but also for a bus driver or a bus buffer for a bus signal. In that case, the present invention can be applied to a bus buffer of an internal bus of the semiconductor integrated circuit. A secondary battery circuit or the like can be applied to a power supply system of a drive voltage output circuit in a semiconductor integrated circuit for driving and controlling a liquid crystal display.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is the field of application as the background has been described. However, the present invention is not limited to this, and is not limited thereto. Such as a protocol processor, a graphic display processor for controlling drawing and display, and a digital signal processor, which can operate in synchronization with a clock signal.

[0053]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

[1] In a clock synchronous circuit having a relatively large driving load such as an output stage circuit such as a clock driver or a bus driver, a capacitive element is inserted into a power supply source via a resistance means. In the transient response stage of the inverting operation of the stage circuit, a current is supplied from the capacitive element on the relatively low impedance side or the current is drawn toward the capacitive element, and the capacitive element is in a steady state after the transient response operation. It is charged via the resistance means and then prepares for a transient response operation. Therefore, a large current does not flow through the power supply terminal during the inversion operation synchronized with the rising edge of the clock signal, and the current peak can be reduced, thereby reducing electromagnetic radiation noise.

[2] Since the output phases of a plurality of clock gate circuits for supplying a clock signal to the inside of the semiconductor integrated circuit can be varied, the peak current flowing to the circuit regularly in synchronization with the clock signal or the like can be suppressed. Radiation noise can be reduced.

[3] Since the transistor size of an output circuit, such as an output buffer circuit or an input / output buffer circuit, for outputting a signal to the outside can be made variable, the power supply current peak during output operation can be reduced by reducing the transistor size. can do. When the operation speed is the highest priority, the transistor size is selected to be large, and when the radiation noise reduction is the highest priority, the transistor size is selected to be small. Which one to select can be determined by the control operation of the CPU.

[4] It is possible to selectively respond to any of different requests whether to give top priority to high-speed operation or to give top priority to low radiation noise.

[Brief description of the drawings]

FIG. 1 is a block diagram mainly showing a clock supply system of a microcomputer which is an example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram schematically showing an entire microcomputer as an example of a semiconductor integrated circuit according to the present invention.

FIG. 3 is a logic circuit diagram showing an example of clock gate times.

FIG. 4 is an explanatory diagram showing a state of a power supply current with respect to a clock signal when a phase of an internal clock signal of each circuit block is not shifted.

FIG. 5 is an explanatory diagram showing a state of an internal clock signal when a phase is shifted in each circuit block.

FIG. 6 is an explanatory diagram showing a state in which the peak of the power supply current is dispersed when the phase of the internal clock signal is shifted.

FIG. 7 is a circuit diagram when a secondary battery circuit is employed in the power source system of the AND gate.

FIG. 8 is an explanatory diagram of the operation of the secondary battery circuit.

FIG. 9 is a power supply current waveform diagram showing a manner in which the peak of the power supply current Icc is reduced by employing a secondary battery circuit.

FIG. 10 is a circuit diagram showing an example in which a pair of inverters that output complementary signals share a secondary battery circuit.

FIG. 11 is an explanatory diagram of an operation in an output circuit having a variable transistor size.

FIG. 12 is a circuit diagram showing another example of the transistor size variable output circuit.

FIG. 13 is a logic circuit diagram showing another example of a clock gate circuit to which a secondary battery circuit can be applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microcomputer 2 CPU 7 SCI 8 Clock pulse generator 8A Clock driver 9 System controller 10A Output circuit Mp4, Mp5, Mn4, Mn5 MOS transistor 11A-11F Clock gate circuit 12 Bus 13, 14 Secondary battery circuit R1, R2 Resistance means Cs Capacitance element 18 AND gate 19 OR gate 21 AND gate 22A to 22F Phase control signal of internal clock signal 22G Transistor size control signal 30 Control register DEL1 to DELn Delay means 20 Selector 21 AND gate

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // G06F 1/04 (72) Inventor Kenichi Ishibashi 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (72) Kaoru Soshishita, Inventor Kaoru Soshita 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In-house Hitachi, Ltd.

Claims (15)

[Claims] 1. A semiconductor integrated circuit having a push-pull circuit operated in synchronization with a clock signal, wherein the push-pull circuit is connected to one power supply terminal via a first resistor, and the second resistor is connected to the power supply terminal. A semiconductor element comprising a capacitor element having a first storage electrode connected to the first resistance means and a second storage electrode connected to the second resistance means, connected to the other power supply terminal via Integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein said push-pull circuit is included in a clock driver that transmits a clock signal to a subsequent stage. 3. The semiconductor integrated circuit according to claim 1, wherein said push-pull circuit is included in a bus driver for driving a bus. 4. In a semiconductor integrated circuit having an inverter circuit section to which a clock signal is supplied, a pair of said inverter circuit sections to which said clock signals whose phases are inverted are supplied through a first resistor means. One power supply terminal is connected, the other power supply terminal is connected via the second resistance means, and connected to the first storage electrode and the second resistance means connected to the first resistance means. A semiconductor integrated circuit provided with a capacitor having a second storage electrode. 5. A CMOS operated synchronously with a clock signal.
In a semiconductor integrated circuit having a circuit, the CMOS circuit is connected to one power supply terminal via a first resistance means, connected to the other power supply terminal via a second resistance means, The first storage electrode connected to
A semiconductor integrated circuit comprising a capacitor having a second storage electrode connected to a second resistance means. 6. The semiconductor integrated circuit according to claim 5, wherein said CMOS circuit is a CMOS inverter constituting a final output stage of a clock driver for transmitting a clock signal to a subsequent stage of a clock wiring. 7. The semiconductor integrated circuit according to claim 6, wherein said clock driver is included in a clock pulse generator, and said clock pulse generator supplies a clock signal to a plurality of circuit blocks via a clock wiring. 8. The semiconductor integrated circuit according to claim 5, wherein said CMOS circuit is a clock gate circuit for transmitting a clock signal to a subsequent stage. 9. The CMOS circuit is a clock gate circuit provided in each of the circuit blocks, and the clock gate circuit inputs a clock signal from the clock wiring and outputs a clock signal inside a corresponding circuit block. 8. The semiconductor integrated circuit according to claim 7, wherein said semiconductor integrated circuit is supplied. 10. A semiconductor integrated circuit comprising: a semiconductor chip including a clock pulse generator and a plurality of circuit blocks operated in synchronization with a clock signal supplied from the clock pulse generator, wherein the circuit block includes a clock signal. A semiconductor integrated circuit having a clock gate circuit for inputting a clock signal supplied from a pulse generator, wherein the clock gate circuit makes a phase of an output clock signal with respect to the input clock signal variable by a control signal. 11. A register unit in which control information for generating the control signal is set in one-to-one correspondence with the clock gate circuit, one of the circuit blocks is a CPU, and the CPU is the register unit. 11. The semiconductor integrated circuit according to claim 10, wherein said control information is set for said control information. 12. The clock gate circuit comprises: a delay unit for delaying an input clock signal; a selection unit for selecting a delay time by the control signal; and a selection unit for selecting the input clock signal and the clock signal. 12. The semiconductor integrated circuit according to claim 11, further comprising: a logic gate that outputs a clock signal based on a logical product of the clock signal having the delay time. 13. The logic gate is connected to one power supply terminal via a first resistance means, and connected to the other power supply terminal via a second resistance means, to receive supply of operation power, 13. The semiconductor integrated circuit according to claim 12, further comprising a capacitor having a first storage electrode connected to the first resistance means and a second storage electrode connected to the second resistance means. circuit. 14. A semiconductor integrated circuit, comprising: a semiconductor chip, an output circuit capable of outputting a signal to the outside of the semiconductor chip, and an internal circuit that supplies a signal to the output circuit and causes the output circuit to perform an output operation. Wherein the output circuit comprises:
A push-pull circuit connected to the output terminal, the push-pull circuit having an output transistor and logic means for variably controlling the size of the output transistor according to a control signal given from the internal circuit; A semiconductor integrated circuit. 15. The internal circuit includes a CPU and register means accessible by the CPU, wherein the register means sets control information for determining a state of the control signal by the CPU. 15. The semiconductor integrated circuit according to claim 14, wherein