ITRM20020281A1 - Metodo ed apparecchiatura per accesso rapido di memorie. - Google Patents
Metodo ed apparecchiatura per accesso rapido di memorie.Info
- Publication number
- ITRM20020281A1 ITRM20020281A1 IT2002RM000281A ITRM20020281A ITRM20020281A1 IT RM20020281 A1 ITRM20020281 A1 IT RM20020281A1 IT 2002RM000281 A IT2002RM000281 A IT 2002RM000281A IT RM20020281 A ITRM20020281 A IT RM20020281A IT RM20020281 A1 ITRM20020281 A1 IT RM20020281A1
- Authority
- IT
- Italy
- Prior art keywords
- memories
- equipment
- quick access
- quick
- access
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT2002RM000281A ITRM20020281A1 (it) | 2002-05-20 | 2002-05-20 | Metodo ed apparecchiatura per accesso rapido di memorie. |
| US10/366,213 US7020737B2 (en) | 2002-05-20 | 2003-02-13 | Pipelined burst memory access |
| US11/343,818 US7363452B2 (en) | 2002-05-20 | 2006-01-31 | Pipelined burst memory access |
| US12/107,296 US7949844B2 (en) | 2002-05-20 | 2008-04-22 | Pipelined burst memory access |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT2002RM000281A ITRM20020281A1 (it) | 2002-05-20 | 2002-05-20 | Metodo ed apparecchiatura per accesso rapido di memorie. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ITRM20020281A0 ITRM20020281A0 (it) | 2002-05-20 |
| ITRM20020281A1 true ITRM20020281A1 (it) | 2003-11-20 |
Family
ID=11456315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT2002RM000281A ITRM20020281A1 (it) | 2002-05-20 | 2002-05-20 | Metodo ed apparecchiatura per accesso rapido di memorie. |
Country Status (2)
| Country | Link |
|---|---|
| US (3) | US7020737B2 (it) |
| IT (1) | ITRM20020281A1 (it) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITRM20020281A1 (it) * | 2002-05-20 | 2003-11-20 | Micron Technology Inc | Metodo ed apparecchiatura per accesso rapido di memorie. |
| KR100518597B1 (ko) * | 2003-10-09 | 2005-10-04 | 삼성전자주식회사 | 입출력 데이터 폭을 선택적으로 변경시키는 저전력 소비형반도체 메모리 장치 및 이에 대한 데이터 입출력 방법 |
| CN101740102B (zh) * | 2008-11-11 | 2014-03-26 | 西安奇维测控科技有限公司 | 一种多通道闪存芯片阵列结构及其写入和读出方法 |
| US7916575B2 (en) * | 2008-12-23 | 2011-03-29 | Emanuele Confalonieri | Configurable latching for asynchronous memories |
| GB2522057B (en) | 2014-01-13 | 2021-02-24 | Advanced Risc Mach Ltd | A data processing system and method for handling multiple transactions |
| US9606851B2 (en) | 2015-02-02 | 2017-03-28 | International Business Machines Corporation | Error monitoring of a memory device containing embedded error correction |
| US9940457B2 (en) * | 2015-02-13 | 2018-04-10 | International Business Machines Corporation | Detecting a cryogenic attack on a memory device with embedded error correction |
| US10152262B2 (en) * | 2016-05-03 | 2018-12-11 | Micron Technology, Inc. | Memory access techniques in memory devices with multiple partitions |
| KR102504332B1 (ko) * | 2018-02-21 | 2023-02-28 | 삼성전자주식회사 | 서로 이격되어 배치되는 범프 어레이들을 포함하는 메모리 장치 및 이를 포함하는 전자 장치 |
| US11513976B2 (en) | 2020-03-31 | 2022-11-29 | Western Digital Technologies, Inc. | Advanced CE encoding for bus multiplexer grid for SSD |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0389151A3 (en) * | 1989-03-22 | 1992-06-03 | International Business Machines Corporation | System and method for partitioned cache memory management |
| ATE185631T1 (de) * | 1991-08-16 | 1999-10-15 | Cypress Semiconductor Corp | Dynamisches hochleistungsspeichersystem |
| US5781908A (en) * | 1995-12-18 | 1998-07-14 | J.D. Edwards World Source Company | File data synchronizer in a distributed data computer network |
| US6167486A (en) * | 1996-11-18 | 2000-12-26 | Nec Electronics, Inc. | Parallel access virtual channel memory system with cacheable channels |
| US6230245B1 (en) * | 1997-02-11 | 2001-05-08 | Micron Technology, Inc. | Method and apparatus for generating a variable sequence of memory device command signals |
| FR2778258A1 (fr) * | 1998-04-29 | 1999-11-05 | Texas Instruments France | Controleur d'acces de trafic dans une memoire, systeme de calcul comprenant ce controleur d'acces et procede de fonctionnement d'un tel controleur d'acces |
| JP3271591B2 (ja) * | 1998-09-30 | 2002-04-02 | 日本電気株式会社 | 半導体記憶装置 |
| US6708254B2 (en) * | 1999-11-10 | 2004-03-16 | Nec Electronics America, Inc. | Parallel access virtual channel memory system |
| US6725336B2 (en) * | 2001-04-20 | 2004-04-20 | Sun Microsystems, Inc. | Dynamically allocated cache memory for a multi-processor unit |
| ITRM20020281A1 (it) * | 2002-05-20 | 2003-11-20 | Micron Technology Inc | Metodo ed apparecchiatura per accesso rapido di memorie. |
| US7076609B2 (en) * | 2002-09-20 | 2006-07-11 | Intel Corporation | Cache sharing for a chip multiprocessor or multiprocessing system |
-
2002
- 2002-05-20 IT IT2002RM000281A patent/ITRM20020281A1/it unknown
-
2003
- 2003-02-13 US US10/366,213 patent/US7020737B2/en not_active Expired - Lifetime
-
2006
- 2006-01-31 US US11/343,818 patent/US7363452B2/en not_active Expired - Lifetime
-
2008
- 2008-04-22 US US12/107,296 patent/US7949844B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| ITRM20020281A0 (it) | 2002-05-20 |
| US7020737B2 (en) | 2006-03-28 |
| US20080195795A1 (en) | 2008-08-14 |
| US7949844B2 (en) | 2011-05-24 |
| US20030214854A1 (en) | 2003-11-20 |
| US7363452B2 (en) | 2008-04-22 |
| US20060126411A1 (en) | 2006-06-15 |
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