ITMI950303A1 - PARTICULARLY INTEGRATED COMPONENT TO PREVENT THE FORMATION OF A PARASITIC TRANSISTOR - Google Patents
PARTICULARLY INTEGRATED COMPONENT TO PREVENT THE FORMATION OF A PARASITIC TRANSISTOR Download PDFInfo
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- ITMI950303A1 ITMI950303A1 IT95MI000303A ITMI950303A ITMI950303A1 IT MI950303 A1 ITMI950303 A1 IT MI950303A1 IT 95MI000303 A IT95MI000303 A IT 95MI000303A IT MI950303 A ITMI950303 A IT MI950303A IT MI950303 A1 ITMI950303 A1 IT MI950303A1
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- zone
- doped
- integrated component
- integrated
- highly
- Prior art date
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- 230000003071 parasitic effect Effects 0.000 title abstract description 20
- 230000015572 biosynthetic process Effects 0.000 title abstract description 3
- 230000005669 field effect Effects 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
- H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Viene proposto un componente integrato, che presenta due zone drogate n, che sono disposte in una prima zona (5) drogata p. La prima zona (5) è disposta sullo strato (7) drogato n. Almeno sotto una zona drogata n è posta una zona altamente drogata p. Così viene impedita la formazione di un transistor npn parassita fra la zone drogata n, la prima zona (5) drogata p e lo strato (7) drogato n.An integrated component is proposed, which has two doped zones n, which are arranged in a first doped zone (5) p. The first zone (5) is arranged on the doped layer (7) n. At least under a doped zone n there is a highly doped zone p. Thus the formation of a parasitic transistor npn between the doped zone n, the first doped zone (5) p and the doped layer (7) n is prevented.
Description
DESCRIZIONE DESCRIPTION
L'invenzione parte da un componente integrato secondo il genere della rivendicazione principale. E' gi? noto un transistor a effetto di campo come componente integrato, nel quale sul substrato drogato n ? disposta una zona drogata p. Nella zona drogata p sono introdotte due zone drogate n, e fra le zone drogate n ? disposto un Gate. Le due zone drogate n costituiscono il collegamento di Source e di Drain del transistor a effetto di campo. The invention starts from an integrated component according to the genre of the main claim. Is it already? known a field effect transistor as an integrated component, in which on the doped substrate n? set up a doped area p. In the doped zone p, two doped zones n are introduced, and between the doped zones n? arranged a Gate. The two doped zones n constitute the Source and Drain connection of the field effect transistor.
La disposizione secondo l'invenzione con le caratteristiche delle rivendicazioni 1 e 2 ha invece il vantaggio che viene impedita la formazione di un transistor parassita npn rispettivamente pnp. Disponendo sotto la quarta e/o quinta zona drogata n rispettivamente p una seconda e/o terza zona altamente drogata p rispettivamente n, viene altamente drogata la base del transistor parassita npn rispettivamente pnp, e quindi si ottiene una ridotta amplificazione del transistor parassita npn rispettivamente pnp. Cos? vengono soppressi gli effetti parassiti. The arrangement according to the invention with the characteristics of claims 1 and 2, on the other hand, has the advantage that the formation of a parasitic transistor npn or pnp is prevented. By placing under the fourth and / or fifth doped zone n respectively p a second and / or third highly doped zone p respectively n, the base of the parasitic transistor npn respectively pnp is highly doped, and therefore a reduced amplification of the parasitic transistor npn respectively is obtained. pnp. What? parasitic effects are suppressed.
Mediante le misure riportate nelle sottorivendicazioni sono possibili vantaggiosi perfezionamenti e miglioramenti dell'elemento integrato indicato nella rivendicazione 1 e 2. E' particolarmente vantaggioso condurre la seconda e/o terza zona fino allo strato debolmente drogato p rispettivamente n. Perci? si ottiene che un gradiente di potenziale, provocato da corrente di perdita o da variazione di tensione, che si manifesta fra la quinta e quarta zona drogata n rispettivamente p e la prima zona debolmente drogata p rispettivamente n, venga minimizzato. Con ci? viene ridotto il pericolo di un'attivazione del transistor parassita npn rispettivamente pnp. Advantageous improvements and improvements of the integrated element indicated in claim 1 and 2 are possible by means of the measures reported in the sub-claims. It is particularly advantageous to conduct the second and / or third zone up to the weakly doped layer p respectively n. So? it is obtained that a potential gradient, caused by a leakage current or by a voltage variation, which occurs between the fifth and fourth doped zones n respectively p and the first weakly doped zone p respectively n, is minimized. With us? the danger of an activation of the parasitic transistor npn or pnp is reduced.
Un miglioramento vantaggioso del componente integrato viene ottenuto collegando conduttivamente la quarta zona drogata n rispettivamente p con la seconda zona altamente drogata p rispettivamente n. Cos? la base del transistor parassita viene mantenuta allo stesso potenziale del suo emettitore. Un'inserzione del transistor parassita viene in tal modo evitata. An advantageous improvement of the integrated component is obtained by conductively connecting the fourth doped zone n respectively p with the second highly doped zone p respectively n. What? the base of the parasitic transistor is kept at the same potential as its emitter. An insertion of the parasitic transistor is thus avoided.
Un'applicazione particolarmente preferita consiste nell'eseguire il componente integrato come transistor a effetto di campo. A particularly preferred application is to run the integrated component as a field effect transistor.
Un ulteriore miglioramento delle caratteristiche parassite del transistor a effetto di campo consiste nel collegare la connessione di Source attraverso una resistenza, che ? formata preferibilmente da polisilicio, con un'alimentazione di tensione. A further improvement of the parasitic characteristics of the field effect transistor is to connect the Source connection through a resistor, which? preferably formed of polysilicon, with a voltage supply.
Un miglioramento supplementare del componente integrato come transistor a effetto di campo viene ottenuto per il fatto che sotto la quarta e quinta zona drogate n rispettivamente p, eccetto la zona che confina con il canale di conduzione del transistor a effetto di campo, viene posta completamente la seconda zona altamente drogata p rispettivamente n. Con ci? viene ottenuta un'ulteriore riduzione dell'amplificazione del transistor parassita. A further improvement of the integrated component as a field effect transistor is achieved by the fact that under the fourth and fifth doped zones n respectively p, except the zone which borders the conduction channel of the field effect transistor, the second highly doped zone p respectively n. With us? a further reduction in the amplification of the parasitic transistor is achieved.
Esempi di esecuzione dell'invenzione sono rappresentati nel disegno e spiegati pi? in dettaglio nella seguente descrizione. La figura 1 mostra un componente integrato sotto forma di un transistor a effetto di campo, la figura 2 mostra un componente integrato sotto forma di una resistenza drogata p e la figura 3 mostra un circuito equivalente per un componente integrato sotto forma di un transistor a effetto di campo con una resistenza antecedente. Examples of embodiments of the invention are shown in the drawing and explained further. in detail in the following description. Figure 1 shows an integrated component in the form of a field effect transistor, Figure 2 shows an integrated component in the form of a p-doped resistor, and Figure 3 shows an equivalent circuit for an integrated component in the form of an effect transistor field with an antecedent resistance.
La figura 1 mostra un transistor a effetto di campo, che presenta uno strato 7 drogato n, sul.quale ? disposta una prima zona 5 drogata p. La prima zona 5 drogata p viene delimitata da un lato da una seconda zona 6 altamente drogata p e dal secondo lato da una terza zona 10 altamente drogata p. Il transistor a effetto di campo, che ? formato da silicio, presenta una connessione di Source, che costituita da una quarta zona 1 drogata n, che ? disposta sulla prima zona 5 drogata p e sulla seconda zona 6 altamente drogata p. La connessione di Drain ? costituita da una quinta zona 2 drogata n, che ? disposta sulla prima zona 5 drogata p e sulla terza zona 10 altamente drogata p. Figure 1 shows a field-effect transistor, which has an n-doped layer 7, on which? a first doped zone 5 p. The first p-doped zone 5 is delimited on one side by a second p-doped highly-doped zone 6 and on the second side by a third p-doped third zone 10. The field effect transistor, which? formed by silicon, has a Source connection, which consists of a fourth n-doped zone 1, which? arranged on the first p-doped zone 5 and on the second highly doped zone 6 p. The Drain connection? consisting of a fifth zone 2 doped n, which? arranged on the first p-doped zone 5 and on the third highly doped zone 10 p.
Fra le connessioni di Drain e di Source 1, 2 ? disposto uno strato isolante 4, che in questo esempio di esecuzione ? costituito da ossido di silicio. Sullo strato isolante 4 ? applicato uno strato 3 conduttivo, che forma la connessione di Gate. La quarta 2ona 1 drogata n della connessione di Source e la quinta zona 2 drogata n della connessione di Drain sono connesse ciascuna con ulteriori zone di diffusione 8, che sono introdotte sotto la connessione di Gate 3 della prima zona 5 drogata p. Le ulteriori zone di diffusione 8 presentano un ridotto drogaggio negativo. Fra le ulteriori zone di diffusione 8 si forma, nello stato di conduzione del transistor a effetto di campo, sotto la connessione di Gate 3 il canale di conduzione del.transistor a effetto di campo. La quarta zona 1 drogata n della connessione di Source ? collegata attraverso un conduttore ohmico con la seconda zona 6 altamente drogata p. Between the connections of Drain and Source 1, 2? arranged an insulating layer 4, which in this embodiment example? consisting of silicon oxide. On the insulation layer 4? applied a conductive layer 3, which forms the Gate connection. The fourth n-doped zone 1 of the Source connection and the fifth n-doped zone 2 of the Drain connection are each connected with further diffusion zones 8, which are introduced under the Gate 3 connection of the first p-doped zone 5. The further diffusion zones 8 exhibit a reduced negative doping. Among the further diffusion zones 8, in the conduction state of the field effect transistor, the conduction channel of the field effect transistor is formed under the connection of Gate 3. The fourth zone 1 doped n of the Source connection? connected through an ohmic conductor with the second highly doped zone 6 p.
La disposizione secondo la figura 1 funziona come segue: per il fatto che sotto la quarta zona 1 drogata n ? posta la seconda zona 6 altamente drogata p, si impedisce che si formi un transistor parassita npn fra la connessione di Source, che viene formata dalla quarta zona 1, la prima zona 5 drogata p e lo strato 7 drogato n. Al posto del transistor a effetto di campo npn, pu? essere disposto anche un transistor a effetto di campo pnp, ove il drogaggio della seconda e terza zona 6, 10, della prima zona 5, dello strato 7, della quarta e quinta zona 1, 2 e delle ulteriori zone di diffusione 8 ? eseguito corrispondentemente in modo inverso. The arrangement according to Figure 1 works as follows: owing to the fact that under the fourth doped zone 1 n? once the second highly p-doped zone 6 is placed, a parasitic npn transistor is prevented from forming between the Source connection, which is formed by the fourth zone 1, the first p-doped zone 5 and the n-doped layer 7. Instead of the npn field effect transistor, it can? also a pnp field effect transistor be arranged, where the doping of the second and third zones 6, 10, of the first zone 5, of the layer 7, of the fourth and fifth zones 1, 2 and of the further diffusion zones 8? performed correspondingly in reverse.
La figura 2 mostra una resistenza integrata, che ? integrata nel silicio. La resistenza integrata ? costituita da uno strato 7 drogato p, sul quale ? applicata una prima zona 5 drogata n. La prima zona 5 viene delimitata da un lato da una seconda zona 6 altamente drogata negativamente, e da un ulteriore lato da una terza zona 10 altamente drogata negativamente. Come connessione di contatto elettrico, nella prima zona 5 e nella seconda zona 6 ? introdotta una quarta zona 1 drogata positivamente un ulteriore contatto elettrico viene formato da una quinta zona 2, che ? introdotta nella prima zona 5 e nella terza zona 10. Fra la quarta e quinta zona 1, 2 drogate p ? disposta una zona di diffusione 9 continua, che ? drogata debolmente p ed ? introdotta nella prima zona 5. La resistenza integrata pu? per? venir rappresentata anche con drogaggio inverso. Figure 2 shows an integrated resistor, which? integrated in silicon. The integrated resistance? consisting of a p-doped layer 7, on which? applied a first doped zone 5 n. The first zone 5 is delimited on one side by a second highly negatively doped zone 6, and on a further side by a third highly negatively doped zone 10. As an electrical contact connection, in the first zone 5 and in the second zone 6? when a positively doped fourth zone 1 is introduced, a further electrical contact is formed by a fifth zone 2, which? introduced in the first zone 5 and in the third zone 10. Between the fourth and fifth zone 1, 2 doped p? arranged a continuous diffusion zone 9, which? weakly doped p and d? introduced in the first zone 5. The integrated resistance can? for? be represented also with inverse doping.
Mediante la disposizione della quarta e della quinta zona 1, 2 drogata p sotto la seconda e/o terza zona 6, 10 altamente drogata n si imped?sce che si formi un transistor parassita pnp fra la zona di diffusione 9 drogata p, la prima zona 5 drogata n e lo strato 7 drogato p. By arranging the fourth and fifth p-doped zones 1, 2 under the second and / or third highly doped n zones 6, 10, a parasitic pnp transistor is prevented from forming between the p-doped diffusion zone 9, the first n-doped zone 5 and p-doped layer 7.
La figura 3 mostra il circuito equivalente di un transistor 11 parassita npn con una resistenza di emettitore RE 12 integrata monolitica. Il connettore del transistor 11 ? collegato, tramite una resistenza di carico Re 10 con una tensione di alimentazione Uv. L'emettitore del transistor 11 ? collegato a massa tramite una resistenza RE 12 ohmica. La base del transistor 11 viene alimentata mediante una tensione d'ingresso Ug. La tensione di ingresso UE si divide nella tensione UBE fra la base e l'emettitore e la caduta di tensione Ug sulla resistenza RE 12 ohmica. Se corrente fluisce attraverso il transistor 11 parassita, allora cresce la caduta di tensione sulla resistenza RE 12 ohmica. Cos? cresce la caduta di tensione UR sulla resistenza RE 12 ohmica. La tensione di comando del transistor 11 parassita risulta da Figure 3 shows the equivalent circuit of a parasitic npn transistor 11 with a monolithic integrated emitter resistor RE 12. The connector of transistor 11? connected, via a load resistor Re 10, to a supply voltage Uv. The emitter of transistor 11? connected to ground by means of a RE 12 ohmic resistor. The base of the transistor 11 is powered by means of an input voltage Ug. The input voltage UE is divided into the voltage UBE between the base and the emitter and the voltage drop Ug on the RE 12 ohmic resistor. If current flows through the parasitic transistor 11, then the voltage drop across the resistance RE 12 ohm increases. What? the voltage drop UR on the RE 12 ohmic resistor increases. The control voltage of the parasitic transistor 11 results from
ove Ig rappresenta la corrente di emettitore del transistor 11 parassita. La tensione di ingresso Ug si oppone alla tensione Ug proporzionale alla corrente di emettitore. L'amplificazione del transistor 11 parassita ? quindi inversamente proporzionale alla resistenza RE 12 ohmica. Affinch? in parallelo alla resistenza RE 12 ohmica non sia collegato parimenti un transistor parassita, questa resistenza ? costituita da polisilicio. Resistenze di emettitore di 100 Ohm sono sufficienti a limitare la corrente parassita in misura tale che il componente possa resistere senza danni a elevati fronti di tensione. where Ig represents the emitter current of the parasitic transistor 11. The input voltage Ug opposes the voltage Ug proportional to the emitter current. The amplification of the parasitic transistor 11? therefore inversely proportional to the resistance RE 12 ohmic. So that? a parasitic transistor is not connected in parallel to the RE 12 ohmic resistor, this resistor? made up of polysilicon. 100 Ohm emitter resistances are sufficient to limit the eddy current to such an extent that the component can withstand high voltage fronts without damage.
Analoghe misure sono applicabili a transistor parassiti pnp. Similar measures are applicable to parasitic pnp transistors.
Claims (7)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4405631A DE4405631C1 (en) | 1994-02-22 | 1994-02-22 | Integrated device esp. FET |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITMI950303A0 ITMI950303A0 (en) | 1995-02-20 |
| ITMI950303A1 true ITMI950303A1 (en) | 1996-08-20 |
| IT1273939B IT1273939B (en) | 1997-07-11 |
Family
ID=6510869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITMI950303A IT1273939B (en) | 1994-02-22 | 1995-02-20 | PARTICULARLY INTEGRATED COMPONENT TO PREVENT THE FORMATION OF A PARASITE TRANSISTOR |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH07263670A (en) |
| DE (1) | DE4405631C1 (en) |
| FR (1) | FR2716574A1 (en) |
| IT (1) | IT1273939B (en) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3751722A (en) * | 1971-04-30 | 1973-08-07 | Standard Microsyst Smc | Mos integrated circuit with substrate containing selectively formed resistivity regions |
| US3990092A (en) * | 1974-01-11 | 1976-11-02 | Hitachi, Ltd. | Resistance element for semiconductor integrated circuit |
| US4394674A (en) * | 1979-10-09 | 1983-07-19 | Nippon Electric Co., Ltd. | Insulated gate field effect transistor |
| JPS5994873A (en) * | 1982-11-22 | 1984-05-31 | Nissan Motor Co Ltd | Metal oxide semiconductor transistor |
| JPS59198749A (en) * | 1983-04-25 | 1984-11-10 | Mitsubishi Electric Corp | Complementary type field effect transistor |
| JP3206026B2 (en) * | 1991-07-19 | 2001-09-04 | 富士電機株式会社 | Semiconductor device having high voltage MISFET |
| JPH06180858A (en) * | 1992-12-10 | 1994-06-28 | Hitachi Maxell Ltd | Optical disk and its production |
| JPH075386A (en) * | 1993-06-15 | 1995-01-10 | Nikon Corp | Optical scanner |
-
1994
- 1994-02-22 DE DE4405631A patent/DE4405631C1/en not_active Expired - Fee Related
-
1995
- 1995-01-23 FR FR9500726A patent/FR2716574A1/en active Pending
- 1995-02-20 IT ITMI950303A patent/IT1273939B/en active IP Right Grant
- 1995-02-21 JP JP7032552A patent/JPH07263670A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| IT1273939B (en) | 1997-07-11 |
| JPH07263670A (en) | 1995-10-13 |
| ITMI950303A0 (en) | 1995-02-20 |
| FR2716574A1 (en) | 1995-08-25 |
| DE4405631C1 (en) | 1995-07-20 |
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