FR2716574A1 - Integrated component. - Google Patents
Integrated component. Download PDFInfo
- Publication number
- FR2716574A1 FR2716574A1 FR9500726A FR9500726A FR2716574A1 FR 2716574 A1 FR2716574 A1 FR 2716574A1 FR 9500726 A FR9500726 A FR 9500726A FR 9500726 A FR9500726 A FR 9500726A FR 2716574 A1 FR2716574 A1 FR 2716574A1
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- Prior art keywords
- zone
- doping
- doped
- integrated component
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 150000001768 cations Chemical class 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 18
- 238000009792 diffusion process Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
- H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
a) L'invention concerne un composant intégré. b) Composant intégré à deux zones à dopage n prévu dans une première zone (5) à dopage p. La première zone (5) se trouve sur une couche (7) à dopage n. Au moins une zone à dopage n trouve en dessous d'elle une quatrième zone à fort dopage p. On évite ainsi le développement d'un transistor parasite npn entre la zone à dopage n, la première zone (5) à dopage p et la couche (7) à dopage n.a) The invention relates to an integrated component. b) Integrated component with two n-doped zones provided in a first p-doped zone (5). The first zone (5) is on an n-doped layer (7). At least one n-doped zone finds below it a fourth heavily p-doped zone. The development of a parasitic transistor npn between the n-doped zone, the first p-doped zone (5) and the n-doped layer (7) is thus avoided.
Description
" Composant intégré ""Integrated component"
Etat de la technique: L'invention concerne un composant intégré comportant une première zone à faible dopage p, prévue sur une couche à dopage n, au moins une quatrième et une cinquième zone, à dopage n étant prévues dans la première zone à do- page p. On connaît déjà un transistor à effet de champ sous la forme d'un composant intégré ayant une zone à do- page p sur un substrat à dopage n. Deux zones à dopage n sont intégrées dans la zone à dopage p et entre les zones dopage n, une porte est disposée. Les deux zones à dopage n forment la source et le drain du transistor à effet de champ. STATE OF THE ART: The invention relates to an integrated component comprising a first zone with low p-doping, provided on an n-doped layer, at least a fourth and a n-doped zone being provided in the first zone to be doped. page p. A field effect transistor is already known in the form of an integrated component having a dot area p on an n-doped substrate. Two n doping zones are integrated in the p doping zone and between the n doping zones, a gate is arranged. The two doping zones n form the source and the drain of the field effect transistor.
Avantages de l'invention: Le composant intégré selon l'invention est carac- térisé en ce qu'au moins une quatrième et/ou une cinquième zone à dopage n comportent partiellement en dessous d'elles une seconde et/ou une seconde troisième zone à fort dopage p. Suivant une autre caractéristique de l'invention, au moins une quatrième et/ou une cinquième zone à dopage p comportent partiellement en dessous d'elles une seconde et/ou une troisième zone à fort dopage n. Advantages of the invention: The integrated component according to the invention is characterized in that at least a fourth and / or a fifth n-doped zone comprises partially below them a second and / or a second third zone. with high doping p. According to another characteristic of the invention, at least one fourth and / or fifth p-doped zone comprises, partially below them, a second and / or a third zone with high n-doping.
Le composant offre l'avantage d'éviter la forma- tion d'un transistor parasite de type npn ou pnp. En pla- çant sous la quatrième et/ou la cinquième zone à dopage n ou p, une seconde et/ou une troisième zone à fort dopage p ou n, on assure un dopage fort de la base du transistor parasite de type npn ou pnp et on arrive ainsi à une faible amplification du transistor parasite de type npn ou de pnp ce qui élimine les effets parasites. The component offers the advantage of avoiding the formation of a parasitic transistor of the npn or pnp type. By placing under the fourth and / or the fifth n or p doped zone, a second and / or a third zone with high p or n doping, strong doping of the base of the npn or pnp type parasitic transistor is provided. and we thus arrive at a weak amplification of the parasitic transistor of npn or pnp type which eliminates parasitic effects.
Il est particulièrement avantageux que la seconde et/ou la troisième zone conduise jusqu'à une couche à fai- ble dopage p ou n. On arrive ainsi à résoudre au minimum une chute de tension créée par un courant de fuite ou une variation de potentiel, entre le cinquième et le quatrième domaine à dopage n ou p et entre la première zone faible- ment dopée en p ou n. Cela diminue ainsi le risque d'une commande du transistor parasite de type npn ou pnp. It is particularly advantageous for the second and / or third zone to lead to a low doping layer p or n. Thus, at least a voltage drop created by a leakage current or a potential variation between the fifth and fourth n-doped or p-doped domain and between the first weakly p-or n-doped zone is resolved. This thus reduces the risk of a control of the npn or pnp type parasitic transistor.
Un perfectionnement avantageux du composant inté- gré résulte de ce que la quatrième zone à dopage p ou n soit reliée à la seconde zone à fort dopage p ou n. Ainsi, la base du transistor parasite est maintenue au même potentiel que son émetteur. On évite de cette manière la mise en oeuvre du transistor parasite. An advantageous improvement of the integrated component results from the fact that the fourth doping zone p or n is connected to the second high-doping zone p or n. Thus, the base of the parasitic transistor is maintained at the same potential as its emitter. This avoids the use of the parasitic transistor.
Une application particulièrement avantageuse con- siste à réaliser le composant intégré comme transistor à effet de champ. A particularly advantageous application is to realize the integrated component as a field effect transistor.
Une autre amélioration des caractéristiques para- sites du transistor à effet de champ résulte du branchement de la source par une résistance, de préférence en polysili- cium, pour assurer la liaison avec une alimentation en ten- sion. Another improvement in the parasitic characteristics of the field effect transistor results from the connection of the source by a resistor, preferably polysilicon, to provide the connection with a power supply.
Un perfectionnement supplémentaire du composant intégré comme transistor à effet de champ résulte de ce que la quatrième et la cinquième zone à dopage n ou p, jusqu'à la zone adjacente au canal de conduction du transistor à effet de champ, sont complètement occupées en dessous d'elles par une seconde zone à fort dopage p ou n. On réduit ainsi, en plus l'amplification du transistor parasite. A further refinement of the integrated component as a field effect transistor results from the fact that the fourth and the fifth n-doped or p-doped zone up to the area adjacent to the conduction channel of the field effect transistor are completely occupied below. of them by a second zone with high doping p or n. This further reduces the amplification of the parasitic transistor.
Dessins: Les exemples de réalisation de l'invention sont représentés dans les dessins et sont décrits ci-après de manière plus détaillée. Ainsi: la figure 1 montre un composant intégré sous la forme d'un transistor à effet de champ, - la figure 2 montre un composant intégré sous la forme d'une résistance à dopage p, - la figure 3 montre un schéma équivalent d'un composant intégré sous la forme d'un transistor à effet de champ avec une résistance intermédiaire. Drawings: The exemplary embodiments of the invention are shown in the drawings and are hereinafter described in more detail. Thus: FIG. 1 shows an integrated component in the form of a field effect transistor; FIG. 2 shows an integrated component in the form of a p-doped resistor; FIG. an integrated component in the form of a field effect transistor with an intermediate resistance.
Description des exemples de réalisation: Description of the examples of realization:
La figure 1 montre un transistor à effet de champ ayant une couche 7 à dopage n et au-dessus de cette couche une première zone 5 à dopage p. La première zone 5 à dopage p est délimitée d'un côté par une seconde zone 6 à fort do- page p et de l'autre côté par une troisième zone 10 à fort dopage p. Le transistor à effet de champ formé en silicium présente un branchement de source composé d'une quatrième zone 1 à dopage n prévue sur la première zone 5 à dopage p et sur la seconde zone 6 à fort dopage p. Le branchement de drain se compose d'une cinquième zone 2 à dopage n prévue sur la première zone 5 à dopage p et sur la troisième zone à fort dopage p. Dans le présent exemple de réalisation entre le branchement de drain 2 et le branchement de source 1, il y a une couche d'isolation 4 en oxyde de silicium. Sur la couche d'isolation 4, il y a une couche conductrice 3 for- mant le branchement de porte. La quatrième zone 1 à dopage n du branchement de source et la cinquième zone 2 à dopage n du branchement de drain sont reliées respectivement à une autre zone de diffusion 8 prévue sous le branchement de porte 3 dans la première zone 5 à dopage p. Les autres zo- nes de diffusion 8 ont un dopage négatif faible. A l'état de conduction du transistor à effet de champ, il se forme entre les autres zones de diffusion 8, le canal de conduc- tion du transistor à effet de champ sous le branchement de porte 3. Le quatrième domaine 1 à dopage n du branchement de source est relié par une liaison ohmique à la seconde zone 6 à fort dopage p. Le dispositif de la figure 1 fonctionne de la manière suivante: comme la quatrième zone 1 à dopage n du branchement de source comporte en dessous de lui la seconde zone 6 à fort dopage p, on évite la formation d'un transis- tor npn parasite entre le branchement de source formé par la quatrième zone 1, la première zone 5 à dopage p et la couche 7 à dopage n. A la place du transistor à effet de champ npn, on peut également prévoir un transistor à effet de champ pnp et le dosage de la seconde et de la troisième zone 6, 10, de la première zone 5, de la couche 7, de la quatrième et de la cinquième zone 1, 2, des autres zones de diffusion 8 sont réalisées de manière inverse. FIG. 1 shows a field effect transistor having an n-doped layer 7 and above this layer a first p-doped zone 5. The first p-doped zone 5 is delimited on one side by a second zone 6 with a high p-value and on the other side by a third zone 10 with high p-doping. The field-effect transistor formed in silicon has a source connection composed of a fourth n-doped zone 1 provided on the first p-doped zone 5 and on the second p-doped zone 6. The drain connection consists of a fifth n-doped zone 2 provided on the first p-doped zone 5 and on the third p-doped zone. In the present embodiment between the drain connection 2 and the source connection 1, there is an insulating layer 4 made of silicon oxide. On the insulating layer 4 there is a conductive layer 3 forming the door connection. The fourth n-doped zone 1 of the source connection and the fifth n-doped zone 2 of the drain connection are respectively connected to another diffusion zone 8 provided under the door connection 3 in the first p-doped zone 5. The other diffusion regions 8 have low negative doping. In the conduction state of the field effect transistor, the conducting channel of the field effect transistor is formed between the other diffusion zones 8 under the gate connection 3. The fourth doping domain 1 the source connection is connected by an ohmic connection to the second zone 6 with high p-doping. The device of FIG. 1 operates in the following manner: since the fourth n-doped zone 1 of the source branch has the second p-doped zone 6 below it, the formation of a parasitic npn transistor is avoided. between the source connection formed by the fourth zone 1, the first p-doped zone 5 and the n-doped layer 7. Instead of the field effect transistor npn, it is also possible to provide a pnp field effect transistor and the determination of the second and third zones 6, 10, of the first zone 5, of the layer 7, of the fourth and fifth zone 1, 2, other diffusion zones 8 are performed in a reverse manner.
La figure 2 montre une résistance intégrée dans le silicium. La résistance intégrée se compose d'une couche 7 à dopage p sur laquelle il y a une première zone 5 à do- page n. La première zone 5 est délimitée d'un côté par une seconde zone 6 à dopage très négatif et d'un autre côté par une troisième zone 10 à dopage fortement négatif. Comme branchement de contact électrique, il y a une quatrième zone 1 à dopage positif intégrée dans la première zone 5 et dans la seconde zone 6. Un autre contact électrique est formé par une cinquième zone 2 réalisée dans la première zone 5 et dans la troisième zone 10. Entre la quatrième et la cinquième zone 1, 2 à dopage p, il y a une zone de dif- fusion 9, continue, à faible dopage p qui est réalisée dans la première zone 5. La résistance intégrée peut toutefois être constituée également par un dopage inverse. Figure 2 shows an integrated resistance in silicon. The built-in resistor consists of a p-doped layer 7 on which there is a first zone 5 with a dot-in. The first zone 5 is delimited on one side by a second zone 6 with a very negative doping and on the other side by a third zone 10 with a strong negative doping. As an electrical contact connection, there is a fourth positive doping zone 1 integrated in the first zone 5 and in the second zone 6. Another electrical contact is formed by a fifth zone 2 made in the first zone 5 and in the third zone 5. zone 10. Between the fourth and fifth zones 1, 2 with p-doping, there is a diffusion area 9, which is continuous, with low p-doping, which is produced in the first zone 5. However, the integrated resistor may consist of also by reverse doping.
Comme en dessous de la quatrième et de la cin- quième zone 1, 2 à dopage p, il y a la seconde et/ou la troisième zone 6, 10 à fort dopage n, on évite le dévelop- pement d'un transistor parasite pnp entre la zone de diffu- sion 9 à dopage p et la première zone 5 à dopage n et la couche 7 à dopage p. La figure 3 montre le schéma équivalent d'un transistor 11 de type npn parasite avec une résistance d'émetteur RE 12, monolithique, intégrée. Le collecteur du transistor 11 est relié à la tension d'alimentation Uv par une résistance de charge Rc 10. L'émetteur du transistor 11 est relié à la masse par une résistance ohmique RE 12. La base du transistor 11 est alimentée par la tension d'entrée UE. La tension d'entrée UE se répartit entre la tension UBE comprise entre la base et l'émetteur et la chute de tension UR sur la résistance ohmique RE 12. Lorsque le courant tra- verse le transistor parasite 11, la chute de tension aux bornes de la résistance ohmique RE 12 augmente. La chute de tension UR aux bornes de la résistance ohmique RE 12 aug- mente également. La commande du transistor parasite 11 ré- sulte de la formule suivante: UBE = UE - IE RE Dans cette formule, IE représente le courant d'émetteur du transistor parasite 11. La tension d'entrée UE s'oppose à la tension UR proportionnelle au courant d'émetteur. L'amplification du transistor parasite 11 est ainsi inversement proportionnelle à la résistance ohmique RE 12. Pour ne pas avoir également un transistor parasite en parallèle à la résistance ohmique RE 12, on réalise cette résistance en polysilicium. Des résistances d'émet- teur de 100 ohms suffisent pour limiter le courant parasite pour que le composant résiste sans difficulté à des flancs de tension élevés. Since below the fourth and fifth p-doped zones 1, 2 there is the second and / or third zone 6, 10 with high n-doping, the development of a parasitic transistor is avoided. pnp between the p-doped diffusion region 9 and the first n-doped zone 5 and the p-doped layer 7. FIG. 3 shows the equivalent diagram of a parasitic npn type transistor 11 with a built-in monolithic RE 12 emitter resistor. The collector of the transistor 11 is connected to the supply voltage Uv by a load resistor Rc 10. The emitter of the transistor 11 is connected to ground by an ohmic resistor RE 12. The base of the transistor 11 is powered by the voltage EU entry. The input voltage UE is distributed between the voltage UBE between the base and the transmitter and the voltage drop UR on the resistance resistor RE 12. When the current flows through the parasitic transistor 11, the voltage drop across the terminals ohmic resistance RE 12 increases. The voltage drop UR across the ohmic resistance RE 12 also increases. The control of the parasitic transistor 11 results from the following formula: UBE = UE - IE RE In this formula, IE represents the emitter current of the parasitic transistor 11. The input voltage UE opposes the proportional voltage UR transmitter current. The amplification of the parasitic transistor 11 is thus inversely proportional to the resistive resistance RE 12. In order not also to have a parasitic transistor in parallel with the ohmic resistance RE 12, this polysilicon resistor is realized. Transmitter resistors of 100 ohms are sufficient to limit the stray current so that the component can easily withstand high voltage edges.
Des moyens analogues peuvent être appliqués aux transistors parasites de type pnp. Analogous means can be applied to pnp type interference transistors.
Claims (7)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4405631A DE4405631C1 (en) | 1994-02-22 | 1994-02-22 | Integrated device esp. FET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2716574A1 true FR2716574A1 (en) | 1995-08-25 |
Family
ID=6510869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR9500726A Pending FR2716574A1 (en) | 1994-02-22 | 1995-01-23 | Integrated component. |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH07263670A (en) |
| DE (1) | DE4405631C1 (en) |
| FR (1) | FR2716574A1 (en) |
| IT (1) | IT1273939B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3990092A (en) * | 1974-01-11 | 1976-11-02 | Hitachi, Ltd. | Resistance element for semiconductor integrated circuit |
| US4394674A (en) * | 1979-10-09 | 1983-07-19 | Nippon Electric Co., Ltd. | Insulated gate field effect transistor |
| EP0109692A1 (en) * | 1982-11-22 | 1984-05-30 | Nissan Motor Co., Ltd. | Semiconductor device for a MOSFET |
| JPH06180858A (en) * | 1992-12-10 | 1994-06-28 | Hitachi Maxell Ltd | Optical disk and its production |
| JPH075386A (en) * | 1993-06-15 | 1995-01-10 | Nikon Corp | Optical scanner |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3751722A (en) * | 1971-04-30 | 1973-08-07 | Standard Microsyst Smc | Mos integrated circuit with substrate containing selectively formed resistivity regions |
| JPS59198749A (en) * | 1983-04-25 | 1984-11-10 | Mitsubishi Electric Corp | Complementary type field effect transistor |
| JP3206026B2 (en) * | 1991-07-19 | 2001-09-04 | 富士電機株式会社 | Semiconductor device having high voltage MISFET |
-
1994
- 1994-02-22 DE DE4405631A patent/DE4405631C1/en not_active Expired - Fee Related
-
1995
- 1995-01-23 FR FR9500726A patent/FR2716574A1/en active Pending
- 1995-02-20 IT ITMI950303A patent/IT1273939B/en active IP Right Grant
- 1995-02-21 JP JP7032552A patent/JPH07263670A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3990092A (en) * | 1974-01-11 | 1976-11-02 | Hitachi, Ltd. | Resistance element for semiconductor integrated circuit |
| US4394674A (en) * | 1979-10-09 | 1983-07-19 | Nippon Electric Co., Ltd. | Insulated gate field effect transistor |
| EP0109692A1 (en) * | 1982-11-22 | 1984-05-30 | Nissan Motor Co., Ltd. | Semiconductor device for a MOSFET |
| JPH06180858A (en) * | 1992-12-10 | 1994-06-28 | Hitachi Maxell Ltd | Optical disk and its production |
| JPH075386A (en) * | 1993-06-15 | 1995-01-10 | Nikon Corp | Optical scanner |
Non-Patent Citations (5)
| Title |
|---|
| ABDELLATIF ELMOZNINE ET AL: "The Smart Power High-Side Switch: Description of a Specific Technology, Its Basic Devices, and Monitoring Circuitries", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 37, no. 4, NEW YORK, US, pages 1154 - 1161, XP000125232 * |
| H. SAKUMA ET AL: "PARASITIC EFFECT-FREE, HIGH VOLTAGE MOS ICs WITH SHIELDED SOURCE STRUCTURE", TECHNICAL DIGEST OF THE INTERNATIONAL ELECTRON DEVICES MEETING 1982, SAN FRANCICO, CA DECEMBER 13-14-15 1982, pages 254 - 257 * |
| JUNJI KOGA ET AL: "Sub-20 psec Switching Cmos at Liquid N2 Temperature", INT. CONF. ON SOLID STATE DEVICES & MATERIALS, TSUKUBA, AUGUST 26-28, TOKYO, JAPAN, pages 502 - 504, XP000312261 * |
| PATENT ABSTRACTS OF JAPAN vol. 10, no. 251 (E - 432) 28 August 1986 (1986-08-28) * |
| PATENT ABSTRACTS OF JAPAN vol. 16, no. 291 (E - 1224) 26 June 1992 (1992-06-26) * |
Also Published As
| Publication number | Publication date |
|---|---|
| IT1273939B (en) | 1997-07-11 |
| JPH07263670A (en) | 1995-10-13 |
| ITMI950303A0 (en) | 1995-02-20 |
| DE4405631C1 (en) | 1995-07-20 |
| ITMI950303A1 (en) | 1996-08-20 |
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