ITMI20041968A1 - "metodo e sistema per la gestione dei bit di indirizzo durante le operazioni di programmazione bufferizzata in un dispositivo di memoria" - Google Patents

"metodo e sistema per la gestione dei bit di indirizzo durante le operazioni di programmazione bufferizzata in un dispositivo di memoria"

Info

Publication number
ITMI20041968A1
ITMI20041968A1 IT001968A ITMI20041968A ITMI20041968A1 IT MI20041968 A1 ITMI20041968 A1 IT MI20041968A1 IT 001968 A IT001968 A IT 001968A IT MI20041968 A ITMI20041968 A IT MI20041968A IT MI20041968 A1 ITMI20041968 A1 IT MI20041968A1
Authority
IT
Italy
Prior art keywords
memory device
address bit
programming operations
management during
bit management
Prior art date
Application number
IT001968A
Other languages
English (en)
Inventor
Simone Bartoli
Donato Ferrario
Davide Manfre
Stefano Surico
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to IT001968A priority Critical patent/ITMI20041968A1/it
Publication of ITMI20041968A1 publication Critical patent/ITMI20041968A1/it
Priority to US11/123,682 priority patent/US7404049B2/en
Priority to PCT/US2005/035658 priority patent/WO2006044190A2/en
Priority to TW094135318A priority patent/TWI296759B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Read Only Memory (AREA)
IT001968A 2004-10-15 2004-10-15 "metodo e sistema per la gestione dei bit di indirizzo durante le operazioni di programmazione bufferizzata in un dispositivo di memoria" ITMI20041968A1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT001968A ITMI20041968A1 (it) 2004-10-15 2004-10-15 "metodo e sistema per la gestione dei bit di indirizzo durante le operazioni di programmazione bufferizzata in un dispositivo di memoria"
US11/123,682 US7404049B2 (en) 2004-10-15 2005-05-06 Method and system for managing address bits during buffered program operations in a memory device
PCT/US2005/035658 WO2006044190A2 (en) 2004-10-15 2005-10-04 Managing address bits during buffered program operations
TW094135318A TWI296759B (en) 2004-10-15 2005-10-11 Method and system for managing address bits during buffered program operations in a memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT001968A ITMI20041968A1 (it) 2004-10-15 2004-10-15 "metodo e sistema per la gestione dei bit di indirizzo durante le operazioni di programmazione bufferizzata in un dispositivo di memoria"

Publications (1)

Publication Number Publication Date
ITMI20041968A1 true ITMI20041968A1 (it) 2005-01-15

Family

ID=36182171

Family Applications (1)

Application Number Title Priority Date Filing Date
IT001968A ITMI20041968A1 (it) 2004-10-15 2004-10-15 "metodo e sistema per la gestione dei bit di indirizzo durante le operazioni di programmazione bufferizzata in un dispositivo di memoria"

Country Status (4)

Country Link
US (1) US7404049B2 (it)
IT (1) ITMI20041968A1 (it)
TW (1) TWI296759B (it)
WO (1) WO2006044190A2 (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7414891B2 (en) 2007-01-04 2008-08-19 Atmel Corporation Erase verify method for NAND-type flash memories

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4839796A (en) * 1987-07-16 1989-06-13 Icon International, Inc. Static frame digital memory
US6081878A (en) 1997-03-31 2000-06-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
JP2000173289A (ja) 1998-12-10 2000-06-23 Toshiba Corp エラー訂正可能なフラッシュメモリシステム
JP2001229021A (ja) * 2000-02-18 2001-08-24 Mitsubishi Electric Corp データ処理装置
US6466508B1 (en) * 2000-11-28 2002-10-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having high-speed read function
US6584034B1 (en) 2001-04-23 2003-06-24 Aplus Flash Technology Inc. Flash memory array structure suitable for multiple simultaneous operations
JP2005092923A (ja) * 2003-09-12 2005-04-07 Renesas Technology Corp 半導体記憶装置

Also Published As

Publication number Publication date
WO2006044190A3 (en) 2007-03-15
TWI296759B (en) 2008-05-11
US7404049B2 (en) 2008-07-22
TW200630796A (en) 2006-09-01
WO2006044190A2 (en) 2006-04-27
US20060085622A1 (en) 2006-04-20

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