IT998133B - EQUIPMENT TO GENERATE THE SAMPLE TEST SAMPLE FOR ASYNCHRONOUS SEQUENTIAL CIRCUITS - Google Patents
EQUIPMENT TO GENERATE THE SAMPLE TEST SAMPLE FOR ASYNCHRONOUS SEQUENTIAL CIRCUITSInfo
- Publication number
- IT998133B IT998133B IT2516773A IT2516773A IT998133B IT 998133 B IT998133 B IT 998133B IT 2516773 A IT2516773 A IT 2516773A IT 2516773 A IT2516773 A IT 2516773A IT 998133 B IT998133 B IT 998133B
- Authority
- IT
- Italy
- Prior art keywords
- state
- sequence
- sample
- generate
- equipment
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
1381413 Generating test patterns INTERNATIONAL BUSINESS MACHINES CORP 4 May 1973 [21 June 1972] 21222/73 Heading G4A A homing sequence for placing a sequential logic circuit in a predetermined state, compatible with testing by a testing sequence, is generated by data processing apparatus arranged to derive the sequence in reverse order from the total state (input variables and circuit state variables) corresponding to the desired set state. A sequence of total states is derived until a state having no circuit state variables is reached, this state defining the start of the homing sequence. Details of an algorithm for generating the homing sequence are described with reference to Fig. 5 (not shown). Specification 1,381,414 is referred to.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US26503572A | 1972-06-21 | 1972-06-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
IT998133B true IT998133B (en) | 1976-01-20 |
Family
ID=23008681
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT2516773A IT998133B (en) | 1972-06-21 | 1973-06-12 | EQUIPMENT TO GENERATE THE SAMPLE TEST SAMPLE FOR ASYNCHRONOUS SEQUENTIAL CIRCUITS |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS4952547A (en) |
CA (1) | CA990405A (en) |
GB (1) | GB1381413A (en) |
IT (1) | IT998133B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4184630A (en) * | 1978-06-19 | 1980-01-22 | International Business Machines Corporation | Verifying circuit operation |
US4853928A (en) * | 1987-08-28 | 1989-08-01 | Hewlett-Packard Company | Automatic test generator for logic devices |
US5097468A (en) * | 1988-05-03 | 1992-03-17 | Digital Equipment Corporation | Testing asynchronous processes |
DE69333806T2 (en) * | 1992-03-27 | 2005-10-06 | Matsushita Electric Industrial Co., Ltd., Kadoma | Method and apparatus for test sequence generation |
-
1973
- 1973-05-04 GB GB2122273A patent/GB1381413A/en not_active Expired
- 1973-05-10 JP JP48051217A patent/JPS4952547A/ja active Pending
- 1973-05-15 CA CA171,632A patent/CA990405A/en not_active Expired
- 1973-06-12 IT IT2516773A patent/IT998133B/en active
Also Published As
Publication number | Publication date |
---|---|
JPS4952547A (en) | 1974-05-22 |
GB1381413A (en) | 1975-01-22 |
CA990405A (en) | 1976-06-01 |
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