ES246497A1 - Timing circuit - Google Patents

Timing circuit

Info

Publication number
ES246497A1
ES246497A1 ES0246497A ES246497A ES246497A1 ES 246497 A1 ES246497 A1 ES 246497A1 ES 0246497 A ES0246497 A ES 0246497A ES 246497 A ES246497 A ES 246497A ES 246497 A1 ES246497 A1 ES 246497A1
Authority
ES
Spain
Prior art keywords
groups
transferred
encrypted
stored
timing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES0246497A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of ES246497A1 publication Critical patent/ES246497A1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/17—Time-division multiplex systems in which the transmission channel allotted to a first user may be taken away and re-allotted to a second user if the first user becomes inactive, e.g. TASI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

An electrical apparatus for simultaneously synchronizing several overlapping operations, characterized by the provision of a recurring key generator to progressively generate several determined or discrete encrypted groups; means for storing only some selected groups among them, the selection of each of these groups being made at the beginning of the respective operation; means to transfer each one of said generated groups to another of them; means for comparing the transferred encrypted groups with each one of the stored ones, and means that respond to coincidences between the transferred groups and each one of the stored groups, to finish the respective reference operation. (Machine-translation by Google Translate, not legally binding)
ES0246497A 1957-12-24 1958-12-20 Timing circuit Expired ES246497A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US704927A US2957945A (en) 1957-12-24 1957-12-24 Timing circuit

Publications (1)

Publication Number Publication Date
ES246497A1 true ES246497A1 (en) 1959-06-01

Family

ID=24831408

Family Applications (1)

Application Number Title Priority Date Filing Date
ES0246497A Expired ES246497A1 (en) 1957-12-24 1958-12-20 Timing circuit

Country Status (8)

Country Link
US (1) US2957945A (en)
JP (1) JPS372563B1 (en)
BE (1) BE574121A (en)
DE (1) DE1183958B (en)
ES (1) ES246497A1 (en)
FR (1) FR1215377A (en)
GB (1) GB861515A (en)
NL (1) NL234515A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3092808A (en) * 1959-05-18 1963-06-04 Acf Ind Inc Continuously variable digital delay line
US3241067A (en) * 1961-04-21 1966-03-15 Bell Telephone Labor Inc Synchronization of decoder systems based on message wave statistics
DE1219983B (en) * 1963-04-24 1966-06-30 Licentia Gmbh Circuit arrangement for the adjustable delay of a signal using a forward binary counter
US3921133A (en) * 1970-12-07 1975-11-18 Honeywell Inf Systems Controllable timing device for signalling the end of an interval
US4220990A (en) * 1978-09-25 1980-09-02 Bell Telephone Laboratories, Incorporated Peripheral processor multifunction timer for data processing systems
JPS56106421A (en) * 1980-01-29 1981-08-24 Nippon Hoso Kyokai <Nhk> Constant ratio delay circuit
FR2604270B1 (en) * 1986-09-22 1991-10-18 Jutand Francis BINARY ADDITIONER COMPRISING A FIXED OPERAND, AND PARALLEL-SERIAL BINARY MULTIPLIER COMPRISING SUCH AN ADDITIONER

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2518405A (en) * 1946-11-18 1950-08-08 Hendrik C A Van Duuren Signal storing and code converting radio telegraph system
GB692412A (en) * 1948-04-30 1953-06-03 Standard Telephones Cables Ltd Improvements in or relating to telecommunication exchange systems
US2541932A (en) * 1948-05-19 1951-02-13 Bell Telephone Labor Inc Multiplex speech interpolation system
US2577141A (en) * 1948-06-10 1951-12-04 Eckert Mauchly Comp Corp Data translating apparatus
US2779933A (en) * 1950-03-29 1957-01-29 Itt Complex pulse communication system
US2669706A (en) * 1950-05-09 1954-02-16 Bell Telephone Labor Inc Code selector
GB722179A (en) * 1950-05-17
US2692303A (en) * 1950-12-19 1954-10-19 Bell Telephone Labor Inc Speech interpolated communication system
US2674733A (en) * 1952-12-02 1954-04-06 Hughes Tool Co Electronic sorting system
US2744955A (en) * 1953-08-24 1956-05-08 Rca Corp Reversible electronic code translators
US2827623A (en) * 1955-01-21 1958-03-18 Ernest F Ainsworth Magnetic tape inscriber-outscriber

Also Published As

Publication number Publication date
GB861515A (en) 1961-02-22
BE574121A (en) 1959-04-16
JPS372563B1 (en) 1962-05-24
US2957945A (en) 1960-10-25
DE1183958B (en) 1964-12-23
NL234515A (en)
FR1215377A (en) 1960-04-19

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