IT993439B - Procedimento per ottenere strut ture del tipo mis - Google Patents

Procedimento per ottenere strut ture del tipo mis

Info

Publication number
IT993439B
IT993439B IT29420/73A IT2942073A IT993439B IT 993439 B IT993439 B IT 993439B IT 29420/73 A IT29420/73 A IT 29420/73A IT 2942073 A IT2942073 A IT 2942073A IT 993439 B IT993439 B IT 993439B
Authority
IT
Italy
Prior art keywords
mis
procedure
obtaining structures
obtaining
structures
Prior art date
Application number
IT29420/73A
Other languages
English (en)
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of IT993439B publication Critical patent/IT993439B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT29420/73A 1972-09-27 1973-09-26 Procedimento per ottenere strut ture del tipo mis IT993439B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47096157A JPS4953776A (it) 1972-09-27 1972-09-27

Publications (1)

Publication Number Publication Date
IT993439B true IT993439B (it) 1975-09-30

Family

ID=14157510

Family Applications (1)

Application Number Title Priority Date Filing Date
IT29420/73A IT993439B (it) 1972-09-27 1973-09-26 Procedimento per ottenere strut ture del tipo mis

Country Status (8)

Country Link
US (1) US3972756A (it)
JP (1) JPS4953776A (it)
CA (1) CA986234A (it)
DE (1) DE2348199A1 (it)
FR (1) FR2200629B1 (it)
GB (1) GB1440643A (it)
IT (1) IT993439B (it)
NL (1) NL7313162A (it)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5228881A (en) * 1975-08-29 1977-03-04 Toko Inc Silicon gated, field effect semiconductor device
GB1545208A (en) * 1975-09-27 1979-05-02 Plessey Co Ltd Electrical solid state devices
JPS5917529B2 (ja) * 1977-11-29 1984-04-21 富士通株式会社 半導体装置の製造方法
DE2754066A1 (de) * 1977-12-05 1979-06-13 Siemens Ag Herstellung einer integrierten schaltung mit abgestuften schichten aus isolations- und elektrodenmaterial
US4149307A (en) * 1977-12-28 1979-04-17 Hughes Aircraft Company Process for fabricating insulated-gate field-effect transistors with self-aligned contacts
JPS5492175A (en) * 1977-12-29 1979-07-21 Fujitsu Ltd Manufacture of semiconductor device
US4251571A (en) * 1978-05-02 1981-02-17 International Business Machines Corporation Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon
USRE32351E (en) * 1978-06-19 1987-02-17 Rca Corporation Method of manufacturing a passivating composite comprising a silicon nitride (SI1 3N4) layer and a phosphosilicate glass (PSG) layer for a semiconductor device layer
US4668973A (en) * 1978-06-19 1987-05-26 Rca Corporation Semiconductor device passivated with phosphosilicate glass over silicon nitride
JPS5534444A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4343078A (en) * 1979-03-05 1982-08-10 Nippon Electric Co., Ltd. IGFET Forming method
US4355454A (en) * 1979-09-05 1982-10-26 Texas Instruments Incorporated Coating device with As2 -O3 -SiO2
US4287661A (en) * 1980-03-26 1981-09-08 International Business Machines Corporation Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
US5879994A (en) * 1997-04-15 1999-03-09 National Semiconductor Corporation Self-aligned method of fabricating terrace gate DMOS transistor
US10138681B2 (en) 2016-08-16 2018-11-27 John Crawford Ladder tie off system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3474310A (en) * 1967-02-03 1969-10-21 Hitachi Ltd Semiconductor device having a sulfurtreated silicon compound thereon and a method of making the same
US3475234A (en) * 1967-03-27 1969-10-28 Bell Telephone Labor Inc Method for making mis structures
US3646665A (en) * 1970-05-22 1972-03-07 Gen Electric Complementary mis-fet devices and method of fabrication
US3700508A (en) * 1970-06-25 1972-10-24 Gen Instrument Corp Fabrication of integrated microcircuit devices
JPS4917073A (it) * 1972-06-09 1974-02-15
JPS5148948B2 (it) * 1972-09-07 1976-12-23

Also Published As

Publication number Publication date
US3972756A (en) 1976-08-03
JPS4953776A (it) 1974-05-24
GB1440643A (en) 1976-06-23
FR2200629A1 (it) 1974-04-19
CA986234A (en) 1976-03-23
NL7313162A (it) 1974-03-29
FR2200629B1 (it) 1977-09-09
DE2348199A1 (de) 1974-05-02

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