IT986462B - Procedimento per la realizzazione dei contatti elettrici per circui ti integpati - Google Patents

Procedimento per la realizzazione dei contatti elettrici per circui ti integpati

Info

Publication number
IT986462B
IT986462B IT68758/73A IT6875873A IT986462B IT 986462 B IT986462 B IT 986462B IT 68758/73 A IT68758/73 A IT 68758/73A IT 6875873 A IT6875873 A IT 6875873A IT 986462 B IT986462 B IT 986462B
Authority
IT
Italy
Prior art keywords
integpated
circuits
procedure
electrical contacts
making electrical
Prior art date
Application number
IT68758/73A
Other languages
English (en)
Inventor
M Montier
J Lacour
J Suat
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of IT986462B publication Critical patent/IT986462B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
IT68758/73A 1972-06-15 1973-06-14 Procedimento per la realizzazione dei contatti elettrici per circui ti integpati IT986462B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7221657A FR2188304B1 (it) 1972-06-15 1972-06-15

Publications (1)

Publication Number Publication Date
IT986462B true IT986462B (it) 1975-01-30

Family

ID=9100271

Family Applications (1)

Application Number Title Priority Date Filing Date
IT68758/73A IT986462B (it) 1972-06-15 1973-06-14 Procedimento per la realizzazione dei contatti elettrici per circui ti integpati

Country Status (7)

Country Link
US (1) US3930305A (it)
JP (1) JPS588143B2 (it)
DE (1) DE2330645C3 (it)
FR (1) FR2188304B1 (it)
GB (1) GB1440627A (it)
IT (1) IT986462B (it)
NL (1) NL182107C (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621332A (en) * 1979-07-31 1981-02-27 Fujitsu Ltd Manufacture of semiconductor device
DE3828812A1 (de) * 1988-08-25 1990-03-08 Fraunhofer Ges Forschung Dreidimensionale integrierte schaltung und verfahren zu deren herstellung

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3274453A (en) * 1961-02-20 1966-09-20 Philco Corp Semiconductor integrated structures and methods for the fabrication thereof
US3341753A (en) * 1964-10-21 1967-09-12 Texas Instruments Inc Metallic contacts for semiconductor devices
US3667005A (en) * 1966-06-30 1972-05-30 Texas Instruments Inc Ohmic contacts for semiconductors devices
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
US3434020A (en) * 1966-12-30 1969-03-18 Texas Instruments Inc Ohmic contacts consisting of a first level of molybdenum-gold mixture of gold and vanadium and a second level of molybdenum-gold
NL158024B (nl) * 1967-05-13 1978-09-15 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting en halfgeleiderinrichting verkregen door toepassing van de werkwijze.
US3495324A (en) * 1967-11-13 1970-02-17 Sperry Rand Corp Ohmic contact for planar devices
US3642528A (en) * 1968-06-05 1972-02-15 Matsushita Electronics Corp Semiconductor device and method of making same
US3641661A (en) * 1968-06-25 1972-02-15 Texas Instruments Inc Method of fabricating integrated circuit arrays
US3700508A (en) * 1970-06-25 1972-10-24 Gen Instrument Corp Fabrication of integrated microcircuit devices
JPS4851595A (it) * 1971-10-29 1973-07-19

Also Published As

Publication number Publication date
JPS588143B2 (ja) 1983-02-14
NL182107C (nl) 1988-01-04
GB1440627A (en) 1976-06-23
JPS4952589A (it) 1974-05-22
DE2330645A1 (de) 1974-01-24
DE2330645B2 (de) 1976-11-18
NL7308278A (it) 1973-12-18
FR2188304B1 (it) 1977-07-22
DE2330645C3 (de) 1982-07-08
NL182107B (nl) 1987-08-03
FR2188304A1 (it) 1974-01-18
US3930305A (en) 1976-01-06

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