IT8419669A0 - INTEGRATED ELECTRONIC COMPONENT FOR SURFACE ASSEMBLY. - Google Patents
INTEGRATED ELECTRONIC COMPONENT FOR SURFACE ASSEMBLY.Info
- Publication number
- IT8419669A0 IT8419669A0 IT8419669A IT1966984A IT8419669A0 IT 8419669 A0 IT8419669 A0 IT 8419669A0 IT 8419669 A IT8419669 A IT 8419669A IT 1966984 A IT1966984 A IT 1966984A IT 8419669 A0 IT8419669 A0 IT 8419669A0
- Authority
- IT
- Italy
- Prior art keywords
- electronic component
- integrated electronic
- surface assembly
- assembly
- integrated
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT8419669A IT1213140B (en) | 1984-02-17 | 1984-02-17 | INTEGRATED ELECTRONIC COMPONENT FOR SURFACE ASSEMBLY. |
GB08503303A GB2154791A (en) | 1984-02-17 | 1985-02-08 | Packaging semiconductor devices |
DE19853504949 DE3504949A1 (en) | 1984-02-17 | 1985-02-13 | INTEGRATED ELECTRONIC COMPONENT FOR THE SURFACE STRUCTURE |
JP60026633A JPS60233843A (en) | 1984-02-17 | 1985-02-15 | Outer surface structure of integrated circuit |
FR8502261A FR2559955B1 (en) | 1984-02-17 | 1985-02-15 | HOUSING FOR INTEGRATED ELECTRONIC COMPONENT BY SURFACE ASSEMBLY INCLUDING INTEGRATED THERMAL DISSIPATION MEANS |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT8419669A IT1213140B (en) | 1984-02-17 | 1984-02-17 | INTEGRATED ELECTRONIC COMPONENT FOR SURFACE ASSEMBLY. |
Publications (2)
Publication Number | Publication Date |
---|---|
IT8419669A0 true IT8419669A0 (en) | 1984-02-17 |
IT1213140B IT1213140B (en) | 1989-12-14 |
Family
ID=11160247
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT8419669A IT1213140B (en) | 1984-02-17 | 1984-02-17 | INTEGRATED ELECTRONIC COMPONENT FOR SURFACE ASSEMBLY. |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS60233843A (en) |
DE (1) | DE3504949A1 (en) |
FR (1) | FR2559955B1 (en) |
GB (1) | GB2154791A (en) |
IT (1) | IT1213140B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04322452A (en) * | 1991-04-23 | 1992-11-12 | Mitsubishi Electric Corp | Semiconductor device housing container of semiconductor element manufacture of semicondcutor device |
GB2292003A (en) * | 1994-07-29 | 1996-02-07 | Ibm Uk | Direct chip attach |
US5625226A (en) * | 1994-09-19 | 1997-04-29 | International Rectifier Corporation | Surface mount package with improved heat transfer |
JP2924854B2 (en) * | 1997-05-20 | 1999-07-26 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1239634A (en) * | 1968-10-02 | 1971-07-21 | ||
GB1289932A (en) * | 1971-03-30 | 1972-09-20 | ||
US3930114A (en) * | 1975-03-17 | 1975-12-30 | Nat Semiconductor Corp | Integrated circuit package utilizing novel heat sink structure |
GB2022317A (en) * | 1978-05-31 | 1979-12-12 | Burroughs Corp | Method of forming a plastic cavity package for integrated circuit devices |
US4420767A (en) * | 1978-11-09 | 1983-12-13 | Zilog, Inc. | Thermally balanced leadless microelectronic circuit chip carrier |
FR2488445A1 (en) * | 1980-08-06 | 1982-02-12 | Efcis | PLASTIC CASE FOR INTEGRATED CIRCUITS |
US4630172A (en) * | 1983-03-09 | 1986-12-16 | Printed Circuits International | Semiconductor chip carrier package with a heat sink |
-
1984
- 1984-02-17 IT IT8419669A patent/IT1213140B/en active
-
1985
- 1985-02-08 GB GB08503303A patent/GB2154791A/en not_active Withdrawn
- 1985-02-13 DE DE19853504949 patent/DE3504949A1/en not_active Withdrawn
- 1985-02-15 JP JP60026633A patent/JPS60233843A/en active Pending
- 1985-02-15 FR FR8502261A patent/FR2559955B1/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2559955B1 (en) | 1988-01-15 |
GB2154791A (en) | 1985-09-11 |
GB8503303D0 (en) | 1985-03-13 |
IT1213140B (en) | 1989-12-14 |
JPS60233843A (en) | 1985-11-20 |
FR2559955A1 (en) | 1985-08-23 |
DE3504949A1 (en) | 1985-08-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970227 |