IT1400749B1 - Cella sram configurabile dinamicamente per funzionamento a bassa tensione - Google Patents

Cella sram configurabile dinamicamente per funzionamento a bassa tensione

Info

Publication number
IT1400749B1
IT1400749B1 ITMI2010A001194A ITMI20101194A IT1400749B1 IT 1400749 B1 IT1400749 B1 IT 1400749B1 IT MI2010A001194 A ITMI2010A001194 A IT MI2010A001194A IT MI20101194 A ITMI20101194 A IT MI20101194A IT 1400749 B1 IT1400749 B1 IT 1400749B1
Authority
IT
Italy
Prior art keywords
low voltage
voltage operation
cell sram
configurable dynamically
configurable
Prior art date
Application number
ITMI2010A001194A
Other languages
English (en)
Inventor
Danilo Rimondi
Carolina Selva
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITMI2010A001194A priority Critical patent/IT1400749B1/it
Priority to US13/173,333 priority patent/US9263120B2/en
Publication of ITMI20101194A1 publication Critical patent/ITMI20101194A1/it
Application granted granted Critical
Publication of IT1400749B1 publication Critical patent/IT1400749B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Power Sources (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
ITMI2010A001194A 2010-06-30 2010-06-30 Cella sram configurabile dinamicamente per funzionamento a bassa tensione IT1400749B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ITMI2010A001194A IT1400749B1 (it) 2010-06-30 2010-06-30 Cella sram configurabile dinamicamente per funzionamento a bassa tensione
US13/173,333 US9263120B2 (en) 2010-06-30 2011-06-30 Dynamically configurable SRAM cell for low voltage operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI2010A001194A IT1400749B1 (it) 2010-06-30 2010-06-30 Cella sram configurabile dinamicamente per funzionamento a bassa tensione

Publications (2)

Publication Number Publication Date
ITMI20101194A1 ITMI20101194A1 (it) 2011-12-31
IT1400749B1 true IT1400749B1 (it) 2013-07-02

Family

ID=43086907

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI2010A001194A IT1400749B1 (it) 2010-06-30 2010-06-30 Cella sram configurabile dinamicamente per funzionamento a bassa tensione

Country Status (2)

Country Link
US (1) US9263120B2 (it)
IT (1) IT1400749B1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9287370B2 (en) * 2012-03-02 2016-03-15 Semiconductor Energy Laboratory Co., Ltd. Memory device comprising a transistor including an oxide semiconductor and semiconductor device including the same
US9390787B2 (en) * 2013-03-15 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Biasing bulk of a transistor
FR3009125B1 (fr) * 2013-07-24 2019-06-28 Areva Np Glace pour garniture d'etancheite pour systeme d'etancheite d'arbre
US9001571B1 (en) * 2014-01-20 2015-04-07 National Tsing Hua University 6T static random access memory cell, array and memory thereof
US11962928B2 (en) 2018-12-17 2024-04-16 Meta Platforms Technologies, Llc Programmable pixel array
US11888002B2 (en) 2018-12-17 2024-01-30 Meta Platforms Technologies, Llc Dynamically programmable image sensor
US11935291B2 (en) 2019-10-30 2024-03-19 Meta Platforms Technologies, Llc Distributed sensor system
US11948089B2 (en) 2019-11-07 2024-04-02 Meta Platforms Technologies, Llc Sparse image sensing and processing
US11825228B2 (en) 2020-05-20 2023-11-21 Meta Platforms Technologies, Llc Programmable pixel array having multiple power domains
US11935575B1 (en) * 2020-12-23 2024-03-19 Meta Platforms Technologies, Llc Heterogeneous memory system

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5943258A (en) 1997-12-24 1999-08-24 Texas Instruments Incorporated Memory with storage cells having SOI drive and access transistors with tied floating body connections
US6998722B2 (en) 2002-07-08 2006-02-14 Viciciv Technology Semiconductor latches and SRAM devices
US7092279B1 (en) * 2003-03-24 2006-08-15 Sheppard Douglas P Shared bit line memory device and method
TWI244729B (en) 2003-08-28 2005-12-01 Renesas Tech Corp Semiconductor memory device and method of manufacturing the same
JP4287768B2 (ja) * 2004-03-16 2009-07-01 パナソニック株式会社 半導体記憶装置
US7176125B2 (en) 2004-07-23 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a static random access memory with a buried local interconnect
US20070047364A1 (en) * 2005-08-31 2007-03-01 International Business Machines Corporation Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices
JP4822791B2 (ja) * 2005-10-04 2011-11-24 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP2007193928A (ja) * 2005-12-19 2007-08-02 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7711998B2 (en) * 2007-03-30 2010-05-04 Infineon Technologies Ag Test circuit arrangement
US7548365B2 (en) 2007-06-06 2009-06-16 Texas Instruments Incorporated Semiconductor device and method comprising a high voltage reset driver and an isolated memory array
JP2009093702A (ja) 2007-10-04 2009-04-30 Sony Corp 半導体記憶装置及びその駆動方法
JP4844619B2 (ja) * 2008-03-27 2011-12-28 株式会社デンソー 半導体メモリ装置
IT1400750B1 (it) 2010-06-30 2013-07-02 St Microelectronics Srl Memoria sram 5t per applicazioni a bassa tensione

Also Published As

Publication number Publication date
ITMI20101194A1 (it) 2011-12-31
US9263120B2 (en) 2016-02-16
US20120002460A1 (en) 2012-01-05

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