IT1302079B1 - Circuito di pilotaggio a tensione survolata a basso consumo peruna memoria non volatile - Google Patents

Circuito di pilotaggio a tensione survolata a basso consumo peruna memoria non volatile

Info

Publication number
IT1302079B1
IT1302079B1 IT1998TO000165A ITTO980165A IT1302079B1 IT 1302079 B1 IT1302079 B1 IT 1302079B1 IT 1998TO000165 A IT1998TO000165 A IT 1998TO000165A IT TO980165 A ITTO980165 A IT TO980165A IT 1302079 B1 IT1302079 B1 IT 1302079B1
Authority
IT
Italy
Prior art keywords
voltage
volatile memory
low consumption
pilot circuit
consumption voltage
Prior art date
Application number
IT1998TO000165A
Other languages
English (en)
Inventor
Tommaso Zerilli
Maurizio Gaibotti
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT1998TO000165A priority Critical patent/IT1302079B1/it
Priority to US09/257,682 priority patent/US6130844A/en
Publication of ITTO980165A1 publication Critical patent/ITTO980165A1/it
Application granted granted Critical
Publication of IT1302079B1 publication Critical patent/IT1302079B1/it

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
IT1998TO000165A 1998-02-27 1998-02-27 Circuito di pilotaggio a tensione survolata a basso consumo peruna memoria non volatile IT1302079B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT1998TO000165A IT1302079B1 (it) 1998-02-27 1998-02-27 Circuito di pilotaggio a tensione survolata a basso consumo peruna memoria non volatile
US09/257,682 US6130844A (en) 1998-02-27 1999-02-26 Low consumption boosted voltage driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1998TO000165A IT1302079B1 (it) 1998-02-27 1998-02-27 Circuito di pilotaggio a tensione survolata a basso consumo peruna memoria non volatile

Publications (2)

Publication Number Publication Date
ITTO980165A1 ITTO980165A1 (it) 1999-08-27
IT1302079B1 true IT1302079B1 (it) 2000-07-20

Family

ID=11416500

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1998TO000165A IT1302079B1 (it) 1998-02-27 1998-02-27 Circuito di pilotaggio a tensione survolata a basso consumo peruna memoria non volatile

Country Status (2)

Country Link
US (1) US6130844A (it)
IT (1) IT1302079B1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3892612B2 (ja) * 1999-04-09 2007-03-14 株式会社東芝 半導体装置
US6867553B2 (en) * 2003-04-16 2005-03-15 General Electric Company Continuous mode voltage fed inverter

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5265052A (en) * 1989-07-20 1993-11-23 Texas Instruments Incorporated Wordline driver circuit for EEPROM memory cell
JPH08227596A (ja) * 1994-11-30 1996-09-03 Texas Instr Inc <Ti> 半導体メモリ用デコード回路
EP0798742B1 (en) * 1996-03-29 2003-11-12 STMicroelectronics S.r.l. Driver device for selection lines for a multiplexer, to be used in a wide range of supply voltages, particularly for non-volatile memories
US5886541A (en) * 1996-08-05 1999-03-23 Fujitsu Limited Combined logic gate and latch

Also Published As

Publication number Publication date
ITTO980165A1 (it) 1999-08-27
US6130844A (en) 2000-10-10

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Legal Events

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0001 Granted