IT1252025B - Procedimento per la realizzazione di celle di memoria a sola lettura programmabili e cancellabili elettricamente a singolo livello di polisilicio - Google Patents
Procedimento per la realizzazione di celle di memoria a sola lettura programmabili e cancellabili elettricamente a singolo livello di polisilicioInfo
- Publication number
- IT1252025B IT1252025B ITMI913196A ITMI913196A IT1252025B IT 1252025 B IT1252025 B IT 1252025B IT MI913196 A ITMI913196 A IT MI913196A IT MI913196 A ITMI913196 A IT MI913196A IT 1252025 B IT1252025 B IT 1252025B
- Authority
- IT
- Italy
- Prior art keywords
- realization
- procedure
- memory cells
- electrically erasable
- single level
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Procedimento per la realizzazione di celle di memoria a sola lettura programmabili e cancellabili elettricamente a singolo livello di polisilicio la cui peculiarità consiste nel fatto di sfruttare uno strato sacrificale di ossido di silicio per realizzare uno strato di ossido di silicio su area attiva di elevato spessore e di proteggere l'area attiva della cella dell'impianto pesante di source e drain per migliorare l'affidabilità.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITMI913196A IT1252025B (it) | 1991-11-29 | 1991-11-29 | Procedimento per la realizzazione di celle di memoria a sola lettura programmabili e cancellabili elettricamente a singolo livello di polisilicio |
DE69217846T DE69217846T2 (de) | 1991-11-29 | 1992-10-30 | Verfahren zur Herstellung elektrisch-löschbarer und -programmierbarer Nurlesespeicherzellen mit einer einzigen Polysiliziumschicht |
EP92118573A EP0545074B1 (en) | 1991-11-29 | 1992-10-30 | Method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level |
US07/983,799 US5367483A (en) | 1991-11-29 | 1992-11-24 | Electrically erasable and programmable read-only memory cells with a single polysilicon level and method for producing the same |
JP4318539A JPH06196662A (ja) | 1991-11-29 | 1992-11-27 | 同一のポリシリコンレベルを有する電気的消去書込み可能な読み出し専用メモリセルの製造方法 |
US08/310,836 US5553017A (en) | 1991-11-29 | 1994-09-22 | Electrically erasable and programmable read-only memory cells with a single polysilicon level and method for producing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITMI913196A IT1252025B (it) | 1991-11-29 | 1991-11-29 | Procedimento per la realizzazione di celle di memoria a sola lettura programmabili e cancellabili elettricamente a singolo livello di polisilicio |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI913196A0 ITMI913196A0 (it) | 1991-11-29 |
ITMI913196A1 ITMI913196A1 (it) | 1993-05-29 |
IT1252025B true IT1252025B (it) | 1995-05-27 |
Family
ID=11361219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI913196A IT1252025B (it) | 1991-11-29 | 1991-11-29 | Procedimento per la realizzazione di celle di memoria a sola lettura programmabili e cancellabili elettricamente a singolo livello di polisilicio |
Country Status (5)
Country | Link |
---|---|
US (2) | US5367483A (it) |
EP (1) | EP0545074B1 (it) |
JP (1) | JPH06196662A (it) |
DE (1) | DE69217846T2 (it) |
IT (1) | IT1252025B (it) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3228230B2 (ja) * | 1998-07-21 | 2001-11-12 | 日本電気株式会社 | 半導体装置の製造方法 |
US6143608A (en) * | 1999-03-31 | 2000-11-07 | Advanced Micro Devices, Inc. | Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation |
US6753590B2 (en) * | 2002-07-08 | 2004-06-22 | International Business Machines Corporation | High impedance antifuse |
US20200091561A1 (en) * | 2018-09-17 | 2020-03-19 | ZAF Energy Systems, Incorporated | Zinc alkaline secondary battery including anchored electrolyte additives |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4047974A (en) * | 1975-12-30 | 1977-09-13 | Hughes Aircraft Company | Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states |
JPS56120166A (en) * | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
JPS57155769A (en) * | 1981-03-20 | 1982-09-25 | Fujitsu Ltd | Manufacture of semiconductor device |
IT1191558B (it) * | 1986-04-21 | 1988-03-23 | Sgs Microelettronica Spa | Dispositivo a semiconduttore integrato di tipo mos con spessore dell'ossido di porta non uniforme e procedimento di fabbricazione dello stesso |
IT1198109B (it) * | 1986-11-18 | 1988-12-21 | Sgs Microelettronica Spa | Cella di memoria eeprom a singolo livello di polisilicio con zona di ossido di tunnel |
JPS63144559A (ja) * | 1986-12-09 | 1988-06-16 | Toshiba Corp | 半導体集積回路 |
JPH03107543A (ja) * | 1989-09-20 | 1991-05-07 | Nippondenso Co Ltd | 燃料噴射時期調整装置 |
US5254489A (en) * | 1990-10-18 | 1993-10-19 | Nec Corporation | Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation |
US5355332A (en) * | 1990-10-23 | 1994-10-11 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with an array of one-transistor memory cells |
-
1991
- 1991-11-29 IT ITMI913196A patent/IT1252025B/it active IP Right Grant
-
1992
- 1992-10-30 EP EP92118573A patent/EP0545074B1/en not_active Expired - Lifetime
- 1992-10-30 DE DE69217846T patent/DE69217846T2/de not_active Expired - Fee Related
- 1992-11-24 US US07/983,799 patent/US5367483A/en not_active Expired - Lifetime
- 1992-11-27 JP JP4318539A patent/JPH06196662A/ja active Pending
-
1994
- 1994-09-22 US US08/310,836 patent/US5553017A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69217846D1 (de) | 1997-04-10 |
ITMI913196A0 (it) | 1991-11-29 |
JPH06196662A (ja) | 1994-07-15 |
US5367483A (en) | 1994-11-22 |
EP0545074B1 (en) | 1997-03-05 |
EP0545074A2 (en) | 1993-06-09 |
ITMI913196A1 (it) | 1993-05-29 |
US5553017A (en) | 1996-09-03 |
EP0545074A3 (en) | 1993-08-18 |
DE69217846T2 (de) | 1997-06-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19971129 |