IT1227821B - Struttura di catena di contatti per il controllo della difettosita' di circuiti di memorie eprom - Google Patents

Struttura di catena di contatti per il controllo della difettosita' di circuiti di memorie eprom

Info

Publication number
IT1227821B
IT1227821B IT8823150A IT2315088A IT1227821B IT 1227821 B IT1227821 B IT 1227821B IT 8823150 A IT8823150 A IT 8823150A IT 2315088 A IT2315088 A IT 2315088A IT 1227821 B IT1227821 B IT 1227821B
Authority
IT
Italy
Prior art keywords
defectivity
circuits
contacts
chain
control
Prior art date
Application number
IT8823150A
Other languages
English (en)
Other versions
IT8823150A0 (it
Inventor
Marco Ivano Buraschi
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8823150A priority Critical patent/IT1227821B/it
Publication of IT8823150A0 publication Critical patent/IT8823150A0/it
Priority to EP19890121332 priority patent/EP0375915A3/en
Priority to JP1336788A priority patent/JPH02290054A/ja
Application granted granted Critical
Publication of IT1227821B publication Critical patent/IT1227821B/it
Priority to US07/782,894 priority patent/US5165066A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Non-Volatile Memory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT8823150A 1988-12-29 1988-12-29 Struttura di catena di contatti per il controllo della difettosita' di circuiti di memorie eprom IT1227821B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT8823150A IT1227821B (it) 1988-12-29 1988-12-29 Struttura di catena di contatti per il controllo della difettosita' di circuiti di memorie eprom
EP19890121332 EP0375915A3 (en) 1988-12-29 1989-11-17 A contact chain structure for troubleshooting eprom memory circuits
JP1336788A JPH02290054A (ja) 1988-12-29 1989-12-27 Ｅｐｒｏｍメモリ回路トラブルシューティング用コンタクトチェーン構造
US07/782,894 US5165066A (en) 1988-12-29 1991-10-22 Contact chain structure for troubleshooting eprom memory circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8823150A IT1227821B (it) 1988-12-29 1988-12-29 Struttura di catena di contatti per il controllo della difettosita' di circuiti di memorie eprom

Publications (2)

Publication Number Publication Date
IT8823150A0 IT8823150A0 (it) 1988-12-29
IT1227821B true IT1227821B (it) 1991-05-07

Family

ID=11204315

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8823150A IT1227821B (it) 1988-12-29 1988-12-29 Struttura di catena di contatti per il controllo della difettosita' di circuiti di memorie eprom

Country Status (4)

Country Link
US (1) US5165066A (it)
EP (1) EP0375915A3 (it)
JP (1) JPH02290054A (it)
IT (1) IT1227821B (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0157900B1 (ko) * 1995-10-02 1999-03-20 문정환 집적 회로내의 입출력 장치
DE10118402A1 (de) * 2001-04-12 2002-10-24 Promos Technologies Inc Kontaktkette für das Testen und deren relevantes Fehlerbeseitungsverfahren
KR100440071B1 (ko) * 2001-12-04 2004-07-14 주식회사 하이닉스반도체 반도체 소자의 테스트 패턴
DE102007063229B4 (de) * 2007-12-31 2013-01-24 Advanced Micro Devices, Inc. Verfahren und Teststruktur zur Überwachung von Prozesseigenschaften für die Herstellung eingebetteter Halbleiterlegierungen in Drain/Source-Gebieten

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1357515A (en) * 1972-03-10 1974-06-26 Matsushita Electronics Corp Method for manufacturing an mos integrated circuit
US4145701A (en) * 1974-09-11 1979-03-20 Hitachi, Ltd. Semiconductor device
US4017888A (en) * 1975-12-31 1977-04-12 International Business Machines Corporation Non-volatile metal nitride oxide semiconductor device
JPS5833708B2 (ja) * 1977-01-31 1983-07-21 株式会社東芝 集積回路装置
US4276095A (en) * 1977-08-31 1981-06-30 International Business Machines Corporation Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations
JPS5850771A (ja) * 1981-09-21 1983-03-25 Hitachi Ltd 再書込み可能な高集積ｒｏｍ及びその製造方法
US4830974A (en) * 1988-01-11 1989-05-16 Atmel Corporation EPROM fabrication process
US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
US4859619A (en) * 1988-07-15 1989-08-22 Atmel Corporation EPROM fabrication process forming tub regions for high voltage devices

Also Published As

Publication number Publication date
IT8823150A0 (it) 1988-12-29
US5165066A (en) 1992-11-17
EP0375915A2 (en) 1990-07-04
JPH02290054A (ja) 1990-11-29
EP0375915A3 (en) 1991-08-14

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227