IT1140489B - Sistema di elaborazione dei dati,decentrato e a struttura modulare - Google Patents

Sistema di elaborazione dei dati,decentrato e a struttura modulare

Info

Publication number
IT1140489B
IT1140489B IT24991/81A IT2499181A IT1140489B IT 1140489 B IT1140489 B IT 1140489B IT 24991/81 A IT24991/81 A IT 24991/81A IT 2499181 A IT2499181 A IT 2499181A IT 1140489 B IT1140489 B IT 1140489B
Authority
IT
Italy
Prior art keywords
decentralized
data processing
processing system
structure data
modular structure
Prior art date
Application number
IT24991/81A
Other languages
English (en)
Other versions
IT8124991A0 (it
Inventor
Andreas Meyer
Werner Zucker
Original Assignee
Stollmann & Co Gmbh
Triumph Adler Buero Inf
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stollmann & Co Gmbh, Triumph Adler Buero Inf filed Critical Stollmann & Co Gmbh
Publication of IT8124991A0 publication Critical patent/IT8124991A0/it
Application granted granted Critical
Publication of IT1140489B publication Critical patent/IT1140489B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
IT24991/81A 1981-03-31 1981-11-12 Sistema di elaborazione dei dati,decentrato e a struttura modulare IT1140489B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19813112693 DE3112693A1 (de) 1981-03-31 1981-03-31 Modular aufgebautes dezentrales datenverarbeitungssystem

Publications (2)

Publication Number Publication Date
IT8124991A0 IT8124991A0 (it) 1981-11-12
IT1140489B true IT1140489B (it) 1986-09-24

Family

ID=6128793

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24991/81A IT1140489B (it) 1981-03-31 1981-11-12 Sistema di elaborazione dei dati,decentrato e a struttura modulare

Country Status (7)

Country Link
JP (1) JPS57209561A (it)
DE (1) DE3112693A1 (it)
FR (1) FR2503420A1 (it)
GB (1) GB2096369A (it)
IT (1) IT1140489B (it)
NL (1) NL8104891A (it)
SE (1) SE8200314L (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2538140B1 (fr) * 1982-12-21 1988-06-24 Thomson Csf Mat Tel Dispositif de couplage de bus pour systeme de traitement de donnees a bus multiples
ATE74675T1 (de) * 1983-04-25 1992-04-15 Cray Research Inc Mehrprozessorsteuerung fuer vektorrechner.
US4751637A (en) * 1984-03-28 1988-06-14 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
US4814983A (en) * 1984-03-28 1989-03-21 Daisy Systems Corporation Digital computer for implementing event driven simulation algorithm
US4870704A (en) * 1984-10-31 1989-09-26 Flexible Computer Corporation Multicomputer digital processing system
GB2195038A (en) * 1986-07-05 1988-03-23 Narayanaswamy D Jayaram A multi-microprocessor system with confederate processors
US4873656A (en) * 1987-06-26 1989-10-10 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4872125A (en) * 1987-06-26 1989-10-03 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4916647A (en) * 1987-06-26 1990-04-10 Daisy Systems Corporation Hardwired pipeline processor for logic simulation
GB2433396B (en) 2005-12-15 2010-06-23 Bridgeworks Ltd A bridge

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1287657A (en) * 1969-07-09 1972-09-06 Burroughs Corp Apparatus for signalling peripheral unit configuration within computer system
US3662401A (en) * 1970-09-23 1972-05-09 Collins Radio Co Method of program execution
US3805247A (en) * 1972-05-16 1974-04-16 Burroughs Corp Description driven microprogrammable multiprocessor system
US4257099A (en) * 1975-10-14 1981-03-17 Texas Instruments Incorporated Communication bus coupler
GB1561962A (en) * 1977-04-29 1980-03-05 Int Computers Ltd Data processing systems
US4223380A (en) * 1978-04-06 1980-09-16 Ncr Corporation Distributed multiprocessor communication system
JPS5840214B2 (ja) * 1979-06-26 1983-09-03 株式会社東芝 計算機システム

Also Published As

Publication number Publication date
DE3112693A1 (de) 1982-10-14
IT8124991A0 (it) 1981-11-12
FR2503420A1 (fr) 1982-10-08
NL8104891A (nl) 1982-10-18
JPS57209561A (en) 1982-12-22
SE8200314L (sv) 1982-10-01
GB2096369A (en) 1982-10-13

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