GB1287657A - Apparatus for signalling peripheral unit configuration within computer system - Google Patents

Abstract

1287657 Data processing systems BURROUGHS CORP 2 April 1970 [9 July 1969] 15585/70 Heading G4A A data processing system has a high speed memory, a number of data storing peripheral units of different types, and an apparatus for providing information to the processor as to the types of peripheral unit connected in the system and whether a communication path is available to a particular unit, the apparatus including a gating circuit operative to energize one or more of a number of output lines each corresponding to a particular peripheral unit, and a comparator responsive to the presence of output signals from the gating circuit and NOT BUSY signals from corresponding peripheral unit control units to produce a signal which is passed to the processor. As described the peripherals may be magnetic tape units, printers &c. and three modes of operation are described. Interrogate peripheral unit type.-A word is placed in the A register 24 which is the top register in a stack memory. A group of bits identifying the word as an "interrogate peripheral unit type" command are decoded and used to gate via gate 26 a further group of bits in the word specifying a particular multiplexor and a channel number to the control lines of the scanbus. These bits are applied to a decoder 28 and via a gate 32 to the gating circuit 34. The gate 32 is enabled by the TYPE output of the decoder and the circuit 34 energizes one or more of its outputs 1-20 in response to the channel designation. The lines 1-20 are connected to respective printed circuit boards 36-40 which generate a coded output specifying the type of peripheral connected to the designated channel. Interrogate peripheral path.-This command verifies the availability of a designated channel. A word is loaded in the A register 24 as above and the operation is similar except that the PATH output of decoder 28 is energized. The outputs 1-20 of the gating circuit 34 pass via AND gates 42-46 respectively which are enabled by the PATH output and also by NOT BUSY signals from the control units associated with the peripherals connected to channels 1-20. The outputs of gates 42-46 are gated to the processor via gate 48. Interrogate status.-This command verifies the availability of the selected peripheral unit, the STATUS output of the decoder 28 being energized as above. A group of bits specifying one of the groups of READY lines from the peripheral units is passed to the decoder 56 which is activated in response to the STATUS output. The READY signals verify the status of the peripheral units and are utilized by the decoder 56 to generate control signals which are applied to the corresponding ones of the gates 50, 52, 54. The selected READY signals are thus gated to the processor. The system may provide for avoiding interrogation of all the READY signals by passing each group of such signals through a corresponding inverter 58, 60, 62 to the gating circuit associated with the next lower order group of READY signals. The output of the inverters indicate that none of the peripheral units is ready and a particular bit in the A-register 24 is set accordingly. The controlling program in response to setting of this bit, inhibits further interrogation.